xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts (revision e7d759f31ca295d589f7420719c311870bb3166f) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
4 *
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
6 *
7 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17
18/ {
19	model = "ZynqMP zc1751-xm019-dc5 RevA";
20	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem1;
24		i2c0 = &i2c0;
25		i2c1 = &i2c1;
26		mmc0 = &sdhci0;
27		serial0 = &uart0;
28		serial1 = &uart1;
29	};
30
31	chosen {
32		bootargs = "earlycon";
33		stdout-path = "serial0:115200n8";
34	};
35
36	memory@0 {
37		device_type = "memory";
38		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
39	};
40};
41
42&fpd_dma_chan1 {
43	status = "okay";
44};
45
46&fpd_dma_chan2 {
47	status = "okay";
48};
49
50&fpd_dma_chan3 {
51	status = "okay";
52};
53
54&fpd_dma_chan4 {
55	status = "okay";
56};
57
58&fpd_dma_chan5 {
59	status = "okay";
60};
61
62&fpd_dma_chan6 {
63	status = "okay";
64};
65
66&fpd_dma_chan7 {
67	status = "okay";
68};
69
70&fpd_dma_chan8 {
71	status = "okay";
72};
73
74&gem1 {
75	status = "okay";
76	phy-handle = <&phy0>;
77	phy-mode = "rgmii-id";
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_gem1_default>;
80	mdio: mdio {
81		#address-cells = <1>;
82		#size-cells = <0>;
83		phy0: ethernet-phy@0 {
84			reg = <0>;
85		};
86	};
87};
88
89&gpio {
90	status = "okay";
91};
92
93&i2c0 {
94	status = "okay";
95	pinctrl-names = "default", "gpio";
96	pinctrl-0 = <&pinctrl_i2c0_default>;
97	pinctrl-1 = <&pinctrl_i2c0_gpio>;
98	scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
99	sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
100};
101
102&i2c1 {
103	status = "okay";
104	pinctrl-names = "default", "gpio";
105	pinctrl-0 = <&pinctrl_i2c1_default>;
106	pinctrl-1 = <&pinctrl_i2c1_gpio>;
107	scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
108	sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
109
110};
111
112&pinctrl0 {
113	status = "okay";
114	pinctrl_i2c0_default: i2c0-default {
115		mux {
116			groups = "i2c0_18_grp";
117			function = "i2c0";
118		};
119
120		conf {
121			groups = "i2c0_18_grp";
122			bias-pull-up;
123			slew-rate = <SLEW_RATE_SLOW>;
124			power-source = <IO_STANDARD_LVCMOS18>;
125		};
126	};
127
128	pinctrl_i2c0_gpio: i2c0-gpio {
129		mux {
130			groups = "gpio0_74_grp", "gpio0_75_grp";
131			function = "gpio0";
132		};
133
134		conf {
135			groups = "gpio0_74_grp", "gpio0_75_grp";
136			slew-rate = <SLEW_RATE_SLOW>;
137			power-source = <IO_STANDARD_LVCMOS18>;
138		};
139	};
140
141	pinctrl_i2c1_default: i2c1-default {
142		mux {
143			groups = "i2c1_19_grp";
144			function = "i2c1";
145		};
146
147		conf {
148			groups = "i2c1_19_grp";
149			bias-pull-up;
150			slew-rate = <SLEW_RATE_SLOW>;
151			power-source = <IO_STANDARD_LVCMOS18>;
152		};
153	};
154
155	pinctrl_i2c1_gpio: i2c1-gpio {
156		mux {
157			groups = "gpio0_76_grp", "gpio0_77_grp";
158			function = "gpio0";
159		};
160
161		conf {
162			groups = "gpio0_76_grp", "gpio0_77_grp";
163			slew-rate = <SLEW_RATE_SLOW>;
164			power-source = <IO_STANDARD_LVCMOS18>;
165		};
166	};
167
168	pinctrl_uart0_default: uart0-default {
169		mux {
170			groups = "uart0_17_grp";
171			function = "uart0";
172		};
173
174		conf {
175			groups = "uart0_17_grp";
176			slew-rate = <SLEW_RATE_SLOW>;
177			power-source = <IO_STANDARD_LVCMOS18>;
178		};
179
180		conf-rx {
181			pins = "MIO70";
182			bias-high-impedance;
183		};
184
185		conf-tx {
186			pins = "MIO71";
187			bias-disable;
188		};
189	};
190
191	pinctrl_uart1_default: uart1-default {
192		mux {
193			groups = "uart1_18_grp";
194			function = "uart1";
195		};
196
197		conf {
198			groups = "uart1_18_grp";
199			slew-rate = <SLEW_RATE_SLOW>;
200			power-source = <IO_STANDARD_LVCMOS18>;
201		};
202
203		conf-rx {
204			pins = "MIO73";
205			bias-high-impedance;
206		};
207
208		conf-tx {
209			pins = "MIO72";
210			bias-disable;
211		};
212	};
213
214	pinctrl_gem1_default: gem1-default {
215		mux {
216			function = "ethernet1";
217			groups = "ethernet1_0_grp";
218		};
219
220		conf {
221			groups = "ethernet1_0_grp";
222			slew-rate = <SLEW_RATE_SLOW>;
223			power-source = <IO_STANDARD_LVCMOS18>;
224		};
225
226		conf-rx {
227			pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
228									"MIO49";
229			bias-high-impedance;
230			low-power-disable;
231		};
232
233		conf-tx {
234			pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
235									"MIO43";
236			bias-disable;
237			low-power-enable;
238		};
239
240		mux-mdio {
241			function = "mdio1";
242			groups = "mdio1_0_grp";
243		};
244
245		conf-mdio {
246			groups = "mdio1_0_grp";
247			slew-rate = <SLEW_RATE_SLOW>;
248			power-source = <IO_STANDARD_LVCMOS18>;
249			bias-disable;
250		};
251	};
252
253	pinctrl_sdhci0_default: sdhci0-default {
254		mux {
255			groups = "sdio0_0_grp";
256			function = "sdio0";
257		};
258
259		conf {
260			groups = "sdio0_0_grp";
261			slew-rate = <SLEW_RATE_SLOW>;
262			power-source = <IO_STANDARD_LVCMOS18>;
263			bias-disable;
264		};
265
266		mux-cd {
267			groups = "sdio0_cd_0_grp";
268			function = "sdio0_cd";
269		};
270
271		conf-cd {
272			groups = "sdio0_cd_0_grp";
273			bias-high-impedance;
274			bias-pull-up;
275			slew-rate = <SLEW_RATE_SLOW>;
276			power-source = <IO_STANDARD_LVCMOS18>;
277		};
278
279		mux-wp {
280			groups = "sdio0_wp_0_grp";
281			function = "sdio0_wp";
282		};
283
284		conf-wp {
285			groups = "sdio0_wp_0_grp";
286			bias-high-impedance;
287			bias-pull-up;
288			slew-rate = <SLEW_RATE_SLOW>;
289			power-source = <IO_STANDARD_LVCMOS18>;
290		};
291	};
292
293	pinctrl_watchdog0_default: watchdog0-default {
294		mux-clk {
295			groups = "swdt0_clk_1_grp";
296			function = "swdt0_clk";
297		};
298
299		conf-clk {
300			groups = "swdt0_clk_1_grp";
301			bias-pull-up;
302		};
303
304		mux-rst {
305			groups = "swdt0_rst_1_grp";
306			function = "swdt0_rst";
307		};
308
309		conf-rst {
310			groups = "swdt0_rst_1_grp";
311			bias-disable;
312			slew-rate = <SLEW_RATE_SLOW>;
313		};
314	};
315
316	pinctrl_ttc0_default: ttc0-default {
317		mux-clk {
318			groups = "ttc0_clk_0_grp";
319			function = "ttc0_clk";
320		};
321
322		conf-clk {
323			groups = "ttc0_clk_0_grp";
324			bias-pull-up;
325		};
326
327		mux-wav {
328			groups = "ttc0_wav_0_grp";
329			function = "ttc0_wav";
330		};
331
332		conf-wav {
333			groups = "ttc0_wav_0_grp";
334			bias-disable;
335			slew-rate = <SLEW_RATE_SLOW>;
336		};
337	};
338
339	pinctrl_ttc1_default: ttc1-default {
340		mux-clk {
341			groups = "ttc1_clk_0_grp";
342			function = "ttc1_clk";
343		};
344
345		conf-clk {
346			groups = "ttc1_clk_0_grp";
347			bias-pull-up;
348		};
349
350		mux-wav {
351			groups = "ttc1_wav_0_grp";
352			function = "ttc1_wav";
353		};
354
355		conf-wav {
356			groups = "ttc1_wav_0_grp";
357			bias-disable;
358			slew-rate = <SLEW_RATE_SLOW>;
359		};
360	};
361
362	pinctrl_ttc2_default: ttc2-default {
363		mux-clk {
364			groups = "ttc2_clk_0_grp";
365			function = "ttc2_clk";
366		};
367
368		conf-clk {
369			groups = "ttc2_clk_0_grp";
370			bias-pull-up;
371		};
372
373		mux-wav {
374			groups = "ttc2_wav_0_grp";
375			function = "ttc2_wav";
376		};
377
378		conf-wav {
379			groups = "ttc2_wav_0_grp";
380			bias-disable;
381			slew-rate = <SLEW_RATE_SLOW>;
382		};
383	};
384
385	pinctrl_ttc3_default: ttc3-default {
386		mux-clk {
387			groups = "ttc3_clk_0_grp";
388			function = "ttc3_clk";
389		};
390
391		conf-clk {
392			groups = "ttc3_clk_0_grp";
393			bias-pull-up;
394		};
395
396		mux-wav {
397			groups = "ttc3_wav_0_grp";
398			function = "ttc3_wav";
399		};
400
401		conf-wav {
402			groups = "ttc3_wav_0_grp";
403			bias-disable;
404			slew-rate = <SLEW_RATE_SLOW>;
405		};
406	};
407};
408
409&sdhci0 {
410	status = "okay";
411	pinctrl-names = "default";
412	pinctrl-0 = <&pinctrl_sdhci0_default>;
413	no-1-8-v;
414	xlnx,mio-bank = <0>;
415};
416
417&ttc0 {
418	status = "okay";
419	pinctrl-names = "default";
420	pinctrl-0 = <&pinctrl_ttc0_default>;
421};
422
423&ttc1 {
424	status = "okay";
425	pinctrl-names = "default";
426	pinctrl-0 = <&pinctrl_ttc1_default>;
427};
428
429&ttc2 {
430	status = "okay";
431	pinctrl-names = "default";
432	pinctrl-0 = <&pinctrl_ttc2_default>;
433};
434
435&ttc3 {
436	status = "okay";
437	pinctrl-names = "default";
438	pinctrl-0 = <&pinctrl_ttc3_default>;
439};
440
441&uart0 {
442	status = "okay";
443	pinctrl-names = "default";
444	pinctrl-0 = <&pinctrl_uart0_default>;
445};
446
447&uart1 {
448	status = "okay";
449	pinctrl-names = "default";
450	pinctrl-0 = <&pinctrl_uart1_default>;
451};
452
453&watchdog0 {
454	status = "okay";
455	pinctrl-names = "default";
456	pinctrl-0 = <&pinctrl_watchdog0_default>;
457};
458