xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts (revision 2da2ac3c8d11bd57cf00d06985a3d9ca5969abae)

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>

/ {
	model = "ZynqMP zc1751-xm017-dc3 RevA";
	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdhci1;
		rtc0 = &rtc;
		serial0 = &uart0;
		serial1 = &uart1;
		usb0 = &usb0;
		usb1 = &usb1;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
	};

	clock_si5338_2: clk26 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	clock_si5338_3: clk125 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
	};
};

&fpd_dma_chan1 {
	status = "okay";
};

&fpd_dma_chan2 {
	status = "okay";
};

&fpd_dma_chan3 {
	status = "okay";
};

&fpd_dma_chan4 {
	status = "okay";
};

&fpd_dma_chan5 {
	status = "okay";
};

&fpd_dma_chan6 {
	status = "okay";
};

&fpd_dma_chan7 {
	status = "okay";
};

&fpd_dma_chan8 {
	status = "okay";
};

&gem0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@0 { /* VSC8211 */
			reg = <0>;
		};
	};
};

&gpio {
	status = "okay";
};

/* just eeprom here */
&i2c0 {
	status = "okay";
	clock-frequency = <400000>;

	tca6416_u26: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		/* IRQ not connected */
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

/* eeprom24c02 and SE98A temp chip pca9306 */
&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
};

/* MT29F64G08AECDBJ4-6 */
&nand0 {
	status = "okay";
	arasan,has-mdma;
	num-cs = <2>;
};

&psgtr {
	status = "okay";
	/* usb3, sata */
	clocks = <&clock_si5338_2>, <&clock_si5338_3>;
	clock-names = "ref2", "ref3";
};

&rtc {
	status = "okay";
};

&sata {
	status = "okay";
	/* SATA phy OOB timing settings */
	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	phy-names = "sata-phy";
	phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
};

&sdhci1 { /* emmc with some settings */
	status = "okay";
};

/* main */
&uart0 {
	status = "okay";
};

/* DB9 */
&uart1 {
	status = "okay";
};

&usb0 {
	status = "okay";
	phy-names = "usb3-phy";
	phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
};

&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};

/* ULPI SMSC USB3320 */
&usb1 {
	status = "okay";
	phy-names = "usb3-phy";
	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
};

&dwc3_1 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};