1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2 4 * 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11/dts-v1/; 12 13#include "zynqmp.dtsi" 14#include "zynqmp-clk-ccf.dtsi" 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17 18/ { 19 model = "ZynqMP zc1751-xm016-dc2 RevA"; 20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 21 22 aliases { 23 ethernet0 = &gem2; 24 i2c0 = &i2c0; 25 rtc0 = &rtc; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 spi0 = &spi0; 29 spi1 = &spi1; 30 usb0 = &usb1; 31 }; 32 33 chosen { 34 bootargs = "earlycon"; 35 stdout-path = "serial0:115200n8"; 36 }; 37 38 memory@0 { 39 device_type = "memory"; 40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 41 }; 42}; 43 44&can0 { 45 status = "okay"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_can0_default>; 48}; 49 50&can1 { 51 status = "okay"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_can1_default>; 54}; 55 56&fpd_dma_chan1 { 57 status = "okay"; 58}; 59 60&fpd_dma_chan2 { 61 status = "okay"; 62}; 63 64&fpd_dma_chan3 { 65 status = "okay"; 66}; 67 68&fpd_dma_chan4 { 69 status = "okay"; 70}; 71 72&fpd_dma_chan5 { 73 status = "okay"; 74}; 75 76&fpd_dma_chan6 { 77 status = "okay"; 78}; 79 80&fpd_dma_chan7 { 81 status = "okay"; 82}; 83 84&fpd_dma_chan8 { 85 status = "okay"; 86}; 87 88&gem2 { 89 status = "okay"; 90 phy-handle = <&phy0>; 91 phy-mode = "rgmii-id"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_gem2_default>; 94 mdio: mdio { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 phy0: ethernet-phy@5 { 98 reg = <5>; 99 ti,rx-internal-delay = <0x8>; 100 ti,tx-internal-delay = <0xa>; 101 ti,fifo-depth = <0x1>; 102 ti,dp83867-rxctrl-strap-quirk; 103 }; 104 }; 105}; 106 107&gpio { 108 status = "okay"; 109}; 110 111&i2c0 { 112 status = "okay"; 113 clock-frequency = <400000>; 114 pinctrl-names = "default", "gpio"; 115 pinctrl-0 = <&pinctrl_i2c0_default>; 116 pinctrl-1 = <&pinctrl_i2c0_gpio>; 117 scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 118 sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 119 120 tca6416_u26: gpio@20 { 121 compatible = "ti,tca6416"; 122 reg = <0x20>; 123 gpio-controller; 124 #gpio-cells = <2>; 125 /* IRQ not connected */ 126 }; 127 128 rtc@68 { 129 compatible = "dallas,ds1339"; 130 reg = <0x68>; 131 }; 132}; 133 134&nand0 { 135 status = "okay"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_nand0_default>; 138 139 nand@0 { 140 reg = <0x0>; 141 #address-cells = <0x2>; 142 #size-cells = <0x1>; 143 nand-ecc-mode = "soft"; 144 nand-ecc-algo = "bch"; 145 nand-rb = <0>; 146 label = "main-storage-0"; 147 }; 148 nand@1 { 149 reg = <0x1>; 150 #address-cells = <0x2>; 151 #size-cells = <0x1>; 152 nand-ecc-mode = "soft"; 153 nand-ecc-algo = "bch"; 154 nand-rb = <0>; 155 label = "main-storage-1"; 156 }; 157}; 158 159&pinctrl0 { 160 status = "okay"; 161 pinctrl_can0_default: can0-default { 162 mux { 163 function = "can0"; 164 groups = "can0_9_grp"; 165 }; 166 167 conf { 168 groups = "can0_9_grp"; 169 slew-rate = <SLEW_RATE_SLOW>; 170 power-source = <IO_STANDARD_LVCMOS18>; 171 }; 172 173 conf-rx { 174 pins = "MIO38"; 175 bias-high-impedance; 176 }; 177 178 conf-tx { 179 pins = "MIO39"; 180 bias-disable; 181 }; 182 }; 183 184 pinctrl_can1_default: can1-default { 185 mux { 186 function = "can1"; 187 groups = "can1_8_grp"; 188 }; 189 190 conf { 191 groups = "can1_8_grp"; 192 slew-rate = <SLEW_RATE_SLOW>; 193 power-source = <IO_STANDARD_LVCMOS18>; 194 }; 195 196 conf-rx { 197 pins = "MIO33"; 198 bias-high-impedance; 199 }; 200 201 conf-tx { 202 pins = "MIO32"; 203 bias-disable; 204 }; 205 }; 206 207 pinctrl_i2c0_default: i2c0-default { 208 mux { 209 groups = "i2c0_1_grp"; 210 function = "i2c0"; 211 }; 212 213 conf { 214 groups = "i2c0_1_grp"; 215 bias-pull-up; 216 slew-rate = <SLEW_RATE_SLOW>; 217 power-source = <IO_STANDARD_LVCMOS18>; 218 }; 219 }; 220 221 pinctrl_i2c0_gpio: i2c0-gpio-grp { 222 mux { 223 groups = "gpio0_6_grp", "gpio0_7_grp"; 224 function = "gpio0"; 225 }; 226 227 conf { 228 groups = "gpio0_6_grp", "gpio0_7_grp"; 229 slew-rate = <SLEW_RATE_SLOW>; 230 power-source = <IO_STANDARD_LVCMOS18>; 231 }; 232 }; 233 234 pinctrl_uart0_default: uart0-default { 235 mux { 236 groups = "uart0_10_grp"; 237 function = "uart0"; 238 }; 239 240 conf { 241 groups = "uart0_10_grp"; 242 slew-rate = <SLEW_RATE_SLOW>; 243 power-source = <IO_STANDARD_LVCMOS18>; 244 }; 245 246 conf-rx { 247 pins = "MIO42"; 248 bias-high-impedance; 249 }; 250 251 conf-tx { 252 pins = "MIO43"; 253 bias-disable; 254 }; 255 }; 256 257 pinctrl_uart1_default: uart1-default { 258 mux { 259 groups = "uart1_10_grp"; 260 function = "uart1"; 261 }; 262 263 conf { 264 groups = "uart1_10_grp"; 265 slew-rate = <SLEW_RATE_SLOW>; 266 power-source = <IO_STANDARD_LVCMOS18>; 267 }; 268 269 conf-rx { 270 pins = "MIO41"; 271 bias-high-impedance; 272 }; 273 274 conf-tx { 275 pins = "MIO40"; 276 bias-disable; 277 }; 278 }; 279 280 pinctrl_usb1_default: usb1-default { 281 mux { 282 groups = "usb1_0_grp"; 283 function = "usb1"; 284 }; 285 286 conf { 287 groups = "usb1_0_grp"; 288 power-source = <IO_STANDARD_LVCMOS18>; 289 }; 290 291 conf-rx { 292 pins = "MIO64", "MIO65", "MIO67"; 293 bias-high-impedance; 294 drive-strength = <12>; 295 slew-rate = <SLEW_RATE_FAST>; 296 }; 297 298 conf-tx { 299 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", 300 "MIO72", "MIO73", "MIO74", "MIO75"; 301 bias-disable; 302 drive-strength = <4>; 303 slew-rate = <SLEW_RATE_SLOW>; 304 }; 305 }; 306 307 pinctrl_gem2_default: gem2-default { 308 mux { 309 function = "ethernet2"; 310 groups = "ethernet2_0_grp"; 311 }; 312 313 conf { 314 groups = "ethernet2_0_grp"; 315 slew-rate = <SLEW_RATE_SLOW>; 316 power-source = <IO_STANDARD_LVCMOS18>; 317 }; 318 319 conf-rx { 320 pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", 321 "MIO63"; 322 bias-high-impedance; 323 low-power-disable; 324 }; 325 326 conf-tx { 327 pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", 328 "MIO57"; 329 bias-disable; 330 low-power-enable; 331 }; 332 333 mux-mdio { 334 function = "mdio2"; 335 groups = "mdio2_0_grp"; 336 }; 337 338 conf-mdio { 339 groups = "mdio2_0_grp"; 340 slew-rate = <SLEW_RATE_SLOW>; 341 power-source = <IO_STANDARD_LVCMOS18>; 342 bias-disable; 343 }; 344 }; 345 346 pinctrl_nand0_default: nand0-default { 347 mux { 348 groups = "nand0_0_grp"; 349 function = "nand0"; 350 }; 351 352 conf { 353 groups = "nand0_0_grp"; 354 bias-pull-up; 355 }; 356 357 mux-ce { 358 groups = "nand0_ce_0_grp"; 359 function = "nand0_ce"; 360 }; 361 362 conf-ce { 363 groups = "nand0_ce_0_grp"; 364 bias-pull-up; 365 }; 366 367 mux-rb { 368 groups = "nand0_rb_0_grp"; 369 function = "nand0_rb"; 370 }; 371 372 conf-rb { 373 groups = "nand0_rb_0_grp"; 374 bias-pull-up; 375 }; 376 377 mux-dqs { 378 groups = "nand0_dqs_0_grp"; 379 function = "nand0_dqs"; 380 }; 381 382 conf-dqs { 383 groups = "nand0_dqs_0_grp"; 384 bias-pull-up; 385 }; 386 }; 387 388 pinctrl_spi0_default: spi0-default { 389 mux { 390 groups = "spi0_0_grp"; 391 function = "spi0"; 392 }; 393 394 conf { 395 groups = "spi0_0_grp"; 396 bias-disable; 397 slew-rate = <SLEW_RATE_SLOW>; 398 power-source = <IO_STANDARD_LVCMOS18>; 399 }; 400 401 mux-cs { 402 groups = "spi0_ss_0_grp", "spi0_ss_1_grp", 403 "spi0_ss_2_grp"; 404 function = "spi0_ss"; 405 }; 406 407 conf-cs { 408 groups = "spi0_ss_0_grp", "spi0_ss_1_grp", 409 "spi0_ss_2_grp"; 410 bias-disable; 411 }; 412 }; 413 414 pinctrl_spi1_default: spi1-default { 415 mux { 416 groups = "spi1_3_grp"; 417 function = "spi1"; 418 }; 419 420 conf { 421 groups = "spi1_3_grp"; 422 bias-disable; 423 slew-rate = <SLEW_RATE_SLOW>; 424 power-source = <IO_STANDARD_LVCMOS18>; 425 }; 426 427 mux-cs { 428 groups = "spi1_ss_9_grp", "spi1_ss_10_grp", 429 "spi1_ss_11_grp"; 430 function = "spi1_ss"; 431 }; 432 433 conf-cs { 434 groups = "spi1_ss_9_grp", "spi1_ss_10_grp", 435 "spi1_ss_11_grp"; 436 bias-disable; 437 }; 438 }; 439}; 440 441&rtc { 442 status = "okay"; 443}; 444 445&spi0 { 446 status = "okay"; 447 num-cs = <1>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_spi0_default>; 450 451 spi0_flash0: flash@0 { 452 #address-cells = <1>; 453 #size-cells = <1>; 454 compatible = "sst,sst25wf080", "jedec,spi-nor"; 455 spi-max-frequency = <50000000>; 456 reg = <0>; 457 458 partition@0 { 459 label = "spi0-data"; 460 reg = <0x0 0x100000>; 461 }; 462 }; 463}; 464 465&spi1 { 466 status = "okay"; 467 num-cs = <1>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_spi1_default>; 470 471 spi1_flash0: flash@0 { 472 #address-cells = <1>; 473 #size-cells = <1>; 474 compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; 475 spi-max-frequency = <20000000>; 476 reg = <0>; 477 478 partition@0 { 479 label = "spi1-data"; 480 reg = <0x0 0x84000>; 481 }; 482 }; 483}; 484 485/* ULPI SMSC USB3320 */ 486&usb1 { 487 status = "okay"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_usb1_default>; 490}; 491 492&dwc3_1 { 493 status = "okay"; 494 dr_mode = "host"; 495}; 496 497&uart0 { 498 status = "okay"; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&pinctrl_uart0_default>; 501}; 502 503&uart1 { 504 status = "okay"; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pinctrl_uart1_default>; 507}; 508