1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZC1232 4 * 5 * (C) Copyright 2017 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14 15/ { 16 model = "ZynqMP ZC1232 RevA"; 17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; 18 19 aliases { 20 serial0 = &uart0; 21 serial1 = &dcc; 22 spi0 = &qspi; 23 }; 24 25 chosen { 26 bootargs = "earlycon"; 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@0 { 31 device_type = "memory"; 32 reg = <0x0 0x0 0x0 0x80000000>; 33 }; 34}; 35 36&dcc { 37 status = "okay"; 38}; 39 40&qspi { 41 status = "okay"; 42 flash@0 { 43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 44 #address-cells = <1>; 45 #size-cells = <1>; 46 reg = <0x0>; 47 spi-tx-bus-width = <4>; 48 spi-rx-bus-width = <4>; 49 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 50 }; 51}; 52 53&sata { 54 status = "okay"; 55 /* SATA OOB timing settings */ 56 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 57 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 58 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 59 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 60 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 61 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 62 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 63 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 64}; 65 66&uart0 { 67 status = "okay"; 68}; 69