xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts (revision b50ecc5aca4d18f1f0c4942f5c797bc85edef144) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
4 *
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/input/input.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/phy/phy.h>
18#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19
20/ {
21	model = "ZynqMP SM-K26 Rev2/1/B/A";
22	compatible = "xlnx,zynqmp-sm-k26-rev2",
23		     "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
24		     "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
25		     "xlnx,zynqmp";
26
27	aliases {
28		i2c0 = &i2c0;
29		i2c1 = &i2c1;
30		mmc0 = &sdhci0;
31		mmc1 = &sdhci1;
32		nvmem0 = &eeprom;
33		nvmem1 = &eeprom_cc;
34		rtc0 = &rtc;
35		serial0 = &uart0;
36		serial1 = &uart1;
37		serial2 = &dcc;
38		spi0 = &qspi;
39		spi1 = &spi0;
40		spi2 = &spi1;
41		usb0 = &usb0;
42		usb1 = &usb1;
43	};
44
45	chosen {
46		bootargs = "earlycon";
47		stdout-path = "serial1:115200n8";
48	};
49
50	memory@0 {
51		device_type = "memory"; /* 4GB */
52		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
53	};
54
55	reserved-memory {
56		#address-cells = <2>;
57		#size-cells = <2>;
58		ranges;
59
60		pmu_region: pmu@7ff00000 {
61			reg = <0x0 0x7ff00000 0x0 0x100000>;
62			no-map;
63		};
64	};
65
66	gpio-keys {
67		compatible = "gpio-keys";
68		autorepeat;
69		key-fwuen {
70			label = "fwuen";
71			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
72			linux,code = <BTN_MISC>;
73			wakeup-source;
74			autorepeat;
75		};
76	};
77
78	leds {
79		compatible = "gpio-leds";
80		ds35-led {
81			label = "heartbeat";
82			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
83			linux,default-trigger = "heartbeat";
84		};
85
86		ds36-led {
87			label = "vbus_det";
88			gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
89			default-state = "on";
90		};
91	};
92
93	pwm-fan {
94		compatible = "pwm-fan";
95		status = "okay";
96		pwms = <&ttc0 2 40000 0>;
97	};
98};
99
100&modepin_gpio {
101	label = "modepin";
102};
103
104&ttc0 {
105	status = "okay";
106	#pwm-cells = <3>;
107};
108
109&uart1 { /* MIO36/MIO37 */
110	status = "okay";
111};
112
113&pinctrl0 {
114	status = "okay";
115	pinctrl_sdhci0_default: sdhci0-default {
116		conf {
117			groups = "sdio0_0_grp";
118			slew-rate = <SLEW_RATE_SLOW>;
119			power-source = <IO_STANDARD_LVCMOS18>;
120			bias-disable;
121		};
122
123		mux {
124			groups = "sdio0_0_grp";
125			function = "sdio0";
126		};
127	};
128};
129
130&qspi { /* MIO 0-5 - U143 */
131	status = "okay";
132	spi_flash: flash@0 { /* MT25QU512A */
133		compatible = "jedec,spi-nor"; /* 64MB */
134		reg = <0>;
135		spi-tx-bus-width = <4>;
136		spi-rx-bus-width = <4>;
137		spi-max-frequency = <40000000>; /* 40MHz */
138
139		partitions {
140			compatible = "fixed-partitions";
141			#address-cells = <1>;
142			#size-cells = <1>;
143
144			partition@0 {
145				label = "Image Selector";
146				reg = <0x0 0x80000>; /* 512KB */
147				read-only;
148				lock;
149			};
150			partition@80000 {
151				label = "Image Selector Golden";
152				reg = <0x80000 0x80000>; /* 512KB */
153				read-only;
154				lock;
155			};
156			partition@100000 {
157				label = "Persistent Register";
158				reg = <0x100000 0x20000>; /* 128KB */
159			};
160			partition@120000 {
161				label = "Persistent Register Backup";
162				reg = <0x120000 0x20000>; /* 128KB */
163			};
164			partition@140000 {
165				label = "Open_1";
166				reg = <0x140000 0xC0000>; /* 768KB */
167			};
168			partition@200000 {
169				label = "Image A (FSBL, PMU, ATF, U-Boot)";
170				reg = <0x200000 0xD00000>; /* 13MB */
171			};
172			partition@f00000 {
173				label = "ImgSel Image A Catch";
174				reg = <0xF00000 0x80000>; /* 512KB */
175				read-only;
176				lock;
177			};
178			partition@f80000 {
179				label = "Image B (FSBL, PMU, ATF, U-Boot)";
180				reg = <0xF80000 0xD00000>; /* 13MB */
181			};
182			partition@1c80000 {
183				label = "ImgSel Image B Catch";
184				reg = <0x1C80000 0x80000>; /* 512KB */
185				read-only;
186				lock;
187			};
188			partition@1d00000 {
189				label = "Open_2";
190				reg = <0x1D00000 0x100000>; /* 1MB */
191			};
192			partition@1e00000 {
193				label = "Recovery Image";
194				reg = <0x1E00000 0x200000>; /* 2MB */
195				read-only;
196				lock;
197			};
198			partition@2000000 {
199				label = "Recovery Image Backup";
200				reg = <0x2000000 0x200000>; /* 2MB */
201				read-only;
202				lock;
203			};
204			partition@2200000 {
205				label = "U-Boot storage variables";
206				reg = <0x2200000 0x20000>; /* 128KB */
207			};
208			partition@2220000 {
209				label = "U-Boot storage variables backup";
210				reg = <0x2220000 0x20000>; /* 128KB */
211			};
212			partition@2240000 {
213				label = "SHA256";
214				reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
215				read-only;
216				lock;
217			};
218			partition@2280000 {
219				label = "Secure OS Storage";
220				reg = <0x2280000 0x20000>; /* 128KB */
221			};
222			partition@22a0000 {
223				label = "User";
224				reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
225			};
226		};
227	};
228};
229
230&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
231	status = "okay";
232	pinctrl-names = "default";
233	pinctrl-0 = <&pinctrl_sdhci0_default>;
234	non-removable;
235	disable-wp;
236	bus-width = <8>;
237	xlnx,mio-bank = <0>;
238	assigned-clock-rates = <187498123>;
239};
240
241&spi1 { /* MIO6, 9-11 */
242	status = "okay";
243	label = "TPM";
244	num-cs = <1>;
245	tpm@0 { /* slm9670 - U144 */
246		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
247		reg = <0>;
248		spi-max-frequency = <18500000>;
249	};
250};
251
252&i2c1 {
253	status = "okay";
254	bootph-all;
255	clock-frequency = <400000>;
256	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
257	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
258
259	eeprom: eeprom@50 { /* u46 - also at address 0x58 */
260		bootph-all;
261		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
262		reg = <0x50>;
263		/* WP pin EE_WP_EN connected to slg7x644092@68 */
264	};
265
266	eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
267		bootph-all;
268		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
269		reg = <0x51>;
270	};
271
272	/* da9062@30 - u170 - also at address 0x31 */
273	/* da9131@33 - u167 */
274	da9131: pmic@33 {
275		compatible = "dlg,da9131";
276		reg = <0x33>;
277		regulators {
278			da9131_buck1: buck1 {
279				regulator-name = "da9131_buck1";
280				regulator-boot-on;
281				regulator-always-on;
282			};
283			da9131_buck2: buck2 {
284				regulator-name = "da9131_buck2";
285				regulator-boot-on;
286				regulator-always-on;
287			};
288		};
289	};
290
291	/* da9130@32 - u166 */
292	da9130: pmic@32 {
293		compatible = "dlg,da9130";
294		reg = <0x32>;
295		regulators {
296			da9130_buck1: buck1 {
297				regulator-name = "da9130_buck1";
298				regulator-boot-on;
299				regulator-always-on;
300			};
301		};
302	};
303
304	/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
305	/*
306	 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
307	 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
308	 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
309	 * With the FW fix, stdp4320 should respond to address 0x73 only.
310	 */
311	/* slg7x644092@68 - u169 */
312	/* Also connected via JA1C as C23/C24 */
313};
314
315&gpio {
316	status = "okay";
317	gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
318			  "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
319			  "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
320			  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
321			  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
322			  "I2C1_SDA", "", "", "", "", /* 25 - 29 */
323			  "", "", "", "", "", /* 30 - 34 */
324			  "", "", "", "", "", /* 35 - 39 */
325			  "", "", "", "", "", /* 40 - 44 */
326			  "", "", "", "", "", /* 45 - 49 */
327			  "", "", "", "", "", /* 50 - 54 */
328			  "", "", "", "", "", /* 55 - 59 */
329			  "", "", "", "", "", /* 60 - 64 */
330			  "", "", "", "", "", /* 65 - 69 */
331			  "", "", "", "", "", /* 70 - 74 */
332			  "", "", "", /* 75 - 77, MIO end and EMIO start */
333			  "", "", /* 78 - 79 */
334			  "", "", "", "", "", /* 80 - 84 */
335			  "", "", "", "", "", /* 85 - 89 */
336			  "", "", "", "", "", /* 90 - 94 */
337			  "", "", "", "", "", /* 95 - 99 */
338			  "", "", "", "", "", /* 100 - 104 */
339			  "", "", "", "", "", /* 105 - 109 */
340			  "", "", "", "", "", /* 110 - 114 */
341			  "", "", "", "", "", /* 115 - 119 */
342			  "", "", "", "", "", /* 120 - 124 */
343			  "", "", "", "", "", /* 125 - 129 */
344			  "", "", "", "", "", /* 130 - 134 */
345			  "", "", "", "", "", /* 135 - 139 */
346			  "", "", "", "", "", /* 140 - 144 */
347			  "", "", "", "", "", /* 145 - 149 */
348			  "", "", "", "", "", /* 150 - 154 */
349			  "", "", "", "", "", /* 155 - 159 */
350			  "", "", "", "", "", /* 160 - 164 */
351			  "", "", "", "", "", /* 165 - 169 */
352			  "", "", "", ""; /* 170 - 173 */
353};
354
355&ams_ps {
356	status = "okay";
357};
358
359&ams_pl {
360	status = "okay";
361};
362
363&zynqmp_dpsub {
364	status = "okay";
365};
366
367&rtc {
368	status = "okay";
369};
370
371&lpd_dma_chan1 {
372	status = "okay";
373};
374
375&lpd_dma_chan2 {
376	status = "okay";
377};
378
379&lpd_dma_chan3 {
380	status = "okay";
381};
382
383&lpd_dma_chan4 {
384	status = "okay";
385};
386
387&lpd_dma_chan5 {
388	status = "okay";
389};
390
391&lpd_dma_chan6 {
392	status = "okay";
393};
394
395&lpd_dma_chan7 {
396	status = "okay";
397};
398
399&lpd_dma_chan8 {
400	status = "okay";
401};
402
403&fpd_dma_chan1 {
404	status = "okay";
405};
406
407&fpd_dma_chan2 {
408	status = "okay";
409};
410
411&fpd_dma_chan3 {
412	status = "okay";
413};
414
415&fpd_dma_chan4 {
416	status = "okay";
417};
418
419&fpd_dma_chan5 {
420	status = "okay";
421};
422
423&fpd_dma_chan6 {
424	status = "okay";
425};
426
427&fpd_dma_chan7 {
428	status = "okay";
429};
430
431&fpd_dma_chan8 {
432	status = "okay";
433};
434
435&gpu {
436	status = "okay";
437};
438
439&lpd_watchdog {
440	status = "okay";
441};
442
443&watchdog0 {
444	status = "okay";
445};
446
447&cpu_opp_table {
448	opp00 {
449		opp-hz = /bits/ 64 <1333333333>;
450	};
451	opp01 {
452		opp-hz = /bits/ 64 <666666666>;
453	};
454	opp02 {
455		opp-hz = /bits/ 64 <444444444>;
456	};
457	opp03 {
458		opp-hz = /bits/ 64 <333333333>;
459	};
460};
461