1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 15 16/dts-v1/; 17/plugin/; 18 19&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 20 #address-cells = <1>; 21 #size-cells = <0>; 22 pinctrl-names = "default", "gpio"; 23 pinctrl-0 = <&pinctrl_i2c1_default>; 24 pinctrl-1 = <&pinctrl_i2c1_gpio>; 25 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 26 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 27 28 /* u14 - 0x40 - ina260 */ 29 /* u43 - 0x2d - usb5744 */ 30 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 31}; 32 33&amba { 34 si5332_0: si5332_0 { /* u17 */ 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <125000000>; 38 }; 39 40 si5332_1: si5332_1 { /* u17 */ 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <25000000>; 44 }; 45 46 si5332_2: si5332_2 { /* u17 */ 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <48000000>; 50 }; 51 52 si5332_3: si5332_3 { /* u17 */ 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <24000000>; 56 }; 57 58 si5332_4: si5332_4 { /* u17 */ 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <26000000>; 62 }; 63 64 si5332_5: si5332_5 { /* u17 */ 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <27000000>; 68 }; 69}; 70 71/* DP/USB 3.0 */ 72&psgtr { 73 status = "okay"; 74 /* pcie, usb3, sata */ 75 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 76 clock-names = "ref0", "ref1", "ref2"; 77}; 78 79&zynqmp_dpsub { 80 status = "okay"; 81 phy-names = "dp-phy0", "dp-phy1"; 82 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 83 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 84}; 85 86&zynqmp_dpdma { 87 status = "okay"; 88 assigned-clock-rates = <600000000>; 89}; 90 91&usb0 { 92 status = "okay"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_usb0_default>; 95 phy-names = "usb3-phy"; 96 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 97}; 98 99&dwc3_0 { 100 status = "okay"; 101 dr_mode = "host"; 102 snps,usb3_lpm_capable; 103 maximum-speed = "super-speed"; 104}; 105 106&sdhci1 { /* on CC with tuned parameters */ 107 status = "okay"; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_sdhci1_default>; 110 /* 111 * SD 3.0 requires level shifter and this property 112 * should be removed if the board has level shifter and 113 * need to work in UHS mode 114 */ 115 no-1-8-v; 116 disable-wp; 117 xlnx,mio-bank = <1>; 118 clk-phase-sd-hs = <126>, <60>; 119 clk-phase-uhs-sdr25 = <120>, <60>; 120 clk-phase-uhs-ddr50 = <126>, <48>; 121 assigned-clock-rates = <187498123>; 122 bus-width = <4>; 123}; 124 125&gem3 { /* required by spec */ 126 status = "okay"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_gem3_default>; 129 phy-handle = <&phy0>; 130 phy-mode = "rgmii-id"; 131 132 mdio: mdio { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 phy0: ethernet-phy@1 { 137 #phy-cells = <1>; 138 reg = <1>; 139 compatible = "ethernet-phy-id2000.a231"; 140 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 141 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 142 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 143 ti,dp83867-rxctrl-strap-quirk; 144 reset-assert-us = <100>; 145 reset-deassert-us = <280>; 146 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 147 }; 148 }; 149}; 150 151&pinctrl0 { /* required by spec */ 152 status = "okay"; 153 154 pinctrl_uart1_default: uart1-default { 155 conf { 156 groups = "uart1_9_grp"; 157 slew-rate = <SLEW_RATE_SLOW>; 158 power-source = <IO_STANDARD_LVCMOS18>; 159 drive-strength = <12>; 160 }; 161 162 conf-rx { 163 pins = "MIO37"; 164 bias-high-impedance; 165 }; 166 167 conf-tx { 168 pins = "MIO36"; 169 bias-disable; 170 }; 171 172 mux { 173 groups = "uart1_9_grp"; 174 function = "uart1"; 175 }; 176 }; 177 178 pinctrl_i2c1_default: i2c1-default { 179 conf { 180 groups = "i2c1_6_grp"; 181 bias-pull-up; 182 slew-rate = <SLEW_RATE_SLOW>; 183 power-source = <IO_STANDARD_LVCMOS18>; 184 }; 185 186 mux { 187 groups = "i2c1_6_grp"; 188 function = "i2c1"; 189 }; 190 }; 191 192 pinctrl_i2c1_gpio: i2c1-gpio { 193 conf { 194 groups = "gpio0_24_grp", "gpio0_25_grp"; 195 slew-rate = <SLEW_RATE_SLOW>; 196 power-source = <IO_STANDARD_LVCMOS18>; 197 }; 198 199 mux { 200 groups = "gpio0_24_grp", "gpio0_25_grp"; 201 function = "gpio0"; 202 }; 203 }; 204 205 pinctrl_gem3_default: gem3-default { 206 conf { 207 groups = "ethernet3_0_grp"; 208 slew-rate = <SLEW_RATE_SLOW>; 209 power-source = <IO_STANDARD_LVCMOS18>; 210 }; 211 212 conf-rx { 213 pins = "MIO70", "MIO72", "MIO74"; 214 bias-high-impedance; 215 low-power-disable; 216 }; 217 218 conf-bootstrap { 219 pins = "MIO71", "MIO73", "MIO75"; 220 bias-disable; 221 low-power-disable; 222 }; 223 224 conf-tx { 225 pins = "MIO64", "MIO65", "MIO66", 226 "MIO67", "MIO68", "MIO69"; 227 bias-disable; 228 low-power-enable; 229 }; 230 231 conf-mdio { 232 groups = "mdio3_0_grp"; 233 slew-rate = <SLEW_RATE_SLOW>; 234 power-source = <IO_STANDARD_LVCMOS18>; 235 bias-disable; 236 }; 237 238 mux-mdio { 239 function = "mdio3"; 240 groups = "mdio3_0_grp"; 241 }; 242 243 mux { 244 function = "ethernet3"; 245 groups = "ethernet3_0_grp"; 246 }; 247 }; 248 249 pinctrl_usb0_default: usb0-default { 250 conf { 251 groups = "usb0_0_grp"; 252 power-source = <IO_STANDARD_LVCMOS18>; 253 }; 254 255 conf-rx { 256 pins = "MIO52", "MIO53", "MIO55"; 257 bias-high-impedance; 258 drive-strength = <12>; 259 slew-rate = <SLEW_RATE_FAST>; 260 }; 261 262 conf-tx { 263 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 264 "MIO60", "MIO61", "MIO62", "MIO63"; 265 bias-disable; 266 drive-strength = <4>; 267 slew-rate = <SLEW_RATE_SLOW>; 268 }; 269 270 mux { 271 groups = "usb0_0_grp"; 272 function = "usb0"; 273 }; 274 }; 275 276 pinctrl_sdhci1_default: sdhci1-default { 277 conf { 278 groups = "sdio1_0_grp"; 279 slew-rate = <SLEW_RATE_SLOW>; 280 power-source = <IO_STANDARD_LVCMOS18>; 281 bias-disable; 282 }; 283 284 conf-cd { 285 groups = "sdio1_cd_0_grp"; 286 bias-high-impedance; 287 bias-pull-up; 288 slew-rate = <SLEW_RATE_SLOW>; 289 power-source = <IO_STANDARD_LVCMOS18>; 290 }; 291 292 mux-cd { 293 groups = "sdio1_cd_0_grp"; 294 function = "sdio1_cd"; 295 }; 296 297 mux { 298 groups = "sdio1_0_grp"; 299 function = "sdio1"; 300 }; 301 }; 302}; 303 304&uart1 { 305 status = "okay"; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_uart1_default>; 308}; 309