1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 15/dts-v1/; 16/plugin/; 17 18&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 19 #address-cells = <1>; 20 #size-cells = <0>; 21 pinctrl-names = "default", "gpio"; 22 pinctrl-0 = <&pinctrl_i2c1_default>; 23 pinctrl-1 = <&pinctrl_i2c1_gpio>; 24 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 25 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 26 27 /* u14 - 0x40 - ina260 */ 28 /* u43 - 0x2d - usb5744 */ 29 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 30}; 31 32&amba { 33 si5332_0: si5332_0 { /* u17 */ 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <125000000>; 37 }; 38 39 si5332_1: si5332_1 { /* u17 */ 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <25000000>; 43 }; 44 45 si5332_2: si5332_2 { /* u17 */ 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <48000000>; 49 }; 50 51 si5332_3: si5332_3 { /* u17 */ 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <24000000>; 55 }; 56 57 si5332_4: si5332_4 { /* u17 */ 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <26000000>; 61 }; 62 63 si5332_5: si5332_5 { /* u17 */ 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <27000000>; 67 }; 68}; 69 70/* DP/USB 3.0 */ 71&psgtr { 72 status = "okay"; 73 /* pcie, usb3, sata */ 74 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 75 clock-names = "ref0", "ref1", "ref2"; 76}; 77 78&zynqmp_dpsub { 79 status = "okay"; 80 phy-names = "dp-phy0", "dp-phy1"; 81 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 82 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 83}; 84 85&zynqmp_dpdma { 86 status = "okay"; 87 assigned-clock-rates = <600000000>; 88}; 89 90&usb0 { 91 status = "okay"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_usb0_default>; 94 phy-names = "usb3-phy"; 95 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 96}; 97 98&dwc3_0 { 99 status = "okay"; 100 dr_mode = "host"; 101 snps,usb3_lpm_capable; 102 maximum-speed = "super-speed"; 103}; 104 105&sdhci1 { /* on CC with tuned parameters */ 106 status = "okay"; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_sdhci1_default>; 109 /* 110 * SD 3.0 requires level shifter and this property 111 * should be removed if the board has level shifter and 112 * need to work in UHS mode 113 */ 114 no-1-8-v; 115 disable-wp; 116 xlnx,mio-bank = <1>; 117 clk-phase-sd-hs = <126>, <60>; 118 clk-phase-uhs-sdr25 = <120>, <60>; 119 clk-phase-uhs-ddr50 = <126>, <48>; 120 assigned-clock-rates = <187498123>; 121}; 122 123&gem3 { /* required by spec */ 124 status = "okay"; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_gem3_default>; 127 phy-handle = <&phy0>; 128 phy-mode = "rgmii-id"; 129 130 mdio: mdio { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 phy0: ethernet-phy@1 { 135 #phy-cells = <1>; 136 reg = <1>; 137 compatible = "ethernet-phy-id2000.a231"; 138 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 139 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 140 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 141 ti,dp83867-rxctrl-strap-quirk; 142 reset-assert-us = <100>; 143 reset-deassert-us = <280>; 144 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 145 }; 146 }; 147}; 148 149&pinctrl0 { /* required by spec */ 150 status = "okay"; 151 152 pinctrl_uart1_default: uart1-default { 153 conf { 154 groups = "uart1_9_grp"; 155 slew-rate = <SLEW_RATE_SLOW>; 156 power-source = <IO_STANDARD_LVCMOS18>; 157 drive-strength = <12>; 158 }; 159 160 conf-rx { 161 pins = "MIO37"; 162 bias-high-impedance; 163 }; 164 165 conf-tx { 166 pins = "MIO36"; 167 bias-disable; 168 }; 169 170 mux { 171 groups = "uart1_9_grp"; 172 function = "uart1"; 173 }; 174 }; 175 176 pinctrl_i2c1_default: i2c1-default { 177 conf { 178 groups = "i2c1_6_grp"; 179 bias-pull-up; 180 slew-rate = <SLEW_RATE_SLOW>; 181 power-source = <IO_STANDARD_LVCMOS18>; 182 }; 183 184 mux { 185 groups = "i2c1_6_grp"; 186 function = "i2c1"; 187 }; 188 }; 189 190 pinctrl_i2c1_gpio: i2c1-gpio { 191 conf { 192 groups = "gpio0_24_grp", "gpio0_25_grp"; 193 slew-rate = <SLEW_RATE_SLOW>; 194 power-source = <IO_STANDARD_LVCMOS18>; 195 }; 196 197 mux { 198 groups = "gpio0_24_grp", "gpio0_25_grp"; 199 function = "gpio0"; 200 }; 201 }; 202 203 pinctrl_gem3_default: gem3-default { 204 conf { 205 groups = "ethernet3_0_grp"; 206 slew-rate = <SLEW_RATE_SLOW>; 207 power-source = <IO_STANDARD_LVCMOS18>; 208 }; 209 210 conf-rx { 211 pins = "MIO70", "MIO72", "MIO74"; 212 bias-high-impedance; 213 low-power-disable; 214 }; 215 216 conf-bootstrap { 217 pins = "MIO71", "MIO73", "MIO75"; 218 bias-disable; 219 low-power-disable; 220 }; 221 222 conf-tx { 223 pins = "MIO64", "MIO65", "MIO66", 224 "MIO67", "MIO68", "MIO69"; 225 bias-disable; 226 low-power-enable; 227 }; 228 229 conf-mdio { 230 groups = "mdio3_0_grp"; 231 slew-rate = <SLEW_RATE_SLOW>; 232 power-source = <IO_STANDARD_LVCMOS18>; 233 bias-disable; 234 }; 235 236 mux-mdio { 237 function = "mdio3"; 238 groups = "mdio3_0_grp"; 239 }; 240 241 mux { 242 function = "ethernet3"; 243 groups = "ethernet3_0_grp"; 244 }; 245 }; 246 247 pinctrl_usb0_default: usb0-default { 248 conf { 249 groups = "usb0_0_grp"; 250 slew-rate = <SLEW_RATE_SLOW>; 251 power-source = <IO_STANDARD_LVCMOS18>; 252 }; 253 254 conf-rx { 255 pins = "MIO52", "MIO53", "MIO55"; 256 bias-high-impedance; 257 }; 258 259 conf-tx { 260 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 261 "MIO60", "MIO61", "MIO62", "MIO63"; 262 bias-disable; 263 }; 264 265 mux { 266 groups = "usb0_0_grp"; 267 function = "usb0"; 268 }; 269 }; 270 271 pinctrl_sdhci1_default: sdhci1-default { 272 conf { 273 groups = "sdio1_0_grp"; 274 slew-rate = <SLEW_RATE_SLOW>; 275 power-source = <IO_STANDARD_LVCMOS18>; 276 bias-disable; 277 }; 278 279 conf-cd { 280 groups = "sdio1_cd_0_grp"; 281 bias-high-impedance; 282 bias-pull-up; 283 slew-rate = <SLEW_RATE_SLOW>; 284 power-source = <IO_STANDARD_LVCMOS18>; 285 }; 286 287 mux-cd { 288 groups = "sdio1_cd_0_grp"; 289 function = "sdio1_cd"; 290 }; 291 292 mux { 293 groups = "sdio1_0_grp"; 294 function = "sdio1"; 295 }; 296 }; 297}; 298 299&uart1 { 300 status = "okay"; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_uart1_default>; 303}; 304