1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 15 16/dts-v1/; 17/plugin/; 18 19&{/} { 20 si5332_0: si5332-0 { /* u17 */ 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <125000000>; 24 }; 25 26 si5332_1: si5332-1 { /* u17 */ 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <25000000>; 30 }; 31 32 si5332_2: si5332-2 { /* u17 */ 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <48000000>; 36 }; 37 38 si5332_3: si5332-3 { /* u17 */ 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <24000000>; 42 }; 43 44 si5332_4: si5332-4 { /* u17 */ 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <26000000>; 48 }; 49 50 si5332_5: si5332-5 { /* u17 */ 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <27000000>; 54 }; 55}; 56 57&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 58 #address-cells = <1>; 59 #size-cells = <0>; 60 pinctrl-names = "default", "gpio"; 61 pinctrl-0 = <&pinctrl_i2c1_default>; 62 pinctrl-1 = <&pinctrl_i2c1_gpio>; 63 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 64 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 65 66 /* u14 - 0x40 - ina260 */ 67 /* u43 - 0x2d - usb5744 */ 68 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 69}; 70 71/* DP/USB 3.0 */ 72&psgtr { 73 status = "okay"; 74 /* pcie, usb3, sata */ 75 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 76 clock-names = "ref0", "ref1", "ref2"; 77}; 78 79&zynqmp_dpsub { 80 status = "okay"; 81 phy-names = "dp-phy0", "dp-phy1"; 82 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 83 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 84}; 85 86&zynqmp_dpdma { 87 status = "okay"; 88 assigned-clock-rates = <600000000>; 89}; 90 91&usb0 { 92 status = "okay"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_usb0_default>; 95 phy-names = "usb3-phy"; 96 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 97 assigned-clock-rates = <250000000>, <20000000>; 98}; 99 100&dwc3_0 { 101 status = "okay"; 102 dr_mode = "host"; 103 snps,usb3_lpm_capable; 104 maximum-speed = "super-speed"; 105}; 106 107&sdhci1 { /* on CC with tuned parameters */ 108 status = "okay"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_sdhci1_default>; 111 /* 112 * SD 3.0 requires level shifter and this property 113 * should be removed if the board has level shifter and 114 * need to work in UHS mode 115 */ 116 no-1-8-v; 117 disable-wp; 118 xlnx,mio-bank = <1>; 119 clk-phase-sd-hs = <126>, <60>; 120 clk-phase-uhs-sdr25 = <120>, <60>; 121 clk-phase-uhs-ddr50 = <126>, <48>; 122 assigned-clock-rates = <187498123>; 123 bus-width = <4>; 124}; 125 126&gem3 { 127 status = "okay"; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_gem3_default>; 130 phy-handle = <&phy0>; 131 phy-mode = "rgmii-id"; 132 assigned-clock-rates = <250000000>; 133 134 mdio: mdio { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 phy0: ethernet-phy@1 { 139 #phy-cells = <1>; 140 reg = <1>; 141 compatible = "ethernet-phy-id2000.a231"; 142 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 143 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 144 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 145 ti,dp83867-rxctrl-strap-quirk; 146 reset-assert-us = <100>; 147 reset-deassert-us = <280>; 148 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 149 }; 150 }; 151}; 152 153&pinctrl0 { 154 status = "okay"; 155 156 pinctrl_gpio0_default: gpio0-default { 157 conf { 158 groups = "gpio0_38_grp"; 159 bias-pull-up; 160 power-source = <IO_STANDARD_LVCMOS18>; 161 }; 162 163 mux { 164 groups = "gpio0_38_grp"; 165 function = "gpio0"; 166 }; 167 168 conf-tx { 169 pins = "MIO38"; 170 bias-disable; 171 output-enable; 172 }; 173 }; 174 175 pinctrl_uart1_default: uart1-default { 176 conf { 177 groups = "uart1_9_grp"; 178 slew-rate = <SLEW_RATE_SLOW>; 179 power-source = <IO_STANDARD_LVCMOS18>; 180 drive-strength = <12>; 181 }; 182 183 conf-rx { 184 pins = "MIO37"; 185 bias-high-impedance; 186 }; 187 188 conf-tx { 189 pins = "MIO36"; 190 bias-disable; 191 output-enable; 192 }; 193 194 mux { 195 groups = "uart1_9_grp"; 196 function = "uart1"; 197 }; 198 }; 199 200 pinctrl_i2c1_default: i2c1-default { 201 conf { 202 groups = "i2c1_6_grp"; 203 bias-pull-up; 204 slew-rate = <SLEW_RATE_SLOW>; 205 power-source = <IO_STANDARD_LVCMOS18>; 206 }; 207 208 mux { 209 groups = "i2c1_6_grp"; 210 function = "i2c1"; 211 }; 212 }; 213 214 pinctrl_i2c1_gpio: i2c1-gpio-grp { 215 conf { 216 groups = "gpio0_24_grp", "gpio0_25_grp"; 217 slew-rate = <SLEW_RATE_SLOW>; 218 power-source = <IO_STANDARD_LVCMOS18>; 219 }; 220 221 mux { 222 groups = "gpio0_24_grp", "gpio0_25_grp"; 223 function = "gpio0"; 224 }; 225 }; 226 227 pinctrl_gem3_default: gem3-default { 228 conf { 229 groups = "ethernet3_0_grp"; 230 slew-rate = <SLEW_RATE_SLOW>; 231 power-source = <IO_STANDARD_LVCMOS18>; 232 }; 233 234 conf-rx { 235 pins = "MIO70", "MIO72", "MIO74"; 236 bias-high-impedance; 237 low-power-disable; 238 }; 239 240 conf-bootstrap { 241 pins = "MIO71", "MIO73", "MIO75"; 242 bias-disable; 243 output-enable; 244 low-power-disable; 245 }; 246 247 conf-tx { 248 pins = "MIO64", "MIO65", "MIO66", 249 "MIO67", "MIO68", "MIO69"; 250 bias-disable; 251 output-enable; 252 low-power-enable; 253 }; 254 255 conf-mdio { 256 groups = "mdio3_0_grp"; 257 slew-rate = <SLEW_RATE_SLOW>; 258 power-source = <IO_STANDARD_LVCMOS18>; 259 bias-disable; 260 output-enable; 261 }; 262 263 mux-mdio { 264 function = "mdio3"; 265 groups = "mdio3_0_grp"; 266 }; 267 268 mux { 269 function = "ethernet3"; 270 groups = "ethernet3_0_grp"; 271 }; 272 }; 273 274 pinctrl_usb0_default: usb0-default { 275 conf { 276 groups = "usb0_0_grp"; 277 power-source = <IO_STANDARD_LVCMOS18>; 278 }; 279 280 conf-rx { 281 pins = "MIO52", "MIO53", "MIO55"; 282 bias-high-impedance; 283 drive-strength = <12>; 284 slew-rate = <SLEW_RATE_FAST>; 285 }; 286 287 conf-tx { 288 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 289 "MIO60", "MIO61", "MIO62", "MIO63"; 290 bias-disable; 291 output-enable; 292 drive-strength = <4>; 293 slew-rate = <SLEW_RATE_SLOW>; 294 }; 295 296 mux { 297 groups = "usb0_0_grp"; 298 function = "usb0"; 299 }; 300 }; 301 302 pinctrl_sdhci1_default: sdhci1-default { 303 conf { 304 groups = "sdio1_0_grp"; 305 slew-rate = <SLEW_RATE_SLOW>; 306 power-source = <IO_STANDARD_LVCMOS18>; 307 bias-disable; 308 }; 309 310 conf-cd { 311 groups = "sdio1_cd_0_grp"; 312 bias-high-impedance; 313 bias-pull-up; 314 slew-rate = <SLEW_RATE_SLOW>; 315 power-source = <IO_STANDARD_LVCMOS18>; 316 }; 317 318 mux-cd { 319 groups = "sdio1_cd_0_grp"; 320 function = "sdio1_cd"; 321 }; 322 323 mux { 324 groups = "sdio1_0_grp"; 325 function = "sdio1"; 326 }; 327 }; 328}; 329 330&gpio { 331 status = "okay"; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_gpio0_default>; 334}; 335 336&uart1 { 337 status = "okay"; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_uart1_default>; 340}; 341