1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 15 16/dts-v1/; 17/plugin/; 18 19&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 20 #address-cells = <1>; 21 #size-cells = <0>; 22 pinctrl-names = "default", "gpio"; 23 pinctrl-0 = <&pinctrl_i2c1_default>; 24 pinctrl-1 = <&pinctrl_i2c1_gpio>; 25 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 26 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 27 28 /* u14 - 0x40 - ina260 */ 29 /* u43 - 0x2d - usb5744 */ 30 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 31}; 32 33&amba { 34 si5332_0: si5332_0 { /* u17 */ 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <125000000>; 38 }; 39 40 si5332_1: si5332_1 { /* u17 */ 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <25000000>; 44 }; 45 46 si5332_2: si5332_2 { /* u17 */ 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <48000000>; 50 }; 51 52 si5332_3: si5332_3 { /* u17 */ 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <24000000>; 56 }; 57 58 si5332_4: si5332_4 { /* u17 */ 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <26000000>; 62 }; 63 64 si5332_5: si5332_5 { /* u17 */ 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <27000000>; 68 }; 69}; 70 71/* DP/USB 3.0 */ 72&psgtr { 73 status = "okay"; 74 /* pcie, usb3, sata */ 75 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 76 clock-names = "ref0", "ref1", "ref2"; 77}; 78 79&zynqmp_dpsub { 80 status = "okay"; 81 phy-names = "dp-phy0", "dp-phy1"; 82 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 83 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 84}; 85 86&zynqmp_dpdma { 87 status = "okay"; 88 assigned-clock-rates = <600000000>; 89}; 90 91&usb0 { 92 status = "okay"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_usb0_default>; 95 phy-names = "usb3-phy"; 96 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 97}; 98 99&dwc3_0 { 100 status = "okay"; 101 dr_mode = "host"; 102 snps,usb3_lpm_capable; 103 maximum-speed = "super-speed"; 104}; 105 106&sdhci1 { /* on CC with tuned parameters */ 107 status = "okay"; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_sdhci1_default>; 110 /* 111 * SD 3.0 requires level shifter and this property 112 * should be removed if the board has level shifter and 113 * need to work in UHS mode 114 */ 115 no-1-8-v; 116 disable-wp; 117 xlnx,mio-bank = <1>; 118 clk-phase-sd-hs = <126>, <60>; 119 clk-phase-uhs-sdr25 = <120>, <60>; 120 clk-phase-uhs-ddr50 = <126>, <48>; 121 assigned-clock-rates = <187498123>; 122 bus-width = <4>; 123}; 124 125&gem3 { /* required by spec */ 126 status = "okay"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_gem3_default>; 129 phy-handle = <&phy0>; 130 phy-mode = "rgmii-id"; 131 assigned-clock-rates = <250000000>; 132 133 mdio: mdio { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 137 phy0: ethernet-phy@1 { 138 #phy-cells = <1>; 139 reg = <1>; 140 compatible = "ethernet-phy-id2000.a231"; 141 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 142 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 143 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 144 ti,dp83867-rxctrl-strap-quirk; 145 reset-assert-us = <100>; 146 reset-deassert-us = <280>; 147 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 148 }; 149 }; 150}; 151 152&pinctrl0 { /* required by spec */ 153 status = "okay"; 154 155 pinctrl_uart1_default: uart1-default { 156 conf { 157 groups = "uart1_9_grp"; 158 slew-rate = <SLEW_RATE_SLOW>; 159 power-source = <IO_STANDARD_LVCMOS18>; 160 drive-strength = <12>; 161 }; 162 163 conf-rx { 164 pins = "MIO37"; 165 bias-high-impedance; 166 }; 167 168 conf-tx { 169 pins = "MIO36"; 170 bias-disable; 171 }; 172 173 mux { 174 groups = "uart1_9_grp"; 175 function = "uart1"; 176 }; 177 }; 178 179 pinctrl_i2c1_default: i2c1-default { 180 conf { 181 groups = "i2c1_6_grp"; 182 bias-pull-up; 183 slew-rate = <SLEW_RATE_SLOW>; 184 power-source = <IO_STANDARD_LVCMOS18>; 185 }; 186 187 mux { 188 groups = "i2c1_6_grp"; 189 function = "i2c1"; 190 }; 191 }; 192 193 pinctrl_i2c1_gpio: i2c1-gpio { 194 conf { 195 groups = "gpio0_24_grp", "gpio0_25_grp"; 196 slew-rate = <SLEW_RATE_SLOW>; 197 power-source = <IO_STANDARD_LVCMOS18>; 198 }; 199 200 mux { 201 groups = "gpio0_24_grp", "gpio0_25_grp"; 202 function = "gpio0"; 203 }; 204 }; 205 206 pinctrl_gem3_default: gem3-default { 207 conf { 208 groups = "ethernet3_0_grp"; 209 slew-rate = <SLEW_RATE_SLOW>; 210 power-source = <IO_STANDARD_LVCMOS18>; 211 }; 212 213 conf-rx { 214 pins = "MIO70", "MIO72", "MIO74"; 215 bias-high-impedance; 216 low-power-disable; 217 }; 218 219 conf-bootstrap { 220 pins = "MIO71", "MIO73", "MIO75"; 221 bias-disable; 222 low-power-disable; 223 }; 224 225 conf-tx { 226 pins = "MIO64", "MIO65", "MIO66", 227 "MIO67", "MIO68", "MIO69"; 228 bias-disable; 229 low-power-enable; 230 }; 231 232 conf-mdio { 233 groups = "mdio3_0_grp"; 234 slew-rate = <SLEW_RATE_SLOW>; 235 power-source = <IO_STANDARD_LVCMOS18>; 236 bias-disable; 237 }; 238 239 mux-mdio { 240 function = "mdio3"; 241 groups = "mdio3_0_grp"; 242 }; 243 244 mux { 245 function = "ethernet3"; 246 groups = "ethernet3_0_grp"; 247 }; 248 }; 249 250 pinctrl_usb0_default: usb0-default { 251 conf { 252 groups = "usb0_0_grp"; 253 power-source = <IO_STANDARD_LVCMOS18>; 254 }; 255 256 conf-rx { 257 pins = "MIO52", "MIO53", "MIO55"; 258 bias-high-impedance; 259 drive-strength = <12>; 260 slew-rate = <SLEW_RATE_FAST>; 261 }; 262 263 conf-tx { 264 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 265 "MIO60", "MIO61", "MIO62", "MIO63"; 266 bias-disable; 267 drive-strength = <4>; 268 slew-rate = <SLEW_RATE_SLOW>; 269 }; 270 271 mux { 272 groups = "usb0_0_grp"; 273 function = "usb0"; 274 }; 275 }; 276 277 pinctrl_sdhci1_default: sdhci1-default { 278 conf { 279 groups = "sdio1_0_grp"; 280 slew-rate = <SLEW_RATE_SLOW>; 281 power-source = <IO_STANDARD_LVCMOS18>; 282 bias-disable; 283 }; 284 285 conf-cd { 286 groups = "sdio1_cd_0_grp"; 287 bias-high-impedance; 288 bias-pull-up; 289 slew-rate = <SLEW_RATE_SLOW>; 290 power-source = <IO_STANDARD_LVCMOS18>; 291 }; 292 293 mux-cd { 294 groups = "sdio1_cd_0_grp"; 295 function = "sdio1_cd"; 296 }; 297 298 mux { 299 groups = "sdio1_0_grp"; 300 function = "sdio1"; 301 }; 302 }; 303}; 304 305&uart1 { 306 status = "okay"; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_uart1_default>; 309}; 310