1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * SD level shifter: 9 * "A" - A01 board un-modified (NXP) 10 * "Y" - A01 board modified with legacy interposer (Nexperia) 11 * "Z" - A01 board modified with Diode interposer 12 * 13 * Michal Simek <michal.simek@amd.com> 14 */ 15 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/net/ti-dp83867.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 20 21/dts-v1/; 22/plugin/; 23 24&{/} { 25 si5332_0: si5332-0 { /* u17 */ 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <125000000>; 29 }; 30 31 si5332_1: si5332-1 { /* u17 */ 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <25000000>; 35 }; 36 37 si5332_2: si5332-2 { /* u17 */ 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <48000000>; 41 }; 42 43 si5332_3: si5332-3 { /* u17 */ 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <24000000>; 47 }; 48 49 si5332_4: si5332-4 { /* u17 */ 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <26000000>; 53 }; 54 55 si5332_5: si5332-5 { /* u17 */ 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <27000000>; 59 }; 60}; 61 62&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 63 #address-cells = <1>; 64 #size-cells = <0>; 65 pinctrl-names = "default", "gpio"; 66 pinctrl-0 = <&pinctrl_i2c1_default>; 67 pinctrl-1 = <&pinctrl_i2c1_gpio>; 68 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 69 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 70 71 /* u14 - 0x40 - ina260 */ 72 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 73}; 74 75/* DP/USB 3.0 and SATA */ 76&psgtr { 77 status = "okay"; 78 /* pcie, usb3, sata */ 79 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 80 clock-names = "ref0", "ref1", "ref2"; 81}; 82 83&sata { 84 status = "okay"; 85 /* SATA OOB timing settings */ 86 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 87 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 88 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 89 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 90 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 91 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 92 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 93 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 94 phy-names = "sata-phy"; 95 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; 96}; 97 98&zynqmp_dpsub { 99 status = "okay"; 100 phy-names = "dp-phy0", "dp-phy1"; 101 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 102 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 103}; 104 105&zynqmp_dpdma { 106 status = "okay"; 107 assigned-clock-rates = <600000000>; 108}; 109 110&usb0 { 111 status = "okay"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_usb0_default>; 114 phy-names = "usb3-phy"; 115 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 116 /* missing usb5744 - u43 */ 117}; 118 119&dwc3_0 { 120 status = "okay"; 121 dr_mode = "host"; 122 snps,usb3_lpm_capable; 123 maximum-speed = "super-speed"; 124}; 125 126&sdhci1 { /* on CC with tuned parameters */ 127 status = "okay"; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_sdhci1_default>; 130 /* 131 * SD 3.0 requires level shifter and this property 132 * should be removed if the board has level shifter and 133 * need to work in UHS mode 134 */ 135 no-1-8-v; 136 disable-wp; 137 xlnx,mio-bank = <1>; 138 assigned-clock-rates = <187498123>; 139 bus-width = <4>; 140}; 141 142&gem3 { 143 status = "okay"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_gem3_default>; 146 phy-handle = <&phy0>; 147 phy-mode = "rgmii-id"; 148 assigned-clock-rates = <250000000>; 149 150 mdio: mdio { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 phy0: ethernet-phy@1 { 155 #phy-cells = <1>; 156 reg = <1>; 157 compatible = "ethernet-phy-id2000.a231"; 158 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 159 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 160 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 161 ti,dp83867-rxctrl-strap-quirk; 162 reset-assert-us = <100>; 163 reset-deassert-us = <280>; 164 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 165 }; 166 }; 167}; 168 169&pinctrl0 { 170 status = "okay"; 171 172 pinctrl_gpio0_default: gpio0-default { 173 conf { 174 groups = "gpio0_38_grp"; 175 bias-pull-up; 176 power-source = <IO_STANDARD_LVCMOS18>; 177 }; 178 179 mux { 180 groups = "gpio0_38_grp"; 181 function = "gpio0"; 182 }; 183 184 conf-tx { 185 pins = "MIO38"; 186 bias-disable; 187 output-enable; 188 }; 189 }; 190 191 pinctrl_uart1_default: uart1-default { 192 conf { 193 groups = "uart1_9_grp"; 194 slew-rate = <SLEW_RATE_SLOW>; 195 power-source = <IO_STANDARD_LVCMOS18>; 196 drive-strength = <12>; 197 }; 198 199 conf-rx { 200 pins = "MIO37"; 201 bias-high-impedance; 202 }; 203 204 conf-tx { 205 pins = "MIO36"; 206 bias-disable; 207 output-enable; 208 }; 209 210 mux { 211 groups = "uart1_9_grp"; 212 function = "uart1"; 213 }; 214 }; 215 216 pinctrl_i2c1_default: i2c1-default { 217 conf { 218 groups = "i2c1_6_grp"; 219 bias-pull-up; 220 slew-rate = <SLEW_RATE_SLOW>; 221 power-source = <IO_STANDARD_LVCMOS18>; 222 }; 223 224 mux { 225 groups = "i2c1_6_grp"; 226 function = "i2c1"; 227 }; 228 }; 229 230 pinctrl_i2c1_gpio: i2c1-gpio-grp { 231 conf { 232 groups = "gpio0_24_grp", "gpio0_25_grp"; 233 slew-rate = <SLEW_RATE_SLOW>; 234 power-source = <IO_STANDARD_LVCMOS18>; 235 }; 236 237 mux { 238 groups = "gpio0_24_grp", "gpio0_25_grp"; 239 function = "gpio0"; 240 }; 241 }; 242 243 pinctrl_gem3_default: gem3-default { 244 conf { 245 groups = "ethernet3_0_grp"; 246 slew-rate = <SLEW_RATE_SLOW>; 247 power-source = <IO_STANDARD_LVCMOS18>; 248 }; 249 250 conf-rx { 251 pins = "MIO70", "MIO72", "MIO74"; 252 bias-high-impedance; 253 low-power-disable; 254 }; 255 256 conf-bootstrap { 257 pins = "MIO71", "MIO73", "MIO75"; 258 bias-disable; 259 output-enable; 260 low-power-disable; 261 }; 262 263 conf-tx { 264 pins = "MIO64", "MIO65", "MIO66", 265 "MIO67", "MIO68", "MIO69"; 266 bias-disable; 267 output-enable; 268 low-power-enable; 269 }; 270 271 conf-mdio { 272 groups = "mdio3_0_grp"; 273 slew-rate = <SLEW_RATE_SLOW>; 274 power-source = <IO_STANDARD_LVCMOS18>; 275 bias-disable; 276 output-enable; 277 }; 278 279 mux-mdio { 280 function = "mdio3"; 281 groups = "mdio3_0_grp"; 282 }; 283 284 mux { 285 function = "ethernet3"; 286 groups = "ethernet3_0_grp"; 287 }; 288 }; 289 290 pinctrl_usb0_default: usb0-default { 291 conf { 292 groups = "usb0_0_grp"; 293 power-source = <IO_STANDARD_LVCMOS18>; 294 }; 295 296 conf-rx { 297 pins = "MIO52", "MIO53", "MIO55"; 298 bias-high-impedance; 299 drive-strength = <12>; 300 slew-rate = <SLEW_RATE_FAST>; 301 }; 302 303 conf-tx { 304 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 305 "MIO60", "MIO61", "MIO62", "MIO63"; 306 bias-disable; 307 output-enable; 308 drive-strength = <4>; 309 slew-rate = <SLEW_RATE_SLOW>; 310 }; 311 312 mux { 313 groups = "usb0_0_grp"; 314 function = "usb0"; 315 }; 316 }; 317 318 pinctrl_sdhci1_default: sdhci1-default { 319 conf { 320 groups = "sdio1_0_grp"; 321 slew-rate = <SLEW_RATE_SLOW>; 322 power-source = <IO_STANDARD_LVCMOS18>; 323 bias-disable; 324 }; 325 326 conf-cd { 327 groups = "sdio1_cd_0_grp"; 328 bias-high-impedance; 329 bias-pull-up; 330 slew-rate = <SLEW_RATE_SLOW>; 331 power-source = <IO_STANDARD_LVCMOS18>; 332 }; 333 334 mux-cd { 335 groups = "sdio1_cd_0_grp"; 336 function = "sdio1_cd"; 337 }; 338 339 mux { 340 groups = "sdio1_0_grp"; 341 function = "sdio1"; 342 }; 343 }; 344}; 345 346&gpio { 347 status = "okay"; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_gpio0_default>; 350}; 351 352&uart1 { 353 status = "okay"; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_uart1_default>; 356}; 357