1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * SD level shifter: 9 * "A" - A01 board un-modified (NXP) 10 * "Y" - A01 board modified with legacy interposer (Nexperia) 11 * "Z" - A01 board modified with Diode interposer 12 * 13 * Michal Simek <michal.simek@amd.com> 14 */ 15 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/net/ti-dp83867.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 20 21/dts-v1/; 22/plugin/; 23 24&{/} { 25 si5332_0: si5332-0 { /* u17 */ 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <125000000>; 29 }; 30 31 si5332_1: si5332-1 { /* u17 */ 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <25000000>; 35 }; 36 37 si5332_2: si5332-2 { /* u17 */ 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <48000000>; 41 }; 42 43 si5332_3: si5332-3 { /* u17 */ 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <24000000>; 47 }; 48 49 si5332_4: si5332-4 { /* u17 */ 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <26000000>; 53 }; 54 55 si5332_5: si5332-5 { /* u17 */ 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <27000000>; 59 }; 60}; 61 62&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 63 #address-cells = <1>; 64 #size-cells = <0>; 65 pinctrl-names = "default", "gpio"; 66 pinctrl-0 = <&pinctrl_i2c1_default>; 67 pinctrl-1 = <&pinctrl_i2c1_gpio>; 68 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 69 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 70 71 /* u14 - 0x40 - ina260 */ 72 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 73}; 74 75/* DP/USB 3.0 and SATA */ 76&psgtr { 77 status = "okay"; 78 /* pcie, usb3, sata */ 79 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 80 clock-names = "ref0", "ref1", "ref2"; 81}; 82 83&sata { 84 status = "okay"; 85 /* SATA OOB timing settings */ 86 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 87 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 88 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 89 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 90 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 91 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 92 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 93 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 94 phy-names = "sata-phy"; 95 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; 96}; 97 98&zynqmp_dpsub { 99 status = "okay"; 100 phy-names = "dp-phy0", "dp-phy1"; 101 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 102 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 103}; 104 105&zynqmp_dpdma { 106 status = "okay"; 107 assigned-clock-rates = <600000000>; 108}; 109 110&usb0 { 111 status = "okay"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_usb0_default>; 114 phy-names = "usb3-phy"; 115 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 116 /* missing usb5744 - u43 */ 117}; 118 119&dwc3_0 { 120 status = "okay"; 121 dr_mode = "host"; 122 snps,usb3_lpm_capable; 123 maximum-speed = "super-speed"; 124}; 125 126&sdhci1 { /* on CC with tuned parameters */ 127 status = "okay"; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_sdhci1_default>; 130 /* 131 * SD 3.0 requires level shifter and this property 132 * should be removed if the board has level shifter and 133 * need to work in UHS mode 134 */ 135 no-1-8-v; 136 disable-wp; 137 xlnx,mio-bank = <1>; 138 assigned-clock-rates = <187498123>; 139 bus-width = <4>; 140}; 141 142&gem3 { /* required by spec */ 143 status = "okay"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_gem3_default>; 146 phy-handle = <&phy0>; 147 phy-mode = "rgmii-id"; 148 assigned-clock-rates = <250000000>; 149 150 mdio: mdio { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 phy0: ethernet-phy@1 { 155 #phy-cells = <1>; 156 reg = <1>; 157 compatible = "ethernet-phy-id2000.a231"; 158 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 159 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 160 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 161 ti,dp83867-rxctrl-strap-quirk; 162 reset-assert-us = <100>; 163 reset-deassert-us = <280>; 164 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 165 }; 166 }; 167}; 168 169&pinctrl0 { /* required by spec */ 170 status = "okay"; 171 172 pinctrl_uart1_default: uart1-default { 173 conf { 174 groups = "uart1_9_grp"; 175 slew-rate = <SLEW_RATE_SLOW>; 176 power-source = <IO_STANDARD_LVCMOS18>; 177 drive-strength = <12>; 178 }; 179 180 conf-rx { 181 pins = "MIO37"; 182 bias-high-impedance; 183 }; 184 185 conf-tx { 186 pins = "MIO36"; 187 bias-disable; 188 }; 189 190 mux { 191 groups = "uart1_9_grp"; 192 function = "uart1"; 193 }; 194 }; 195 196 pinctrl_i2c1_default: i2c1-default { 197 conf { 198 groups = "i2c1_6_grp"; 199 bias-pull-up; 200 slew-rate = <SLEW_RATE_SLOW>; 201 power-source = <IO_STANDARD_LVCMOS18>; 202 }; 203 204 mux { 205 groups = "i2c1_6_grp"; 206 function = "i2c1"; 207 }; 208 }; 209 210 pinctrl_i2c1_gpio: i2c1-gpio { 211 conf { 212 groups = "gpio0_24_grp", "gpio0_25_grp"; 213 slew-rate = <SLEW_RATE_SLOW>; 214 power-source = <IO_STANDARD_LVCMOS18>; 215 }; 216 217 mux { 218 groups = "gpio0_24_grp", "gpio0_25_grp"; 219 function = "gpio0"; 220 }; 221 }; 222 223 pinctrl_gem3_default: gem3-default { 224 conf { 225 groups = "ethernet3_0_grp"; 226 slew-rate = <SLEW_RATE_SLOW>; 227 power-source = <IO_STANDARD_LVCMOS18>; 228 }; 229 230 conf-rx { 231 pins = "MIO70", "MIO72", "MIO74"; 232 bias-high-impedance; 233 low-power-disable; 234 }; 235 236 conf-bootstrap { 237 pins = "MIO71", "MIO73", "MIO75"; 238 bias-disable; 239 low-power-disable; 240 }; 241 242 conf-tx { 243 pins = "MIO64", "MIO65", "MIO66", 244 "MIO67", "MIO68", "MIO69"; 245 bias-disable; 246 low-power-enable; 247 }; 248 249 conf-mdio { 250 groups = "mdio3_0_grp"; 251 slew-rate = <SLEW_RATE_SLOW>; 252 power-source = <IO_STANDARD_LVCMOS18>; 253 bias-disable; 254 }; 255 256 mux-mdio { 257 function = "mdio3"; 258 groups = "mdio3_0_grp"; 259 }; 260 261 mux { 262 function = "ethernet3"; 263 groups = "ethernet3_0_grp"; 264 }; 265 }; 266 267 pinctrl_usb0_default: usb0-default { 268 conf { 269 groups = "usb0_0_grp"; 270 power-source = <IO_STANDARD_LVCMOS18>; 271 }; 272 273 conf-rx { 274 pins = "MIO52", "MIO53", "MIO55"; 275 bias-high-impedance; 276 drive-strength = <12>; 277 slew-rate = <SLEW_RATE_FAST>; 278 }; 279 280 conf-tx { 281 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 282 "MIO60", "MIO61", "MIO62", "MIO63"; 283 bias-disable; 284 drive-strength = <4>; 285 slew-rate = <SLEW_RATE_SLOW>; 286 }; 287 288 mux { 289 groups = "usb0_0_grp"; 290 function = "usb0"; 291 }; 292 }; 293 294 pinctrl_sdhci1_default: sdhci1-default { 295 conf { 296 groups = "sdio1_0_grp"; 297 slew-rate = <SLEW_RATE_SLOW>; 298 power-source = <IO_STANDARD_LVCMOS18>; 299 bias-disable; 300 }; 301 302 conf-cd { 303 groups = "sdio1_cd_0_grp"; 304 bias-high-impedance; 305 bias-pull-up; 306 slew-rate = <SLEW_RATE_SLOW>; 307 power-source = <IO_STANDARD_LVCMOS18>; 308 }; 309 310 mux-cd { 311 groups = "sdio1_cd_0_grp"; 312 function = "sdio1_cd"; 313 }; 314 315 mux { 316 groups = "sdio1_0_grp"; 317 function = "sdio1"; 318 }; 319 }; 320}; 321 322&uart1 { 323 status = "okay"; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_uart1_default>; 326}; 327