1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 14 15/ { 16 compatible = "toshiba,tmpv7708"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x81100000>; 61 reg = <0x00>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 enable-method = "spin-table"; 68 cpu-release-addr = <0x0 0x81100000>; 69 reg = <0x01>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x0 0x81100000>; 77 reg = <0x02>; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53"; 82 device_type = "cpu"; 83 enable-method = "spin-table"; 84 cpu-release-addr = <0x0 0x81100000>; 85 reg = <0x03>; 86 }; 87 88 cpu4: cpu@100 { 89 compatible = "arm,cortex-a53"; 90 device_type = "cpu"; 91 enable-method = "spin-table"; 92 cpu-release-addr = <0x0 0x81100000>; 93 reg = <0x100>; 94 }; 95 96 cpu5: cpu@101 { 97 compatible = "arm,cortex-a53"; 98 device_type = "cpu"; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0x0 0x81100000>; 101 reg = <0x101>; 102 }; 103 104 cpu6: cpu@102 { 105 compatible = "arm,cortex-a53"; 106 device_type = "cpu"; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0x0 0x81100000>; 109 reg = <0x102>; 110 }; 111 112 cpu7: cpu@103 { 113 compatible = "arm,cortex-a53"; 114 device_type = "cpu"; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0x0 0x81100000>; 117 reg = <0x103>; 118 }; 119 }; 120 121 timer { 122 compatible = "arm,armv8-timer"; 123 interrupt-parent = <&gic>; 124 interrupts = 125 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 uart_clk: uart-clk { 132 compatible = "fixed-clock"; 133 clock-frequency = <150000000>; 134 #clock-cells = <0>; 135 }; 136 137 clk25mhz: clk25mhz { 138 compatible = "fixed-clock"; 139 #clock-cells = <0>; 140 clock-frequency = <25000000>; 141 clock-output-names = "clk25mhz"; 142 }; 143 144 clk125mhz: clk125mhz { 145 compatible = "fixed-clock"; 146 clock-frequency = <125000000>; 147 #clock-cells = <0>; 148 clock-output-names = "clk125mhz"; 149 }; 150 151 clk300mhz: clk300mhz { 152 compatible = "fixed-clock"; 153 clock-frequency = <300000000>; 154 #clock-cells = <0>; 155 clock-output-names = "clk300mhz"; 156 }; 157 158 clk600mhz: clk600mhz { 159 compatible = "fixed-clock"; 160 #clock-cells = <0>; 161 clock-frequency = <600000000>; 162 clock-output-names = "clk600mhz"; 163 }; 164 165 extclk100mhz: extclk100mhz { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <100000000>; 169 clock-output-names = "extclk100mhz"; 170 }; 171 172 wdt_clk: wdt-clk { 173 compatible = "fixed-clock"; 174 clock-frequency = <150000000>; 175 #clock-cells = <0>; 176 }; 177 178 soc { 179 #address-cells = <2>; 180 #size-cells = <2>; 181 compatible = "simple-bus"; 182 interrupt-parent = <&gic>; 183 ranges; 184 185 gic: interrupt-controller@24001000 { 186 compatible = "arm,gic-400"; 187 interrupt-controller; 188 #interrupt-cells = <3>; 189 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 190 reg = <0 0x24001000 0 0x1000>, 191 <0 0x24002000 0 0x2000>, 192 <0 0x24004000 0 0x2000>, 193 <0 0x24006000 0 0x2000>; 194 }; 195 196 pmux: pmux@24190000 { 197 compatible = "toshiba,tmpv7708-pinctrl"; 198 reg = <0 0x24190000 0 0x10000>; 199 }; 200 201 gpio: gpio@28020000 { 202 compatible = "toshiba,gpio-tmpv7708"; 203 reg = <0 0x28020000 0 0x1000>; 204 #gpio-cells = <0x2>; 205 gpio-ranges = <&pmux 0 0 32>; 206 gpio-controller; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 interrupt-parent = <&gic>; 210 }; 211 212 uart0: serial@28200000 { 213 compatible = "arm,pl011", "arm,primecell"; 214 reg = <0 0x28200000 0 0x1000>; 215 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&uart0_pins>; 218 status = "disabled"; 219 }; 220 221 uart1: serial@28201000 { 222 compatible = "arm,pl011", "arm,primecell"; 223 reg = <0 0x28201000 0 0x1000>; 224 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&uart1_pins>; 227 status = "disabled"; 228 }; 229 230 uart2: serial@28202000 { 231 compatible = "arm,pl011", "arm,primecell"; 232 reg = <0 0x28202000 0 0x1000>; 233 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart2_pins>; 236 status = "disabled"; 237 }; 238 239 uart3: serial@28203000 { 240 compatible = "arm,pl011", "arm,primecell"; 241 reg = <0 0x28203000 0 0x1000>; 242 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart3_pins>; 245 status = "disabled"; 246 }; 247 248 i2c0: i2c@28030000 { 249 compatible = "snps,designware-i2c"; 250 reg = <0 0x28030000 0 0x1000>; 251 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&i2c0_pins>; 254 clock-frequency = <400000>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 status = "disabled"; 258 }; 259 260 i2c1: i2c@28031000 { 261 compatible = "snps,designware-i2c"; 262 reg = <0 0x28031000 0 0x1000>; 263 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&i2c1_pins>; 266 clock-frequency = <400000>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 status = "disabled"; 270 }; 271 272 i2c2: i2c@28032000 { 273 compatible = "snps,designware-i2c"; 274 reg = <0 0x28032000 0 0x1000>; 275 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&i2c2_pins>; 278 clock-frequency = <400000>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 status = "disabled"; 282 }; 283 284 i2c3: i2c@28033000 { 285 compatible = "snps,designware-i2c"; 286 reg = <0 0x28033000 0 0x1000>; 287 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&i2c3_pins>; 290 clock-frequency = <400000>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 }; 295 296 i2c4: i2c@28034000 { 297 compatible = "snps,designware-i2c"; 298 reg = <0 0x28034000 0 0x1000>; 299 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c4_pins>; 302 clock-frequency = <400000>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 status = "disabled"; 306 }; 307 308 i2c5: i2c@28035000 { 309 compatible = "snps,designware-i2c"; 310 reg = <0 0x28035000 0 0x1000>; 311 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&i2c5_pins>; 314 clock-frequency = <400000>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 status = "disabled"; 318 }; 319 320 i2c6: i2c@28036000 { 321 compatible = "snps,designware-i2c"; 322 reg = <0 0x28036000 0 0x1000>; 323 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c6_pins>; 326 clock-frequency = <400000>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 status = "disabled"; 330 }; 331 332 i2c7: i2c@28037000 { 333 compatible = "snps,designware-i2c"; 334 reg = <0 0x28037000 0 0x1000>; 335 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&i2c7_pins>; 338 clock-frequency = <400000>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 i2c8: i2c@28038000 { 345 compatible = "snps,designware-i2c"; 346 reg = <0 0x28038000 0 0x1000>; 347 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&i2c8_pins>; 350 clock-frequency = <400000>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 status = "disabled"; 354 }; 355 356 spi0: spi@28140000 { 357 compatible = "arm,pl022", "arm,primecell"; 358 reg = <0 0x28140000 0 0x1000>; 359 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&spi0_pins>; 362 num-cs = <1>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 status = "disabled"; 366 }; 367 368 spi1: spi@28141000 { 369 compatible = "arm,pl022", "arm,primecell"; 370 reg = <0 0x28141000 0 0x1000>; 371 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&spi1_pins>; 374 num-cs = <1>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 status = "disabled"; 378 }; 379 380 spi2: spi@28142000 { 381 compatible = "arm,pl022", "arm,primecell"; 382 reg = <0 0x28142000 0 0x1000>; 383 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&spi2_pins>; 386 num-cs = <1>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 status = "disabled"; 390 }; 391 392 spi3: spi@28143000 { 393 compatible = "arm,pl022", "arm,primecell"; 394 reg = <0 0x28143000 0 0x1000>; 395 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&spi3_pins>; 398 num-cs = <1>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 status = "disabled"; 402 }; 403 404 spi4: spi@28144000 { 405 compatible = "arm,pl022", "arm,primecell"; 406 reg = <0 0x28144000 0 0x1000>; 407 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&spi4_pins>; 410 num-cs = <1>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 status = "disabled"; 414 }; 415 416 spi5: spi@28145000 { 417 compatible = "arm,pl022", "arm,primecell"; 418 reg = <0 0x28145000 0 0x1000>; 419 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&spi5_pins>; 422 num-cs = <1>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 spi6: spi@28146000 { 429 compatible = "arm,pl022", "arm,primecell"; 430 reg = <0 0x28146000 0 0x1000>; 431 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&spi6_pins>; 434 num-cs = <1>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 status = "disabled"; 438 }; 439 440 piether: ethernet@28000000 { 441 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 442 reg = <0 0x28000000 0 0x10000>; 443 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 444 interrupt-names = "macirq"; 445 snps,txpbl = <4>; 446 snps,rxpbl = <4>; 447 snps,tso; 448 status = "disabled"; 449 }; 450 451 wdt: wdt@28330000 { 452 compatible = "toshiba,visconti-wdt"; 453 reg = <0 0x28330000 0 0x1000>; 454 status = "disabled"; 455 }; 456 457 pwm: pwm@241c0000 { 458 compatible = "toshiba,visconti-pwm"; 459 reg = <0 0x241c0000 0 0x1000>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm_mux>; 462 #pwm-cells = <2>; 463 status = "disabled"; 464 }; 465 466 pcie: pcie@28400000 { 467 compatible = "toshiba,visconti-pcie"; 468 reg = <0x0 0x28400000 0x0 0x00400000>, 469 <0x0 0x70000000 0x0 0x10000000>, 470 <0x0 0x28050000 0x0 0x00010000>, 471 <0x0 0x24200000 0x0 0x00002000>, 472 <0x0 0x24162000 0x0 0x00001000>; 473 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 474 device_type = "pci"; 475 bus-range = <0x00 0xff>; 476 num-lanes = <2>; 477 num-viewport = <8>; 478 479 #address-cells = <3>; 480 #size-cells = <2>; 481 #interrupt-cells = <1>; 482 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 483 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 484 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 486 interrupt-names = "msi", "intr"; 487 interrupt-map-mask = <0 0 0 7>; 488 interrupt-map = 489 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 490 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 491 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 492 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 493 max-link-speed = <2>; 494 status = "disabled"; 495 }; 496 }; 497}; 498 499#include "tmpv7708_pins.dtsi" 500