1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/clock/toshiba,tmpv770x.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 15 16/ { 17 compatible = "toshiba,tmpv7708"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0x0 0x81100000>; 62 reg = <0x00>; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x0 0x81100000>; 70 reg = <0x01>; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0x0 0x81100000>; 78 reg = <0x02>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0x0 0x81100000>; 86 reg = <0x03>; 87 }; 88 89 cpu4: cpu@100 { 90 compatible = "arm,cortex-a53"; 91 device_type = "cpu"; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0x0 0x81100000>; 94 reg = <0x100>; 95 }; 96 97 cpu5: cpu@101 { 98 compatible = "arm,cortex-a53"; 99 device_type = "cpu"; 100 enable-method = "spin-table"; 101 cpu-release-addr = <0x0 0x81100000>; 102 reg = <0x101>; 103 }; 104 105 cpu6: cpu@102 { 106 compatible = "arm,cortex-a53"; 107 device_type = "cpu"; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0x0 0x81100000>; 110 reg = <0x102>; 111 }; 112 113 cpu7: cpu@103 { 114 compatible = "arm,cortex-a53"; 115 device_type = "cpu"; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0x0 0x81100000>; 118 reg = <0x103>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupt-parent = <&gic>; 125 interrupts = 126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 130 }; 131 132 extclk100mhz: extclk100mhz { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <100000000>; 136 clock-output-names = "extclk100mhz"; 137 }; 138 139 osc2_clk: osc2-clk { 140 compatible = "fixed-clock"; 141 clock-frequency = <20000000>; 142 #clock-cells = <0>; 143 }; 144 145 soc { 146 #address-cells = <2>; 147 #size-cells = <2>; 148 compatible = "simple-bus"; 149 interrupt-parent = <&gic>; 150 ranges; 151 152 gic: interrupt-controller@24001000 { 153 compatible = "arm,gic-400"; 154 interrupt-controller; 155 #address-cells = <0>; 156 #interrupt-cells = <3>; 157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 158 reg = <0 0x24001000 0 0x1000>, 159 <0 0x24002000 0 0x2000>, 160 <0 0x24004000 0 0x2000>, 161 <0 0x24006000 0 0x2000>; 162 }; 163 164 pmux: pmux@24190000 { 165 compatible = "toshiba,tmpv7708-pinctrl"; 166 reg = <0 0x24190000 0 0x10000>; 167 }; 168 169 gpio: gpio@28020000 { 170 compatible = "toshiba,gpio-tmpv7708"; 171 reg = <0 0x28020000 0 0x1000>; 172 #gpio-cells = <0x2>; 173 gpio-ranges = <&pmux 0 0 32>; 174 gpio-controller; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 interrupt-parent = <&gic>; 178 }; 179 180 pipllct: clock-controller@24220000 { 181 compatible = "toshiba,tmpv7708-pipllct"; 182 reg = <0 0x24220000 0 0x820>; 183 #clock-cells = <1>; 184 clocks = <&osc2_clk>; 185 }; 186 187 pismu: syscon@24200000 { 188 compatible = "toshiba,tmpv7708-pismu", "syscon"; 189 reg = <0 0x24200000 0 0x2140>; 190 #clock-cells = <1>; 191 #reset-cells = <1>; 192 }; 193 194 uart0: serial@28200000 { 195 compatible = "arm,pl011", "arm,primecell"; 196 reg = <0 0x28200000 0 0x1000>; 197 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&uart0_pins>; 200 clocks = <&pismu TMPV770X_CLK_PIUART0>, <&pismu TMPV770X_CLK_PIUART0>; 201 clock-names = "uartclk", "apb_pclk"; 202 status = "disabled"; 203 }; 204 205 uart1: serial@28201000 { 206 compatible = "arm,pl011", "arm,primecell"; 207 reg = <0 0x28201000 0 0x1000>; 208 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&uart1_pins>; 211 clocks = <&pismu TMPV770X_CLK_PIUART1>, <&pismu TMPV770X_CLK_PIUART1>; 212 clock-names = "uartclk", "apb_pclk"; 213 status = "disabled"; 214 }; 215 216 uart2: serial@28202000 { 217 compatible = "arm,pl011", "arm,primecell"; 218 reg = <0 0x28202000 0 0x1000>; 219 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&uart2_pins>; 222 clocks = <&pismu TMPV770X_CLK_PIUART2>, <&pismu TMPV770X_CLK_PIUART2>; 223 clock-names = "uartclk", "apb_pclk"; 224 status = "disabled"; 225 }; 226 227 uart3: serial@28203000 { 228 compatible = "arm,pl011", "arm,primecell"; 229 reg = <0 0x28203000 0 0x1000>; 230 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&uart3_pins>; 233 clocks = <&pismu TMPV770X_CLK_PIUART2>, <&pismu TMPV770X_CLK_PIUART2>; 234 clock-names = "uartclk", "apb_pclk"; 235 status = "disabled"; 236 }; 237 238 i2c0: i2c@28030000 { 239 compatible = "snps,designware-i2c"; 240 reg = <0 0x28030000 0 0x1000>; 241 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&i2c0_pins>; 244 clock-frequency = <400000>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 clocks = <&pismu TMPV770X_CLK_PII2C0>; 248 status = "disabled"; 249 }; 250 251 i2c1: i2c@28031000 { 252 compatible = "snps,designware-i2c"; 253 reg = <0 0x28031000 0 0x1000>; 254 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&i2c1_pins>; 257 clock-frequency = <400000>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 clocks = <&pismu TMPV770X_CLK_PII2C1>; 261 status = "disabled"; 262 }; 263 264 i2c2: i2c@28032000 { 265 compatible = "snps,designware-i2c"; 266 reg = <0 0x28032000 0 0x1000>; 267 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&i2c2_pins>; 270 clock-frequency = <400000>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 clocks = <&pismu TMPV770X_CLK_PII2C2>; 274 status = "disabled"; 275 }; 276 277 i2c3: i2c@28033000 { 278 compatible = "snps,designware-i2c"; 279 reg = <0 0x28033000 0 0x1000>; 280 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c3_pins>; 283 clock-frequency = <400000>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&pismu TMPV770X_CLK_PII2C3>; 287 status = "disabled"; 288 }; 289 290 i2c4: i2c@28034000 { 291 compatible = "snps,designware-i2c"; 292 reg = <0 0x28034000 0 0x1000>; 293 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c4_pins>; 296 clock-frequency = <400000>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 clocks = <&pismu TMPV770X_CLK_PII2C4>; 300 status = "disabled"; 301 }; 302 303 i2c5: i2c@28035000 { 304 compatible = "snps,designware-i2c"; 305 reg = <0 0x28035000 0 0x1000>; 306 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c5_pins>; 309 clock-frequency = <400000>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 clocks = <&pismu TMPV770X_CLK_PII2C5>; 313 status = "disabled"; 314 }; 315 316 i2c6: i2c@28036000 { 317 compatible = "snps,designware-i2c"; 318 reg = <0 0x28036000 0 0x1000>; 319 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&i2c6_pins>; 322 clock-frequency = <400000>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 clocks = <&pismu TMPV770X_CLK_PII2C6>; 326 status = "disabled"; 327 }; 328 329 i2c7: i2c@28037000 { 330 compatible = "snps,designware-i2c"; 331 reg = <0 0x28037000 0 0x1000>; 332 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&i2c7_pins>; 335 clock-frequency = <400000>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 clocks = <&pismu TMPV770X_CLK_PII2C7>; 339 status = "disabled"; 340 }; 341 342 i2c8: i2c@28038000 { 343 compatible = "snps,designware-i2c"; 344 reg = <0 0x28038000 0 0x1000>; 345 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&i2c8_pins>; 348 clock-frequency = <400000>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 clocks = <&pismu TMPV770X_CLK_PII2C8>; 352 status = "disabled"; 353 }; 354 355 spi0: spi@28140000 { 356 compatible = "arm,pl022", "arm,primecell"; 357 reg = <0 0x28140000 0 0x1000>; 358 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&spi0_pins>; 361 num-cs = <1>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 clocks = <&pismu TMPV770X_CLK_PISPI1>, <&pismu TMPV770X_CLK_PISPI1>; 365 clock-names = "sspclk", "apb_pclk"; 366 status = "disabled"; 367 }; 368 369 spi1: spi@28141000 { 370 compatible = "arm,pl022", "arm,primecell"; 371 reg = <0 0x28141000 0 0x1000>; 372 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&spi1_pins>; 375 num-cs = <1>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&pismu TMPV770X_CLK_PISPI1>, <&pismu TMPV770X_CLK_PISPI1>; 379 clock-names = "sspclk", "apb_pclk"; 380 status = "disabled"; 381 }; 382 383 spi2: spi@28142000 { 384 compatible = "arm,pl022", "arm,primecell"; 385 reg = <0 0x28142000 0 0x1000>; 386 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&spi2_pins>; 389 num-cs = <1>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 clocks = <&pismu TMPV770X_CLK_PISPI2>, <&pismu TMPV770X_CLK_PISPI2>; 393 clock-names = "sspclk", "apb_pclk"; 394 status = "disabled"; 395 }; 396 397 spi3: spi@28143000 { 398 compatible = "arm,pl022", "arm,primecell"; 399 reg = <0 0x28143000 0 0x1000>; 400 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&spi3_pins>; 403 num-cs = <1>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 clocks = <&pismu TMPV770X_CLK_PISPI3>, <&pismu TMPV770X_CLK_PISPI3>; 407 clock-names = "sspclk", "apb_pclk"; 408 status = "disabled"; 409 }; 410 411 spi4: spi@28144000 { 412 compatible = "arm,pl022", "arm,primecell"; 413 reg = <0 0x28144000 0 0x1000>; 414 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&spi4_pins>; 417 num-cs = <1>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 clocks = <&pismu TMPV770X_CLK_PISPI4>, <&pismu TMPV770X_CLK_PISPI4>; 421 clock-names = "sspclk", "apb_pclk"; 422 status = "disabled"; 423 }; 424 425 spi5: spi@28145000 { 426 compatible = "arm,pl022", "arm,primecell"; 427 reg = <0 0x28145000 0 0x1000>; 428 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&spi5_pins>; 431 num-cs = <1>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 clocks = <&pismu TMPV770X_CLK_PISPI5>, <&pismu TMPV770X_CLK_PISPI5>; 435 clock-names = "sspclk", "apb_pclk"; 436 status = "disabled"; 437 }; 438 439 spi6: spi@28146000 { 440 compatible = "arm,pl022", "arm,primecell"; 441 reg = <0 0x28146000 0 0x1000>; 442 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&spi6_pins>; 445 num-cs = <1>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 clocks = <&pismu TMPV770X_CLK_PISPI6>, <&pismu TMPV770X_CLK_PISPI6>; 449 clock-names = "sspclk", "apb_pclk"; 450 status = "disabled"; 451 }; 452 453 piether: ethernet@28000000 { 454 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 455 reg = <0 0x28000000 0 0x10000>; 456 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 457 interrupt-names = "macirq"; 458 snps,txpbl = <4>; 459 snps,rxpbl = <4>; 460 snps,tso; 461 clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>; 462 clock-names = "stmmaceth", "phy_ref_clk"; 463 status = "disabled"; 464 }; 465 466 wdt: wdt@28330000 { 467 compatible = "toshiba,visconti-wdt"; 468 reg = <0 0x28330000 0 0x1000>; 469 clocks = <&pismu TMPV770X_CLK_WDTCLK>; 470 status = "disabled"; 471 }; 472 473 pwm: pwm@241c0000 { 474 compatible = "toshiba,visconti-pwm"; 475 reg = <0 0x241c0000 0 0x1000>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pwm_mux>; 478 #pwm-cells = <2>; 479 status = "disabled"; 480 }; 481 482 pcie: pcie@28400000 { 483 compatible = "toshiba,visconti-pcie"; 484 reg = <0x0 0x28400000 0x0 0x00400000>, 485 <0x0 0x70000000 0x0 0x10000000>, 486 <0x0 0x28050000 0x0 0x00010000>, 487 <0x0 0x24200000 0x0 0x00002000>, 488 <0x0 0x24162000 0x0 0x00001000>; 489 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 490 device_type = "pci"; 491 bus-range = <0x00 0xff>; 492 num-lanes = <2>; 493 num-viewport = <8>; 494 495 #address-cells = <3>; 496 #size-cells = <2>; 497 #interrupt-cells = <1>; 498 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 499 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 500 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "msi", "intr"; 503 interrupt-map-mask = <0 0 0 7>; 504 interrupt-map = 505 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 506 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 507 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 508 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 509 max-link-speed = <2>; 510 clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>; 511 clock-names = "ref", "core", "aux"; 512 status = "disabled"; 513 }; 514 }; 515}; 516 517#include "tmpv7708_pins.dtsi" 518