1*518d432fSYuji Ishikawa// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*518d432fSYuji Ishikawa/* 3*518d432fSYuji Ishikawa * Device Tree File for TMPV7708 VisROBO VRC SoM 4*518d432fSYuji Ishikawa * 5*518d432fSYuji Ishikawa * (C) Copyright 2020, 2021, Toshiba Corporation. 6*518d432fSYuji Ishikawa * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7*518d432fSYuji Ishikawa */ 8*518d432fSYuji Ishikawa 9*518d432fSYuji Ishikawa/dts-v1/; 10*518d432fSYuji Ishikawa 11*518d432fSYuji Ishikawa#include "tmpv7708.dtsi" 12*518d432fSYuji Ishikawa#include <dt-bindings/gpio/gpio.h> 13*518d432fSYuji Ishikawa 14*518d432fSYuji Ishikawa&wdt { 15*518d432fSYuji Ishikawa status = "okay"; 16*518d432fSYuji Ishikawa}; 17*518d432fSYuji Ishikawa 18*518d432fSYuji Ishikawa&gpio { 19*518d432fSYuji Ishikawa status = "okay"; 20*518d432fSYuji Ishikawa}; 21*518d432fSYuji Ishikawa 22*518d432fSYuji Ishikawa&spi0_pins { 23*518d432fSYuji Ishikawa groups = "spi0_grp", "spi0_cs0_grp"; 24*518d432fSYuji Ishikawa}; 25*518d432fSYuji Ishikawa 26*518d432fSYuji Ishikawa&spi0 { 27*518d432fSYuji Ishikawa status = "okay"; 28*518d432fSYuji Ishikawa 29*518d432fSYuji Ishikawa mmc-slot@0 { 30*518d432fSYuji Ishikawa compatible = "mmc-spi-slot"; 31*518d432fSYuji Ishikawa reg = <0>; 32*518d432fSYuji Ishikawa gpios = <&gpio 15 GPIO_ACTIVE_LOW>; 33*518d432fSYuji Ishikawa voltage-ranges = <3200 3400>; 34*518d432fSYuji Ishikawa spi-max-frequency = <12000000>; 35*518d432fSYuji Ishikawa }; 36*518d432fSYuji Ishikawa}; 37*518d432fSYuji Ishikawa 38*518d432fSYuji Ishikawa&i2c0 { 39*518d432fSYuji Ishikawa status = "okay"; 40*518d432fSYuji Ishikawa}; 41