1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family 4 * 5 * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 6 * 7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 * 9 */ 10 11#include "k3-j784s4-j742s2-common.dtsi" 12 13/ { 14 model = "Texas Instruments K3 J784S4 SoC"; 15 compatible = "ti,j784s4"; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 cpu-map { 21 cluster0: cluster0 { 22 core0 { 23 cpu = <&cpu0>; 24 }; 25 26 core1 { 27 cpu = <&cpu1>; 28 }; 29 30 core2 { 31 cpu = <&cpu2>; 32 }; 33 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 39 cluster1: cluster1 { 40 core0 { 41 cpu = <&cpu4>; 42 }; 43 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 52 core3 { 53 cpu = <&cpu7>; 54 }; 55 }; 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a72"; 60 reg = <0x000>; 61 device_type = "cpu"; 62 enable-method = "psci"; 63 i-cache-size = <0xc000>; 64 i-cache-line-size = <64>; 65 i-cache-sets = <256>; 66 d-cache-size = <0x8000>; 67 d-cache-line-size = <64>; 68 d-cache-sets = <256>; 69 next-level-cache = <&L2_0>; 70 }; 71 72 cpu1: cpu@1 { 73 compatible = "arm,cortex-a72"; 74 reg = <0x001>; 75 device_type = "cpu"; 76 enable-method = "psci"; 77 i-cache-size = <0xc000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <256>; 83 next-level-cache = <&L2_0>; 84 }; 85 86 cpu2: cpu@2 { 87 compatible = "arm,cortex-a72"; 88 reg = <0x002>; 89 device_type = "cpu"; 90 enable-method = "psci"; 91 i-cache-size = <0xc000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <256>; 97 next-level-cache = <&L2_0>; 98 }; 99 100 cpu3: cpu@3 { 101 compatible = "arm,cortex-a72"; 102 reg = <0x003>; 103 device_type = "cpu"; 104 enable-method = "psci"; 105 i-cache-size = <0xc000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <256>; 111 next-level-cache = <&L2_0>; 112 }; 113 114 cpu4: cpu@100 { 115 compatible = "arm,cortex-a72"; 116 reg = <0x100>; 117 device_type = "cpu"; 118 enable-method = "psci"; 119 i-cache-size = <0xc000>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <256>; 122 d-cache-size = <0x8000>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <256>; 125 next-level-cache = <&L2_1>; 126 }; 127 128 cpu5: cpu@101 { 129 compatible = "arm,cortex-a72"; 130 reg = <0x101>; 131 device_type = "cpu"; 132 enable-method = "psci"; 133 i-cache-size = <0xc000>; 134 i-cache-line-size = <64>; 135 i-cache-sets = <256>; 136 d-cache-size = <0x8000>; 137 d-cache-line-size = <64>; 138 d-cache-sets = <256>; 139 next-level-cache = <&L2_1>; 140 }; 141 142 cpu6: cpu@102 { 143 compatible = "arm,cortex-a72"; 144 reg = <0x102>; 145 device_type = "cpu"; 146 enable-method = "psci"; 147 i-cache-size = <0xc000>; 148 i-cache-line-size = <64>; 149 i-cache-sets = <256>; 150 d-cache-size = <0x8000>; 151 d-cache-line-size = <64>; 152 d-cache-sets = <256>; 153 next-level-cache = <&L2_1>; 154 }; 155 156 cpu7: cpu@103 { 157 compatible = "arm,cortex-a72"; 158 reg = <0x103>; 159 device_type = "cpu"; 160 enable-method = "psci"; 161 i-cache-size = <0xc000>; 162 i-cache-line-size = <64>; 163 i-cache-sets = <256>; 164 d-cache-size = <0x8000>; 165 d-cache-line-size = <64>; 166 d-cache-sets = <256>; 167 next-level-cache = <&L2_1>; 168 }; 169 }; 170}; 171 172#include "k3-j784s4-main.dtsi" 173