1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 bootph-all; 11 compatible = "ti,k2g-sci"; 12 ti,host-id = <12>; 13 14 mbox-names = "rx", "tx"; 15 16 mboxes = <&secure_proxy_main 11>, 17 <&secure_proxy_main 13>; 18 19 reg-names = "debug_messages"; 20 reg = <0x00 0x44083000 0x00 0x1000>; 21 22 k3_pds: power-controller { 23 bootph-all; 24 compatible = "ti,sci-pm-domain"; 25 #power-domain-cells = <2>; 26 }; 27 28 k3_clks: clock-controller { 29 bootph-all; 30 compatible = "ti,k2g-sci-clk"; 31 #clock-cells = <2>; 32 }; 33 34 k3_reset: reset-controller { 35 bootph-all; 36 compatible = "ti,sci-reset"; 37 #reset-cells = <2>; 38 }; 39 }; 40 41 wkup_conf: bus@43000000 { 42 bootph-all; 43 compatible = "simple-bus"; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x00 0x43000000 0x20000>; 47 48 chipid: chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x14 0x4>; 52 }; 53 }; 54 55 secure_proxy_sa3: mailbox@43600000 { 56 compatible = "ti,am654-secure-proxy"; 57 #mbox-cells = <1>; 58 reg-names = "target_data", "rt", "scfg"; 59 reg = <0x00 0x43600000 0x00 0x10000>, 60 <0x00 0x44880000 0x00 0x20000>, 61 <0x00 0x44860000 0x00 0x20000>; 62 /* 63 * Marked Disabled: 64 * Node is incomplete as it is meant for bootloaders and 65 * firmware on non-MPU processors 66 */ 67 status = "disabled"; 68 }; 69 70 mcu_ram: sram@41c00000 { 71 compatible = "mmio-sram"; 72 reg = <0x00 0x41c00000 0x00 0x100000>; 73 ranges = <0x00 0x00 0x41c00000 0x100000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 }; 77 78 wkup_pmx0: pinctrl@4301c000 { 79 compatible = "pinctrl-single"; 80 /* Proxy 0 addressing */ 81 reg = <0x00 0x4301c000 0x00 0x034>; 82 #pinctrl-cells = <1>; 83 pinctrl-single,register-width = <32>; 84 pinctrl-single,function-mask = <0xffffffff>; 85 }; 86 87 wkup_pmx1: pinctrl@4301c038 { 88 compatible = "pinctrl-single"; 89 /* Proxy 0 addressing */ 90 reg = <0x00 0x4301c038 0x00 0x02c>; 91 #pinctrl-cells = <1>; 92 pinctrl-single,register-width = <32>; 93 pinctrl-single,function-mask = <0xffffffff>; 94 }; 95 96 wkup_pmx2: pinctrl@4301c068 { 97 compatible = "pinctrl-single"; 98 /* Proxy 0 addressing */ 99 reg = <0x00 0x4301c068 0x00 0x120>; 100 #pinctrl-cells = <1>; 101 pinctrl-single,register-width = <32>; 102 pinctrl-single,function-mask = <0xffffffff>; 103 }; 104 105 wkup_pmx3: pinctrl@4301c190 { 106 compatible = "pinctrl-single"; 107 /* Proxy 0 addressing */ 108 reg = <0x00 0x4301c190 0x00 0x004>; 109 #pinctrl-cells = <1>; 110 pinctrl-single,register-width = <32>; 111 pinctrl-single,function-mask = <0xffffffff>; 112 }; 113 114 wkup_gpio_intr: interrupt-controller@42200000 { 115 compatible = "ti,sci-intr"; 116 reg = <0x00 0x42200000 0x00 0x400>; 117 ti,intr-trigger-type = <1>; 118 interrupt-controller; 119 interrupt-parent = <&gic500>; 120 #interrupt-cells = <1>; 121 ti,sci = <&sms>; 122 ti,sci-dev-id = <177>; 123 ti,interrupt-ranges = <16 960 16>; 124 }; 125 126 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 127 mcu_timerio_input: pinctrl@40f04200 { 128 compatible = "pinctrl-single"; 129 reg = <0x00 0x40f04200 0x00 0x28>; 130 #pinctrl-cells = <1>; 131 pinctrl-single,register-width = <32>; 132 pinctrl-single,function-mask = <0x0000000f>; 133 /* Non-MPU Firmware usage */ 134 status = "reserved"; 135 }; 136 137 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 138 mcu_timerio_output: pinctrl@40f04280 { 139 compatible = "pinctrl-single"; 140 reg = <0x00 0x40f04280 0x00 0x28>; 141 #pinctrl-cells = <1>; 142 pinctrl-single,register-width = <32>; 143 pinctrl-single,function-mask = <0x0000000f>; 144 /* Non-MPU Firmware usage */ 145 status = "reserved"; 146 }; 147 148 mcu_conf: syscon@40f00000 { 149 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 150 reg = <0x00 0x40f00000 0x00 0x20000>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0x00 0x00 0x40f00000 0x20000>; 154 155 phy_gmii_sel: phy@4040 { 156 compatible = "ti,am654-phy-gmii-sel"; 157 reg = <0x4040 0x4>; 158 #phy-cells = <1>; 159 }; 160 }; 161 162 mcu_timer0: timer@40400000 { 163 compatible = "ti,am654-timer"; 164 reg = <0x00 0x40400000 0x00 0x400>; 165 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&k3_clks 35 2>; 167 clock-names = "fck"; 168 assigned-clocks = <&k3_clks 35 2>; 169 assigned-clock-parents = <&k3_clks 35 3>; 170 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 171 ti,timer-pwm; 172 /* Non-MPU Firmware usage */ 173 status = "reserved"; 174 }; 175 176 mcu_timer1: timer@40410000 { 177 bootph-all; 178 compatible = "ti,am654-timer"; 179 reg = <0x00 0x40410000 0x00 0x400>; 180 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&k3_clks 117 2>; 182 clock-names = "fck"; 183 assigned-clocks = <&k3_clks 117 2>; 184 assigned-clock-parents = <&k3_clks 117 3>; 185 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; 186 ti,timer-pwm; 187 /* Non-MPU Firmware usage */ 188 status = "reserved"; 189 }; 190 191 mcu_timer2: timer@40420000 { 192 compatible = "ti,am654-timer"; 193 reg = <0x00 0x40420000 0x00 0x400>; 194 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&k3_clks 118 2>; 196 clock-names = "fck"; 197 assigned-clocks = <&k3_clks 118 2>; 198 assigned-clock-parents = <&k3_clks 118 3>; 199 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; 200 ti,timer-pwm; 201 /* Non-MPU Firmware usage */ 202 status = "reserved"; 203 }; 204 205 mcu_timer3: timer@40430000 { 206 compatible = "ti,am654-timer"; 207 reg = <0x00 0x40430000 0x00 0x400>; 208 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&k3_clks 119 2>; 210 clock-names = "fck"; 211 assigned-clocks = <&k3_clks 119 2>; 212 assigned-clock-parents = <&k3_clks 119 3>; 213 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 214 ti,timer-pwm; 215 /* Non-MPU Firmware usage */ 216 status = "reserved"; 217 }; 218 219 mcu_timer4: timer@40440000 { 220 compatible = "ti,am654-timer"; 221 reg = <0x00 0x40440000 0x00 0x400>; 222 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&k3_clks 120 2>; 224 clock-names = "fck"; 225 assigned-clocks = <&k3_clks 120 2>; 226 assigned-clock-parents = <&k3_clks 120 3>; 227 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 228 ti,timer-pwm; 229 /* Non-MPU Firmware usage */ 230 status = "reserved"; 231 }; 232 233 mcu_timer5: timer@40450000 { 234 compatible = "ti,am654-timer"; 235 reg = <0x00 0x40450000 0x00 0x400>; 236 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&k3_clks 121 2>; 238 clock-names = "fck"; 239 assigned-clocks = <&k3_clks 121 2>; 240 assigned-clock-parents = <&k3_clks 121 3>; 241 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 242 ti,timer-pwm; 243 /* Non-MPU Firmware usage */ 244 status = "reserved"; 245 }; 246 247 mcu_timer6: timer@40460000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x40460000 0x00 0x400>; 250 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 122 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 122 2>; 254 assigned-clock-parents = <&k3_clks 122 3>; 255 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 /* Non-MPU Firmware usage */ 258 status = "reserved"; 259 }; 260 261 mcu_timer7: timer@40470000 { 262 compatible = "ti,am654-timer"; 263 reg = <0x00 0x40470000 0x00 0x400>; 264 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&k3_clks 123 2>; 266 clock-names = "fck"; 267 assigned-clocks = <&k3_clks 123 2>; 268 assigned-clock-parents = <&k3_clks 123 3>; 269 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; 270 ti,timer-pwm; 271 /* Non-MPU Firmware usage */ 272 status = "reserved"; 273 }; 274 275 mcu_timer8: timer@40480000 { 276 compatible = "ti,am654-timer"; 277 reg = <0x00 0x40480000 0x00 0x400>; 278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 124 2>; 280 clock-names = "fck"; 281 assigned-clocks = <&k3_clks 124 2>; 282 assigned-clock-parents = <&k3_clks 124 3>; 283 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; 284 ti,timer-pwm; 285 /* Non-MPU Firmware usage */ 286 status = "reserved"; 287 }; 288 289 mcu_timer9: timer@40490000 { 290 compatible = "ti,am654-timer"; 291 reg = <0x00 0x40490000 0x00 0x400>; 292 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&k3_clks 125 2>; 294 clock-names = "fck"; 295 assigned-clocks = <&k3_clks 125 2>; 296 assigned-clock-parents = <&k3_clks 125 3>; 297 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 298 ti,timer-pwm; 299 /* Non-MPU Firmware usage */ 300 status = "reserved"; 301 }; 302 303 wkup_uart0: serial@42300000 { 304 compatible = "ti,j721e-uart", "ti,am654-uart"; 305 reg = <0x00 0x42300000 0x00 0x200>; 306 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&k3_clks 397 0>; 308 clock-names = "fclk"; 309 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; 310 status = "disabled"; 311 }; 312 313 mcu_uart0: serial@40a00000 { 314 compatible = "ti,j721e-uart", "ti,am654-uart"; 315 reg = <0x00 0x40a00000 0x00 0x200>; 316 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&k3_clks 149 0>; 318 clock-names = "fclk"; 319 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 320 status = "disabled"; 321 }; 322 323 wkup_gpio0: gpio@42110000 { 324 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 325 reg = <0x00 0x42110000 0x00 0x100>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupt-parent = <&wkup_gpio_intr>; 329 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 330 interrupt-controller; 331 #interrupt-cells = <2>; 332 ti,ngpio = <89>; 333 ti,davinci-gpio-unbanked = <0>; 334 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 335 clocks = <&k3_clks 167 0>; 336 clock-names = "gpio"; 337 status = "disabled"; 338 }; 339 340 wkup_gpio1: gpio@42100000 { 341 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 342 reg = <0x00 0x42100000 0x00 0x100>; 343 gpio-controller; 344 #gpio-cells = <2>; 345 interrupt-parent = <&wkup_gpio_intr>; 346 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 ti,ngpio = <89>; 350 ti,davinci-gpio-unbanked = <0>; 351 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 352 clocks = <&k3_clks 168 0>; 353 clock-names = "gpio"; 354 status = "disabled"; 355 }; 356 357 wkup_i2c0: i2c@42120000 { 358 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 359 reg = <0x00 0x42120000 0x00 0x100>; 360 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 clocks = <&k3_clks 279 2>; 364 clock-names = "fck"; 365 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 366 status = "disabled"; 367 }; 368 369 mcu_i2c0: i2c@40b00000 { 370 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 371 reg = <0x00 0x40b00000 0x00 0x100>; 372 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 clocks = <&k3_clks 277 2>; 376 clock-names = "fck"; 377 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 378 status = "disabled"; 379 }; 380 381 mcu_i2c1: i2c@40b10000 { 382 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 383 reg = <0x00 0x40b10000 0x00 0x100>; 384 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 clocks = <&k3_clks 278 2>; 388 clock-names = "fck"; 389 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 390 status = "disabled"; 391 }; 392 393 mcu_mcan0: can@40528000 { 394 compatible = "bosch,m_can"; 395 reg = <0x00 0x40528000 0x00 0x200>, 396 <0x00 0x40500000 0x00 0x8000>; 397 reg-names = "m_can", "message_ram"; 398 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>; 399 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>; 400 clock-names = "hclk", "cclk"; 401 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "int0", "int1"; 404 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 405 status = "disabled"; 406 }; 407 408 mcu_mcan1: can@40568000 { 409 compatible = "bosch,m_can"; 410 reg = <0x00 0x40568000 0x00 0x200>, 411 <0x00 0x40540000 0x00 0x8000>; 412 reg-names = "m_can", "message_ram"; 413 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 414 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>; 415 clock-names = "hclk", "cclk"; 416 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 418 interrupt-names = "int0", "int1"; 419 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 420 status = "disabled"; 421 }; 422 423 mcu_spi0: spi@40300000 { 424 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 425 reg = <0x00 0x040300000 0x00 0x400>; 426 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; 430 clocks = <&k3_clks 384 0>; 431 status = "disabled"; 432 }; 433 434 mcu_spi1: spi@40310000 { 435 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 436 reg = <0x00 0x040310000 0x00 0x400>; 437 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; 441 clocks = <&k3_clks 385 0>; 442 status = "disabled"; 443 }; 444 445 mcu_spi2: spi@40320000 { 446 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 447 reg = <0x00 0x040320000 0x00 0x400>; 448 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; 452 clocks = <&k3_clks 386 0>; 453 status = "disabled"; 454 }; 455 456 mcu_navss: bus@28380000 { 457 bootph-all; 458 compatible = "simple-bus"; 459 #address-cells = <2>; 460 #size-cells = <2>; 461 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 462 ti,sci-dev-id = <323>; 463 dma-coherent; 464 dma-ranges; 465 466 mcu_ringacc: ringacc@2b800000 { 467 bootph-all; 468 compatible = "ti,am654-navss-ringacc"; 469 reg = <0x00 0x2b800000 0x00 0x400000>, 470 <0x00 0x2b000000 0x00 0x400000>, 471 <0x00 0x28590000 0x00 0x100>, 472 <0x00 0x2a500000 0x00 0x40000>, 473 <0x00 0x28440000 0x00 0x40000>; 474 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 475 ti,num-rings = <286>; 476 ti,sci-rm-range-gp-rings = <0x1>; 477 ti,sci = <&sms>; 478 ti,sci-dev-id = <328>; 479 msi-parent = <&main_udmass_inta>; 480 }; 481 482 mcu_udmap: dma-controller@285c0000 { 483 bootph-all; 484 compatible = "ti,j721e-navss-mcu-udmap"; 485 reg = <0x00 0x285c0000 0x00 0x100>, 486 <0x00 0x2a800000 0x00 0x40000>, 487 <0x00 0x2aa00000 0x00 0x40000>, 488 <0x00 0x284a0000 0x00 0x4000>, 489 <0x00 0x284c0000 0x00 0x4000>, 490 <0x00 0x28400000 0x00 0x2000>; 491 reg-names = "gcfg", "rchanrt", "tchanrt", 492 "tchan", "rchan", "rflow"; 493 msi-parent = <&main_udmass_inta>; 494 #dma-cells = <1>; 495 496 ti,sci = <&sms>; 497 ti,sci-dev-id = <329>; 498 ti,ringacc = <&mcu_ringacc>; 499 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 500 <0x0f>; /* TX_HCHAN */ 501 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 502 <0x0b>; /* RX_HCHAN */ 503 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 504 }; 505 }; 506 507 secure_proxy_mcu: mailbox@2a480000 { 508 compatible = "ti,am654-secure-proxy"; 509 #mbox-cells = <1>; 510 reg-names = "target_data", "rt", "scfg"; 511 reg = <0x00 0x2a480000 0x00 0x80000>, 512 <0x00 0x2a380000 0x00 0x80000>, 513 <0x00 0x2a400000 0x00 0x80000>; 514 /* 515 * Marked Disabled: 516 * Node is incomplete as it is meant for bootloaders and 517 * firmware on non-MPU processors 518 */ 519 status = "disabled"; 520 }; 521 522 mcu_cpsw: ethernet@46000000 { 523 compatible = "ti,j721e-cpsw-nuss"; 524 #address-cells = <2>; 525 #size-cells = <2>; 526 reg = <0x00 0x46000000 0x00 0x200000>; 527 reg-names = "cpsw_nuss"; 528 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 529 dma-coherent; 530 clocks = <&k3_clks 63 0>; 531 clock-names = "fck"; 532 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 533 534 dmas = <&mcu_udmap 0xf000>, 535 <&mcu_udmap 0xf001>, 536 <&mcu_udmap 0xf002>, 537 <&mcu_udmap 0xf003>, 538 <&mcu_udmap 0xf004>, 539 <&mcu_udmap 0xf005>, 540 <&mcu_udmap 0xf006>, 541 <&mcu_udmap 0xf007>, 542 <&mcu_udmap 0x7000>; 543 dma-names = "tx0", "tx1", "tx2", "tx3", 544 "tx4", "tx5", "tx6", "tx7", 545 "rx"; 546 status = "disabled"; 547 548 ethernet-ports { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 552 mcu_cpsw_port1: port@1 { 553 reg = <1>; 554 ti,mac-only; 555 label = "port1"; 556 ti,syscon-efuse = <&mcu_conf 0x200>; 557 phys = <&phy_gmii_sel 1>; 558 }; 559 }; 560 561 davinci_mdio: mdio@f00 { 562 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 563 reg = <0x00 0xf00 0x00 0x100>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 clocks = <&k3_clks 63 0>; 567 clock-names = "fck"; 568 bus_freq = <1000000>; 569 }; 570 571 cpts@3d000 { 572 compatible = "ti,am65-cpts"; 573 reg = <0x00 0x3d000 0x00 0x400>; 574 clocks = <&k3_clks 63 3>; 575 clock-names = "cpts"; 576 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */ 577 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */ 578 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 579 interrupt-names = "cpts"; 580 ti,cpts-ext-ts-inputs = <4>; 581 ti,cpts-periodic-outputs = <2>; 582 }; 583 }; 584 585 mcu_r5fss0: r5fss@41000000 { 586 compatible = "ti,j721s2-r5fss"; 587 ti,cluster-mode = <1>; 588 #address-cells = <1>; 589 #size-cells = <1>; 590 ranges = <0x41000000 0x00 0x41000000 0x20000>, 591 <0x41400000 0x00 0x41400000 0x20000>; 592 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 593 594 mcu_r5fss0_core0: r5f@41000000 { 595 compatible = "ti,j721s2-r5f"; 596 reg = <0x41000000 0x00010000>, 597 <0x41010000 0x00010000>; 598 reg-names = "atcm", "btcm"; 599 ti,sci = <&sms>; 600 ti,sci-dev-id = <346>; 601 ti,sci-proc-ids = <0x01 0xff>; 602 resets = <&k3_reset 346 1>; 603 firmware-name = "j784s4-mcu-r5f0_0-fw"; 604 ti,atcm-enable = <1>; 605 ti,btcm-enable = <1>; 606 ti,loczrama = <1>; 607 }; 608 609 mcu_r5fss0_core1: r5f@41400000 { 610 compatible = "ti,j721s2-r5f"; 611 reg = <0x41400000 0x00010000>, 612 <0x41410000 0x00010000>; 613 reg-names = "atcm", "btcm"; 614 ti,sci = <&sms>; 615 ti,sci-dev-id = <347>; 616 ti,sci-proc-ids = <0x02 0xff>; 617 resets = <&k3_reset 347 1>; 618 firmware-name = "j784s4-mcu-r5f0_1-fw"; 619 ti,atcm-enable = <1>; 620 ti,btcm-enable = <1>; 621 ti,loczrama = <1>; 622 }; 623 }; 624 625 wkup_vtm0: temperature-sensor@42040000 { 626 compatible = "ti,j7200-vtm"; 627 reg = <0x00 0x42040000 0x00 0x350>, 628 <0x00 0x42050000 0x00 0x350>; 629 power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; 630 #thermal-sensor-cells = <1>; 631 }; 632 633 tscadc0: tscadc@40200000 { 634 compatible = "ti,am3359-tscadc"; 635 reg = <0x00 0x40200000 0x00 0x1000>; 636 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 637 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 638 clocks = <&k3_clks 0 0>; 639 assigned-clocks = <&k3_clks 0 2>; 640 assigned-clock-rates = <60000000>; 641 clock-names = "fck"; 642 dmas = <&main_udmap 0x7400>, 643 <&main_udmap 0x7401>; 644 dma-names = "fifo0", "fifo1"; 645 status = "disabled"; 646 647 adc { 648 #io-channel-cells = <1>; 649 compatible = "ti,am3359-adc"; 650 }; 651 }; 652 653 tscadc1: tscadc@40210000 { 654 compatible = "ti,am3359-tscadc"; 655 reg = <0x00 0x40210000 0x00 0x1000>; 656 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 657 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 658 clocks = <&k3_clks 1 0>; 659 assigned-clocks = <&k3_clks 1 2>; 660 assigned-clock-rates = <60000000>; 661 clock-names = "fck"; 662 dmas = <&main_udmap 0x7402>, 663 <&main_udmap 0x7403>; 664 dma-names = "fifo0", "fifo1"; 665 status = "disabled"; 666 667 adc { 668 #io-channel-cells = <1>; 669 compatible = "ti,am3359-adc"; 670 }; 671 }; 672 673 fss: bus@47000000 { 674 compatible = "simple-bus"; 675 #address-cells = <2>; 676 #size-cells = <2>; 677 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 678 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 679 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ 680 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */ 681 <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ 682 683 ospi0: spi@47040000 { 684 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 685 reg = <0x00 0x47040000 0x00 0x100>, 686 <0x05 0x0000000 0x01 0x0000000>; 687 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 688 cdns,fifo-depth = <256>; 689 cdns,fifo-width = <4>; 690 cdns,trigger-address = <0x0>; 691 clocks = <&k3_clks 161 7>; 692 assigned-clocks = <&k3_clks 161 7>; 693 assigned-clock-parents = <&k3_clks 161 9>; 694 assigned-clock-rates = <166666666>; 695 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 status = "disabled"; 699 }; 700 701 ospi1: spi@47050000 { 702 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 703 reg = <0x00 0x47050000 0x00 0x100>, 704 <0x07 0x0000000 0x01 0x0000000>; 705 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 706 cdns,fifo-depth = <256>; 707 cdns,fifo-width = <4>; 708 cdns,trigger-address = <0x0>; 709 clocks = <&k3_clks 162 7>; 710 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 status = "disabled"; 714 }; 715 }; 716 717 mcu_esm: esm@40800000 { 718 compatible = "ti,j721e-esm"; 719 reg = <0x00 0x40800000 0x00 0x1000>; 720 ti,esm-pins = <95>; 721 bootph-pre-ram; 722 }; 723 724 wkup_esm: esm@42080000 { 725 compatible = "ti,j721e-esm"; 726 reg = <0x00 0x42080000 0x00 0x1000>; 727 ti,esm-pins = <63>; 728 bootph-pre-ram; 729 }; 730 731 /* 732 * The 2 RTI instances are couple with MCU R5Fs so keeping them 733 * reserved as these will be used by their respective firmware 734 */ 735 mcu_watchdog0: watchdog@40600000 { 736 compatible = "ti,j7-rti-wdt"; 737 reg = <0x00 0x40600000 0x00 0x100>; 738 clocks = <&k3_clks 367 1>; 739 power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>; 740 assigned-clocks = <&k3_clks 367 0>; 741 assigned-clock-parents = <&k3_clks 367 4>; 742 /* reserved for MCU_R5F0_0 */ 743 status = "reserved"; 744 }; 745 746 mcu_watchdog1: watchdog@40610000 { 747 compatible = "ti,j7-rti-wdt"; 748 reg = <0x00 0x40610000 0x00 0x100>; 749 clocks = <&k3_clks 368 1>; 750 power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>; 751 assigned-clocks = <&k3_clks 368 0>; 752 assigned-clock-parents = <&k3_clks 368 4>; 753 /* reserved for MCU_R5F0_1 */ 754 status = "reserved"; 755 }; 756}; 757