1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 bootph-all; 11 compatible = "ti,k2g-sci"; 12 ti,host-id = <12>; 13 14 mbox-names = "rx", "tx"; 15 16 mboxes = <&secure_proxy_main 11>, 17 <&secure_proxy_main 13>; 18 19 reg-names = "debug_messages"; 20 reg = <0x00 0x44083000 0x00 0x1000>; 21 22 k3_pds: power-controller { 23 bootph-all; 24 compatible = "ti,sci-pm-domain"; 25 #power-domain-cells = <2>; 26 }; 27 28 k3_clks: clock-controller { 29 bootph-all; 30 compatible = "ti,k2g-sci-clk"; 31 #clock-cells = <2>; 32 }; 33 34 k3_reset: reset-controller { 35 bootph-all; 36 compatible = "ti,sci-reset"; 37 #reset-cells = <2>; 38 }; 39 }; 40 41 wkup_conf: bus@43000000 { 42 bootph-all; 43 compatible = "simple-bus"; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x00 0x43000000 0x20000>; 47 48 chipid: chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x14 0x4>; 52 }; 53 }; 54 55 secure_proxy_sa3: mailbox@43600000 { 56 compatible = "ti,am654-secure-proxy"; 57 #mbox-cells = <1>; 58 reg-names = "target_data", "rt", "scfg"; 59 reg = <0x00 0x43600000 0x00 0x10000>, 60 <0x00 0x44880000 0x00 0x20000>, 61 <0x00 0x44860000 0x00 0x20000>; 62 /* 63 * Marked Disabled: 64 * Node is incomplete as it is meant for bootloaders and 65 * firmware on non-MPU processors 66 */ 67 status = "disabled"; 68 }; 69 70 mcu_ram: sram@41c00000 { 71 compatible = "mmio-sram"; 72 reg = <0x00 0x41c00000 0x00 0x100000>; 73 ranges = <0x00 0x00 0x41c00000 0x100000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 }; 77 78 wkup_pmx0: pinctrl@4301c000 { 79 compatible = "pinctrl-single"; 80 /* Proxy 0 addressing */ 81 reg = <0x00 0x4301c000 0x00 0x034>; 82 #pinctrl-cells = <1>; 83 pinctrl-single,register-width = <32>; 84 pinctrl-single,function-mask = <0xffffffff>; 85 }; 86 87 wkup_pmx1: pinctrl@4301c038 { 88 compatible = "pinctrl-single"; 89 /* Proxy 0 addressing */ 90 reg = <0x00 0x4301c038 0x00 0x02c>; 91 #pinctrl-cells = <1>; 92 pinctrl-single,register-width = <32>; 93 pinctrl-single,function-mask = <0xffffffff>; 94 }; 95 96 wkup_pmx2: pinctrl@4301c068 { 97 compatible = "pinctrl-single"; 98 /* Proxy 0 addressing */ 99 reg = <0x00 0x4301c068 0x00 0x120>; 100 #pinctrl-cells = <1>; 101 pinctrl-single,register-width = <32>; 102 pinctrl-single,function-mask = <0xffffffff>; 103 }; 104 105 wkup_pmx3: pinctrl@4301c190 { 106 compatible = "pinctrl-single"; 107 /* Proxy 0 addressing */ 108 reg = <0x00 0x4301c190 0x00 0x004>; 109 #pinctrl-cells = <1>; 110 pinctrl-single,register-width = <32>; 111 pinctrl-single,function-mask = <0xffffffff>; 112 }; 113 114 wkup_gpio_intr: interrupt-controller@42200000 { 115 compatible = "ti,sci-intr"; 116 reg = <0x00 0x42200000 0x00 0x400>; 117 ti,intr-trigger-type = <1>; 118 interrupt-controller; 119 interrupt-parent = <&gic500>; 120 #interrupt-cells = <1>; 121 ti,sci = <&sms>; 122 ti,sci-dev-id = <177>; 123 ti,interrupt-ranges = <16 960 16>; 124 }; 125 126 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 127 mcu_timerio_input: pinctrl@40f04200 { 128 compatible = "pinctrl-single"; 129 reg = <0x00 0x40f04200 0x00 0x28>; 130 #pinctrl-cells = <1>; 131 pinctrl-single,register-width = <32>; 132 pinctrl-single,function-mask = <0x0000000f>; 133 /* Non-MPU Firmware usage */ 134 status = "reserved"; 135 }; 136 137 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 138 mcu_timerio_output: pinctrl@40f04280 { 139 compatible = "pinctrl-single"; 140 reg = <0x00 0x40f04280 0x00 0x28>; 141 #pinctrl-cells = <1>; 142 pinctrl-single,register-width = <32>; 143 pinctrl-single,function-mask = <0x0000000f>; 144 /* Non-MPU Firmware usage */ 145 status = "reserved"; 146 }; 147 148 mcu_conf: syscon@40f00000 { 149 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 150 reg = <0x00 0x40f00000 0x00 0x20000>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0x00 0x00 0x40f00000 0x20000>; 154 155 phy_gmii_sel: phy@4040 { 156 compatible = "ti,am654-phy-gmii-sel"; 157 reg = <0x4040 0x4>; 158 #phy-cells = <1>; 159 }; 160 }; 161 162 mcu_timer0: timer@40400000 { 163 compatible = "ti,am654-timer"; 164 reg = <0x00 0x40400000 0x00 0x400>; 165 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&k3_clks 35 2>; 167 clock-names = "fck"; 168 assigned-clocks = <&k3_clks 35 2>; 169 assigned-clock-parents = <&k3_clks 35 3>; 170 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 171 ti,timer-pwm; 172 /* Non-MPU Firmware usage */ 173 status = "reserved"; 174 }; 175 176 mcu_timer1: timer@40410000 { 177 bootph-all; 178 compatible = "ti,am654-timer"; 179 reg = <0x00 0x40410000 0x00 0x400>; 180 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&k3_clks 117 2>; 182 clock-names = "fck"; 183 assigned-clocks = <&k3_clks 117 2>; 184 assigned-clock-parents = <&k3_clks 117 3>; 185 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; 186 ti,timer-pwm; 187 /* Non-MPU Firmware usage */ 188 status = "reserved"; 189 }; 190 191 mcu_timer2: timer@40420000 { 192 compatible = "ti,am654-timer"; 193 reg = <0x00 0x40420000 0x00 0x400>; 194 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&k3_clks 118 2>; 196 clock-names = "fck"; 197 assigned-clocks = <&k3_clks 118 2>; 198 assigned-clock-parents = <&k3_clks 118 3>; 199 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; 200 ti,timer-pwm; 201 /* Non-MPU Firmware usage */ 202 status = "reserved"; 203 }; 204 205 mcu_timer3: timer@40430000 { 206 compatible = "ti,am654-timer"; 207 reg = <0x00 0x40430000 0x00 0x400>; 208 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&k3_clks 119 2>; 210 clock-names = "fck"; 211 assigned-clocks = <&k3_clks 119 2>; 212 assigned-clock-parents = <&k3_clks 119 3>; 213 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 214 ti,timer-pwm; 215 /* Non-MPU Firmware usage */ 216 status = "reserved"; 217 }; 218 219 mcu_timer4: timer@40440000 { 220 compatible = "ti,am654-timer"; 221 reg = <0x00 0x40440000 0x00 0x400>; 222 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&k3_clks 120 2>; 224 clock-names = "fck"; 225 assigned-clocks = <&k3_clks 120 2>; 226 assigned-clock-parents = <&k3_clks 120 3>; 227 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 228 ti,timer-pwm; 229 /* Non-MPU Firmware usage */ 230 status = "reserved"; 231 }; 232 233 mcu_timer5: timer@40450000 { 234 compatible = "ti,am654-timer"; 235 reg = <0x00 0x40450000 0x00 0x400>; 236 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&k3_clks 121 2>; 238 clock-names = "fck"; 239 assigned-clocks = <&k3_clks 121 2>; 240 assigned-clock-parents = <&k3_clks 121 3>; 241 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 242 ti,timer-pwm; 243 /* Non-MPU Firmware usage */ 244 status = "reserved"; 245 }; 246 247 mcu_timer6: timer@40460000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x40460000 0x00 0x400>; 250 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 122 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 122 2>; 254 assigned-clock-parents = <&k3_clks 122 3>; 255 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 /* Non-MPU Firmware usage */ 258 status = "reserved"; 259 }; 260 261 mcu_timer7: timer@40470000 { 262 compatible = "ti,am654-timer"; 263 reg = <0x00 0x40470000 0x00 0x400>; 264 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&k3_clks 123 2>; 266 clock-names = "fck"; 267 assigned-clocks = <&k3_clks 123 2>; 268 assigned-clock-parents = <&k3_clks 123 3>; 269 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; 270 ti,timer-pwm; 271 /* Non-MPU Firmware usage */ 272 status = "reserved"; 273 }; 274 275 mcu_timer8: timer@40480000 { 276 compatible = "ti,am654-timer"; 277 reg = <0x00 0x40480000 0x00 0x400>; 278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 124 2>; 280 clock-names = "fck"; 281 assigned-clocks = <&k3_clks 124 2>; 282 assigned-clock-parents = <&k3_clks 124 3>; 283 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; 284 ti,timer-pwm; 285 /* Non-MPU Firmware usage */ 286 status = "reserved"; 287 }; 288 289 mcu_timer9: timer@40490000 { 290 compatible = "ti,am654-timer"; 291 reg = <0x00 0x40490000 0x00 0x400>; 292 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&k3_clks 125 2>; 294 clock-names = "fck"; 295 assigned-clocks = <&k3_clks 125 2>; 296 assigned-clock-parents = <&k3_clks 125 3>; 297 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 298 ti,timer-pwm; 299 /* Non-MPU Firmware usage */ 300 status = "reserved"; 301 }; 302 303 wkup_uart0: serial@42300000 { 304 compatible = "ti,j721e-uart", "ti,am654-uart"; 305 reg = <0x00 0x42300000 0x00 0x200>; 306 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 307 current-speed = <115200>; 308 clocks = <&k3_clks 397 0>; 309 clock-names = "fclk"; 310 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; 311 status = "disabled"; 312 }; 313 314 mcu_uart0: serial@40a00000 { 315 compatible = "ti,j721e-uart", "ti,am654-uart"; 316 reg = <0x00 0x40a00000 0x00 0x200>; 317 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 318 current-speed = <115200>; 319 clocks = <&k3_clks 149 0>; 320 clock-names = "fclk"; 321 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 322 status = "disabled"; 323 }; 324 325 wkup_gpio0: gpio@42110000 { 326 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 327 reg = <0x00 0x42110000 0x00 0x100>; 328 gpio-controller; 329 #gpio-cells = <2>; 330 interrupt-parent = <&wkup_gpio_intr>; 331 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 ti,ngpio = <89>; 335 ti,davinci-gpio-unbanked = <0>; 336 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 337 clocks = <&k3_clks 167 0>; 338 clock-names = "gpio"; 339 status = "disabled"; 340 }; 341 342 wkup_gpio1: gpio@42100000 { 343 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 344 reg = <0x00 0x42100000 0x00 0x100>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-parent = <&wkup_gpio_intr>; 348 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 ti,ngpio = <89>; 352 ti,davinci-gpio-unbanked = <0>; 353 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 354 clocks = <&k3_clks 168 0>; 355 clock-names = "gpio"; 356 status = "disabled"; 357 }; 358 359 wkup_i2c0: i2c@42120000 { 360 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 361 reg = <0x00 0x42120000 0x00 0x100>; 362 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 clocks = <&k3_clks 279 2>; 366 clock-names = "fck"; 367 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 368 status = "disabled"; 369 }; 370 371 mcu_i2c0: i2c@40b00000 { 372 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 373 reg = <0x00 0x40b00000 0x00 0x100>; 374 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 clocks = <&k3_clks 277 2>; 378 clock-names = "fck"; 379 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 380 status = "disabled"; 381 }; 382 383 mcu_i2c1: i2c@40b10000 { 384 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 385 reg = <0x00 0x40b10000 0x00 0x100>; 386 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 clocks = <&k3_clks 278 2>; 390 clock-names = "fck"; 391 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 392 status = "disabled"; 393 }; 394 395 mcu_mcan0: can@40528000 { 396 compatible = "bosch,m_can"; 397 reg = <0x00 0x40528000 0x00 0x200>, 398 <0x00 0x40500000 0x00 0x8000>; 399 reg-names = "m_can", "message_ram"; 400 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>; 402 clock-names = "hclk", "cclk"; 403 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 405 interrupt-names = "int0", "int1"; 406 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 407 status = "disabled"; 408 }; 409 410 mcu_mcan1: can@40568000 { 411 compatible = "bosch,m_can"; 412 reg = <0x00 0x40568000 0x00 0x200>, 413 <0x00 0x40540000 0x00 0x8000>; 414 reg-names = "m_can", "message_ram"; 415 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>; 417 clock-names = "hclk", "cclk"; 418 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 420 interrupt-names = "int0", "int1"; 421 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 422 status = "disabled"; 423 }; 424 425 mcu_spi0: spi@40300000 { 426 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 427 reg = <0x00 0x040300000 0x00 0x400>; 428 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; 432 clocks = <&k3_clks 384 0>; 433 status = "disabled"; 434 }; 435 436 mcu_spi1: spi@40310000 { 437 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 438 reg = <0x00 0x040310000 0x00 0x400>; 439 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; 443 clocks = <&k3_clks 385 0>; 444 status = "disabled"; 445 }; 446 447 mcu_spi2: spi@40320000 { 448 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 449 reg = <0x00 0x040320000 0x00 0x400>; 450 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; 454 clocks = <&k3_clks 386 0>; 455 status = "disabled"; 456 }; 457 458 mcu_navss: bus@28380000 { 459 bootph-all; 460 compatible = "simple-bus"; 461 #address-cells = <2>; 462 #size-cells = <2>; 463 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 464 ti,sci-dev-id = <323>; 465 dma-coherent; 466 dma-ranges; 467 468 mcu_ringacc: ringacc@2b800000 { 469 bootph-all; 470 compatible = "ti,am654-navss-ringacc"; 471 reg = <0x00 0x2b800000 0x00 0x400000>, 472 <0x00 0x2b000000 0x00 0x400000>, 473 <0x00 0x28590000 0x00 0x100>, 474 <0x00 0x2a500000 0x00 0x40000>, 475 <0x00 0x28440000 0x00 0x40000>; 476 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 477 ti,num-rings = <286>; 478 ti,sci-rm-range-gp-rings = <0x1>; 479 ti,sci = <&sms>; 480 ti,sci-dev-id = <328>; 481 msi-parent = <&main_udmass_inta>; 482 }; 483 484 mcu_udmap: dma-controller@285c0000 { 485 bootph-all; 486 compatible = "ti,j721e-navss-mcu-udmap"; 487 reg = <0x00 0x285c0000 0x00 0x100>, 488 <0x00 0x2a800000 0x00 0x40000>, 489 <0x00 0x2aa00000 0x00 0x40000>, 490 <0x00 0x284a0000 0x00 0x4000>, 491 <0x00 0x284c0000 0x00 0x4000>, 492 <0x00 0x28400000 0x00 0x2000>; 493 reg-names = "gcfg", "rchanrt", "tchanrt", 494 "tchan", "rchan", "rflow"; 495 msi-parent = <&main_udmass_inta>; 496 #dma-cells = <1>; 497 498 ti,sci = <&sms>; 499 ti,sci-dev-id = <329>; 500 ti,ringacc = <&mcu_ringacc>; 501 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 502 <0x0f>; /* TX_HCHAN */ 503 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 504 <0x0b>; /* RX_HCHAN */ 505 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 506 }; 507 }; 508 509 secure_proxy_mcu: mailbox@2a480000 { 510 compatible = "ti,am654-secure-proxy"; 511 #mbox-cells = <1>; 512 reg-names = "target_data", "rt", "scfg"; 513 reg = <0x00 0x2a480000 0x00 0x80000>, 514 <0x00 0x2a380000 0x00 0x80000>, 515 <0x00 0x2a400000 0x00 0x80000>; 516 /* 517 * Marked Disabled: 518 * Node is incomplete as it is meant for bootloaders and 519 * firmware on non-MPU processors 520 */ 521 status = "disabled"; 522 }; 523 524 mcu_cpsw: ethernet@46000000 { 525 compatible = "ti,j721e-cpsw-nuss"; 526 #address-cells = <2>; 527 #size-cells = <2>; 528 reg = <0x00 0x46000000 0x00 0x200000>; 529 reg-names = "cpsw_nuss"; 530 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 531 dma-coherent; 532 clocks = <&k3_clks 63 0>; 533 clock-names = "fck"; 534 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 535 536 dmas = <&mcu_udmap 0xf000>, 537 <&mcu_udmap 0xf001>, 538 <&mcu_udmap 0xf002>, 539 <&mcu_udmap 0xf003>, 540 <&mcu_udmap 0xf004>, 541 <&mcu_udmap 0xf005>, 542 <&mcu_udmap 0xf006>, 543 <&mcu_udmap 0xf007>, 544 <&mcu_udmap 0x7000>; 545 dma-names = "tx0", "tx1", "tx2", "tx3", 546 "tx4", "tx5", "tx6", "tx7", 547 "rx"; 548 status = "disabled"; 549 550 ethernet-ports { 551 #address-cells = <1>; 552 #size-cells = <0>; 553 554 mcu_cpsw_port1: port@1 { 555 reg = <1>; 556 ti,mac-only; 557 label = "port1"; 558 ti,syscon-efuse = <&mcu_conf 0x200>; 559 phys = <&phy_gmii_sel 1>; 560 }; 561 }; 562 563 davinci_mdio: mdio@f00 { 564 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 565 reg = <0x00 0xf00 0x00 0x100>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&k3_clks 63 0>; 569 clock-names = "fck"; 570 bus_freq = <1000000>; 571 }; 572 573 cpts@3d000 { 574 compatible = "ti,am65-cpts"; 575 reg = <0x00 0x3d000 0x00 0x400>; 576 clocks = <&k3_clks 63 3>; 577 clock-names = "cpts"; 578 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */ 579 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */ 580 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 581 interrupt-names = "cpts"; 582 ti,cpts-ext-ts-inputs = <4>; 583 ti,cpts-periodic-outputs = <2>; 584 }; 585 }; 586 587 mcu_r5fss0: r5fss@41000000 { 588 compatible = "ti,j721s2-r5fss"; 589 ti,cluster-mode = <1>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges = <0x41000000 0x00 0x41000000 0x20000>, 593 <0x41400000 0x00 0x41400000 0x20000>; 594 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 595 596 mcu_r5fss0_core0: r5f@41000000 { 597 compatible = "ti,j721s2-r5f"; 598 reg = <0x41000000 0x00010000>, 599 <0x41010000 0x00010000>; 600 reg-names = "atcm", "btcm"; 601 ti,sci = <&sms>; 602 ti,sci-dev-id = <346>; 603 ti,sci-proc-ids = <0x01 0xff>; 604 resets = <&k3_reset 346 1>; 605 firmware-name = "j784s4-mcu-r5f0_0-fw"; 606 ti,atcm-enable = <1>; 607 ti,btcm-enable = <1>; 608 ti,loczrama = <1>; 609 }; 610 611 mcu_r5fss0_core1: r5f@41400000 { 612 compatible = "ti,j721s2-r5f"; 613 reg = <0x41400000 0x00010000>, 614 <0x41410000 0x00010000>; 615 reg-names = "atcm", "btcm"; 616 ti,sci = <&sms>; 617 ti,sci-dev-id = <347>; 618 ti,sci-proc-ids = <0x02 0xff>; 619 resets = <&k3_reset 347 1>; 620 firmware-name = "j784s4-mcu-r5f0_1-fw"; 621 ti,atcm-enable = <1>; 622 ti,btcm-enable = <1>; 623 ti,loczrama = <1>; 624 }; 625 }; 626 627 wkup_vtm0: temperature-sensor@42040000 { 628 compatible = "ti,j7200-vtm"; 629 reg = <0x00 0x42040000 0x00 0x350>, 630 <0x00 0x42050000 0x00 0x350>; 631 power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; 632 #thermal-sensor-cells = <1>; 633 }; 634 635 tscadc0: tscadc@40200000 { 636 compatible = "ti,am3359-tscadc"; 637 reg = <0x00 0x40200000 0x00 0x1000>; 638 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 639 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 640 clocks = <&k3_clks 0 0>; 641 assigned-clocks = <&k3_clks 0 2>; 642 assigned-clock-rates = <60000000>; 643 clock-names = "fck"; 644 dmas = <&main_udmap 0x7400>, 645 <&main_udmap 0x7401>; 646 dma-names = "fifo0", "fifo1"; 647 status = "disabled"; 648 649 adc { 650 #io-channel-cells = <1>; 651 compatible = "ti,am3359-adc"; 652 }; 653 }; 654 655 tscadc1: tscadc@40210000 { 656 compatible = "ti,am3359-tscadc"; 657 reg = <0x00 0x40210000 0x00 0x1000>; 658 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 659 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 660 clocks = <&k3_clks 1 0>; 661 assigned-clocks = <&k3_clks 1 2>; 662 assigned-clock-rates = <60000000>; 663 clock-names = "fck"; 664 dmas = <&main_udmap 0x7402>, 665 <&main_udmap 0x7403>; 666 dma-names = "fifo0", "fifo1"; 667 status = "disabled"; 668 669 adc { 670 #io-channel-cells = <1>; 671 compatible = "ti,am3359-adc"; 672 }; 673 }; 674 675 fss: bus@47000000 { 676 compatible = "simple-bus"; 677 reg = <0x00 0x47000000 0x00 0x100>; 678 #address-cells = <2>; 679 #size-cells = <2>; 680 ranges; 681 682 ospi0: spi@47040000 { 683 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 684 reg = <0x00 0x47040000 0x00 0x100>, 685 <0x05 0x0000000 0x01 0x0000000>; 686 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 687 cdns,fifo-depth = <256>; 688 cdns,fifo-width = <4>; 689 cdns,trigger-address = <0x0>; 690 clocks = <&k3_clks 161 7>; 691 assigned-clocks = <&k3_clks 161 7>; 692 assigned-clock-parents = <&k3_clks 161 9>; 693 assigned-clock-rates = <166666666>; 694 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 ospi1: spi@47050000 { 701 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 702 reg = <0x00 0x47050000 0x00 0x100>, 703 <0x07 0x0000000 0x01 0x0000000>; 704 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 705 cdns,fifo-depth = <256>; 706 cdns,fifo-width = <4>; 707 cdns,trigger-address = <0x0>; 708 clocks = <&k3_clks 162 7>; 709 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 }; 715 716 mcu_esm: esm@40800000 { 717 compatible = "ti,j721e-esm"; 718 reg = <0x00 0x40800000 0x00 0x1000>; 719 ti,esm-pins = <95>; 720 bootph-pre-ram; 721 }; 722 723 wkup_esm: esm@42080000 { 724 compatible = "ti,j721e-esm"; 725 reg = <0x00 0x42080000 0x00 0x1000>; 726 ti,esm-pins = <63>; 727 bootph-pre-ram; 728 }; 729 730 /* 731 * The 2 RTI instances are couple with MCU R5Fs so keeping them 732 * reserved as these will be used by their respective firmware 733 */ 734 mcu_watchdog0: watchdog@40600000 { 735 compatible = "ti,j7-rti-wdt"; 736 reg = <0x00 0x40600000 0x00 0x100>; 737 clocks = <&k3_clks 367 1>; 738 power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>; 739 assigned-clocks = <&k3_clks 367 0>; 740 assigned-clock-parents = <&k3_clks 367 4>; 741 /* reserved for MCU_R5F0_0 */ 742 status = "reserved"; 743 }; 744 745 mcu_watchdog1: watchdog@40610000 { 746 compatible = "ti,j7-rti-wdt"; 747 reg = <0x00 0x40610000 0x00 0x100>; 748 clocks = <&k3_clks 368 1>; 749 power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>; 750 assigned-clocks = <&k3_clks 368 0>; 751 assigned-clock-parents = <&k3_clks 368 4>; 752 /* reserved for MCU_R5F0_1 */ 753 status = "reserved"; 754 }; 755}; 756