1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 c71_3: dsp@67800000 { 10 compatible = "ti,j721s2-c71-dsp"; 11 reg = <0x00 0x67800000 0x00 0x00080000>, 12 <0x00 0x67e00000 0x00 0x0000c000>; 13 reg-names = "l2sram", "l1dram"; 14 resets = <&k3_reset 40 1>; 15 firmware-name = "j784s4-c71_3-fw"; 16 ti,sci = <&sms>; 17 ti,sci-dev-id = <40>; 18 ti,sci-proc-ids = <0x33 0xff>; 19 status = "disabled"; 20 }; 21 22 pcie2_rc: pcie@2920000 { 23 compatible = "ti,j784s4-pcie-host"; 24 reg = <0x00 0x02920000 0x00 0x1000>, 25 <0x00 0x02927000 0x00 0x400>, 26 <0x00 0x0e000000 0x00 0x00800000>, 27 <0x44 0x00000000 0x00 0x00001000>; 28 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 29 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 30 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 31 interrupt-names = "link_state"; 32 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 33 device_type = "pci"; 34 max-link-speed = <3>; 35 num-lanes = <2>; 36 power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; 37 clocks = <&k3_clks 334 0>; 38 clock-names = "fck"; 39 #address-cells = <3>; 40 #size-cells = <2>; 41 bus-range = <0x0 0xff>; 42 vendor-id = <0x104c>; 43 device-id = <0xb012>; 44 msi-map = <0x0 &gic_its 0x20000 0x10000>; 45 dma-coherent; 46 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 47 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; 48 status = "disabled"; 49 }; 50 51 pcie3_rc: pcie@2930000 { 52 compatible = "ti,j784s4-pcie-host"; 53 reg = <0x00 0x02930000 0x00 0x1000>, 54 <0x00 0x02937000 0x00 0x400>, 55 <0x00 0x0e800000 0x00 0x00800000>, 56 <0x44 0x10000000 0x00 0x00001000>; 57 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 58 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 59 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 60 interrupt-names = "link_state"; 61 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 62 device_type = "pci"; 63 max-link-speed = <3>; 64 num-lanes = <2>; 65 power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; 66 clocks = <&k3_clks 335 0>; 67 clock-names = "fck"; 68 #address-cells = <3>; 69 #size-cells = <2>; 70 bus-range = <0x0 0xff>; 71 vendor-id = <0x104c>; 72 device-id = <0xb012>; 73 msi-map = <0x0 &gic_its 0x30000 0x10000>; 74 dma-coherent; 75 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 76 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; 77 status = "disabled"; 78 }; 79 80 serdes_wiz2: wiz@5020000 { 81 compatible = "ti,j784s4-wiz-10g"; 82 ranges = <0x05020000 0x00 0x05020000 0x10000>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; 86 clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; 87 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 88 assigned-clocks = <&k3_clks 406 6>; 89 assigned-clock-parents = <&k3_clks 406 10>; 90 num-lanes = <4>; 91 #reset-cells = <1>; 92 #clock-cells = <1>; 93 status = "disabled"; 94 95 serdes2: serdes@5020000 { 96 compatible = "ti,j721e-serdes-10g"; 97 reg = <0x05020000 0x010000>; 98 reg-names = "torrent_phy"; 99 resets = <&serdes_wiz2 0>; 100 reset-names = "torrent_reset"; 101 clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 102 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; 103 clock-names = "refclk", "phy_en_refclk"; 104 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 105 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, 106 <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; 107 assigned-clock-parents = <&k3_clks 406 6>, 108 <&k3_clks 406 6>, 109 <&k3_clks 406 6>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 #clock-cells = <1>; 113 status = "disabled"; 114 }; 115 }; 116}; 117 118&scm_conf { 119 pcie2_ctrl: pcie2-ctrl@4078 { 120 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 121 reg = <0x4078 0x4>; 122 }; 123 124 pcie3_ctrl: pcie3-ctrl@407c { 125 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 126 reg = <0x407c 0x4>; 127 }; 128}; 129