1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 msmc_ram: sram@70000000 { 25 compatible = "mmio-sram"; 26 reg = <0x00 0x70000000 0x00 0x800000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x00 0x00 0x70000000 0x800000>; 30 31 atf-sram@0 { 32 reg = <0x00 0x20000>; 33 }; 34 35 tifs-sram@1f0000 { 36 reg = <0x1f0000 0x10000>; 37 }; 38 39 l3cache-sram@200000 { 40 reg = <0x200000 0x200000>; 41 }; 42 }; 43 44 scm_conf: bus@100000 { 45 compatible = "simple-bus"; 46 reg = <0x00 0x00100000 0x00 0x1c000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x1c000>; 50 51 cpsw1_phy_gmii_sel: phy@4034 { 52 compatible = "ti,am654-phy-gmii-sel"; 53 reg = <0x4034 0x4>; 54 #phy-cells = <1>; 55 }; 56 57 cpsw0_phy_gmii_sel: phy@4044 { 58 compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; 59 reg = <0x4044 0x20>; 60 #phy-cells = <1>; 61 ti,qsgmii-main-ports = <7>, <7>; 62 }; 63 64 pcie0_ctrl: pcie0-ctrl@4070 { 65 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 66 reg = <0x4070 0x4>; 67 }; 68 69 pcie1_ctrl: pcie1-ctrl@4074 { 70 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 71 reg = <0x4074 0x4>; 72 }; 73 74 pcie2_ctrl: pcie2-ctrl@4078 { 75 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 76 reg = <0x4078 0x4>; 77 }; 78 79 pcie3_ctrl: pcie3-ctrl@407c { 80 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 81 reg = <0x407c 0x4>; 82 }; 83 84 serdes_ln_ctrl: mux-controller@4080 { 85 compatible = "reg-mux"; 86 reg = <0x00004080 0x30>; 87 #mux-control-cells = <1>; 88 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 89 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ 90 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 91 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ 92 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 93 <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ 94 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 95 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 96 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 97 <J784S4_SERDES0_LANE3_USB>, 98 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 99 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 100 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 101 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 102 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 103 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 104 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 105 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 106 <J784S4_SERDES4_LANE0_EDP_LANE0>, 107 <J784S4_SERDES4_LANE1_EDP_LANE1>, 108 <J784S4_SERDES4_LANE2_EDP_LANE2>, 109 <J784S4_SERDES4_LANE3_EDP_LANE3>; 110 }; 111 112 usb_serdes_mux: mux-controller@4000 { 113 compatible = "reg-mux"; 114 reg = <0x4000 0x4>; 115 #mux-control-cells = <1>; 116 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ 117 }; 118 119 ehrpwm_tbclk: clock-controller@4140 { 120 compatible = "ti,am654-ehrpwm-tbclk"; 121 reg = <0x4140 0x18>; 122 #clock-cells = <1>; 123 }; 124 125 audio_refclk1: clock@82e4 { 126 compatible = "ti,am62-audio-refclk"; 127 reg = <0x82e4 0x4>; 128 clocks = <&k3_clks 157 34>; 129 assigned-clocks = <&k3_clks 157 34>; 130 assigned-clock-parents = <&k3_clks 157 63>; 131 #clock-cells = <0>; 132 }; 133 }; 134 135 main_ehrpwm0: pwm@3000000 { 136 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 137 reg = <0x00 0x3000000 0x00 0x100>; 138 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; 139 clock-names = "tbclk", "fck"; 140 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 141 #pwm-cells = <3>; 142 status = "disabled"; 143 }; 144 145 main_ehrpwm1: pwm@3010000 { 146 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 147 reg = <0x00 0x3010000 0x00 0x100>; 148 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; 149 clock-names = "tbclk", "fck"; 150 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 151 #pwm-cells = <3>; 152 status = "disabled"; 153 }; 154 155 main_ehrpwm2: pwm@3020000 { 156 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 157 reg = <0x00 0x3020000 0x00 0x100>; 158 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; 159 clock-names = "tbclk", "fck"; 160 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 161 #pwm-cells = <3>; 162 status = "disabled"; 163 }; 164 165 main_ehrpwm3: pwm@3030000 { 166 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 167 reg = <0x00 0x3030000 0x00 0x100>; 168 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; 169 clock-names = "tbclk", "fck"; 170 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 171 #pwm-cells = <3>; 172 status = "disabled"; 173 }; 174 175 main_ehrpwm4: pwm@3040000 { 176 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 177 reg = <0x00 0x3040000 0x00 0x100>; 178 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; 179 clock-names = "tbclk", "fck"; 180 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 181 #pwm-cells = <3>; 182 status = "disabled"; 183 }; 184 185 main_ehrpwm5: pwm@3050000 { 186 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 187 reg = <0x00 0x3050000 0x00 0x100>; 188 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; 189 clock-names = "tbclk", "fck"; 190 power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; 191 #pwm-cells = <3>; 192 status = "disabled"; 193 }; 194 195 gic500: interrupt-controller@1800000 { 196 compatible = "arm,gic-v3"; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 #interrupt-cells = <3>; 201 interrupt-controller; 202 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 203 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 204 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 205 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 206 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 207 208 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 209 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 210 211 gic_its: msi-controller@1820000 { 212 compatible = "arm,gic-v3-its"; 213 reg = <0x00 0x01820000 0x00 0x10000>; 214 socionext,synquacer-pre-its = <0x1000000 0x400000>; 215 msi-controller; 216 #msi-cells = <1>; 217 }; 218 }; 219 220 main_gpio_intr: interrupt-controller@a00000 { 221 compatible = "ti,sci-intr"; 222 reg = <0x00 0x00a00000 0x00 0x800>; 223 ti,intr-trigger-type = <1>; 224 interrupt-controller; 225 interrupt-parent = <&gic500>; 226 #interrupt-cells = <1>; 227 ti,sci = <&sms>; 228 ti,sci-dev-id = <10>; 229 ti,interrupt-ranges = <8 392 56>; 230 }; 231 232 main_pmx0: pinctrl@11c000 { 233 compatible = "pinctrl-single"; 234 /* Proxy 0 addressing */ 235 reg = <0x00 0x11c000 0x00 0x120>; 236 #pinctrl-cells = <1>; 237 pinctrl-single,register-width = <32>; 238 pinctrl-single,function-mask = <0xffffffff>; 239 }; 240 241 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 242 main_timerio_input: pinctrl@104200 { 243 compatible = "pinctrl-single"; 244 reg = <0x00 0x104200 0x00 0x50>; 245 #pinctrl-cells = <1>; 246 pinctrl-single,register-width = <32>; 247 pinctrl-single,function-mask = <0x00000007>; 248 }; 249 250 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 251 main_timerio_output: pinctrl@104280 { 252 compatible = "pinctrl-single"; 253 reg = <0x00 0x104280 0x00 0x20>; 254 #pinctrl-cells = <1>; 255 pinctrl-single,register-width = <32>; 256 pinctrl-single,function-mask = <0x0000001f>; 257 }; 258 259 main_crypto: crypto@4e00000 { 260 compatible = "ti,j721e-sa2ul"; 261 reg = <0x00 0x4e00000 0x00 0x1200>; 262 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 263 #address-cells = <2>; 264 #size-cells = <2>; 265 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 266 267 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 268 <&main_udmap 0x4a41>; 269 dma-names = "tx", "rx1", "rx2"; 270 271 rng: rng@4e10000 { 272 compatible = "inside-secure,safexcel-eip76"; 273 reg = <0x00 0x4e10000 0x00 0x7d>; 274 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 275 }; 276 }; 277 278 main_timer0: timer@2400000 { 279 compatible = "ti,am654-timer"; 280 reg = <0x00 0x2400000 0x00 0x400>; 281 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&k3_clks 97 2>; 283 clock-names = "fck"; 284 assigned-clocks = <&k3_clks 97 2>; 285 assigned-clock-parents = <&k3_clks 97 3>; 286 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 287 ti,timer-pwm; 288 }; 289 290 main_timer1: timer@2410000 { 291 compatible = "ti,am654-timer"; 292 reg = <0x00 0x2410000 0x00 0x400>; 293 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&k3_clks 98 2>; 295 clock-names = "fck"; 296 assigned-clocks = <&k3_clks 98 2>; 297 assigned-clock-parents = <&k3_clks 98 3>; 298 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 299 ti,timer-pwm; 300 }; 301 302 main_timer2: timer@2420000 { 303 compatible = "ti,am654-timer"; 304 reg = <0x00 0x2420000 0x00 0x400>; 305 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&k3_clks 99 2>; 307 clock-names = "fck"; 308 assigned-clocks = <&k3_clks 99 2>; 309 assigned-clock-parents = <&k3_clks 99 3>; 310 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 311 ti,timer-pwm; 312 }; 313 314 main_timer3: timer@2430000 { 315 compatible = "ti,am654-timer"; 316 reg = <0x00 0x2430000 0x00 0x400>; 317 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&k3_clks 100 2>; 319 clock-names = "fck"; 320 assigned-clocks = <&k3_clks 100 2>; 321 assigned-clock-parents = <&k3_clks 100 3>; 322 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 323 ti,timer-pwm; 324 }; 325 326 main_timer4: timer@2440000 { 327 compatible = "ti,am654-timer"; 328 reg = <0x00 0x2440000 0x00 0x400>; 329 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&k3_clks 101 2>; 331 clock-names = "fck"; 332 assigned-clocks = <&k3_clks 101 2>; 333 assigned-clock-parents = <&k3_clks 101 3>; 334 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 335 ti,timer-pwm; 336 }; 337 338 main_timer5: timer@2450000 { 339 compatible = "ti,am654-timer"; 340 reg = <0x00 0x2450000 0x00 0x400>; 341 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&k3_clks 102 2>; 343 clock-names = "fck"; 344 assigned-clocks = <&k3_clks 102 2>; 345 assigned-clock-parents = <&k3_clks 102 3>; 346 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 347 ti,timer-pwm; 348 }; 349 350 main_timer6: timer@2460000 { 351 compatible = "ti,am654-timer"; 352 reg = <0x00 0x2460000 0x00 0x400>; 353 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&k3_clks 103 2>; 355 clock-names = "fck"; 356 assigned-clocks = <&k3_clks 103 2>; 357 assigned-clock-parents = <&k3_clks 103 3>; 358 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 359 ti,timer-pwm; 360 }; 361 362 main_timer7: timer@2470000 { 363 compatible = "ti,am654-timer"; 364 reg = <0x00 0x2470000 0x00 0x400>; 365 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&k3_clks 104 2>; 367 clock-names = "fck"; 368 assigned-clocks = <&k3_clks 104 2>; 369 assigned-clock-parents = <&k3_clks 104 3>; 370 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 371 ti,timer-pwm; 372 }; 373 374 main_timer8: timer@2480000 { 375 compatible = "ti,am654-timer"; 376 reg = <0x00 0x2480000 0x00 0x400>; 377 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&k3_clks 105 2>; 379 clock-names = "fck"; 380 assigned-clocks = <&k3_clks 105 2>; 381 assigned-clock-parents = <&k3_clks 105 3>; 382 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 383 ti,timer-pwm; 384 }; 385 386 main_timer9: timer@2490000 { 387 compatible = "ti,am654-timer"; 388 reg = <0x00 0x2490000 0x00 0x400>; 389 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&k3_clks 106 2>; 391 clock-names = "fck"; 392 assigned-clocks = <&k3_clks 106 2>; 393 assigned-clock-parents = <&k3_clks 106 3>; 394 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 395 ti,timer-pwm; 396 }; 397 398 main_timer10: timer@24a0000 { 399 compatible = "ti,am654-timer"; 400 reg = <0x00 0x24a0000 0x00 0x400>; 401 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&k3_clks 107 2>; 403 clock-names = "fck"; 404 assigned-clocks = <&k3_clks 107 2>; 405 assigned-clock-parents = <&k3_clks 107 3>; 406 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 407 ti,timer-pwm; 408 }; 409 410 main_timer11: timer@24b0000 { 411 compatible = "ti,am654-timer"; 412 reg = <0x00 0x24b0000 0x00 0x400>; 413 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&k3_clks 108 2>; 415 clock-names = "fck"; 416 assigned-clocks = <&k3_clks 108 2>; 417 assigned-clock-parents = <&k3_clks 108 3>; 418 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 419 ti,timer-pwm; 420 }; 421 422 main_timer12: timer@24c0000 { 423 compatible = "ti,am654-timer"; 424 reg = <0x00 0x24c0000 0x00 0x400>; 425 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&k3_clks 109 2>; 427 clock-names = "fck"; 428 assigned-clocks = <&k3_clks 109 2>; 429 assigned-clock-parents = <&k3_clks 109 3>; 430 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 431 ti,timer-pwm; 432 }; 433 434 main_timer13: timer@24d0000 { 435 compatible = "ti,am654-timer"; 436 reg = <0x00 0x24d0000 0x00 0x400>; 437 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&k3_clks 110 2>; 439 clock-names = "fck"; 440 assigned-clocks = <&k3_clks 110 2>; 441 assigned-clock-parents = <&k3_clks 110 3>; 442 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 443 ti,timer-pwm; 444 }; 445 446 main_timer14: timer@24e0000 { 447 compatible = "ti,am654-timer"; 448 reg = <0x00 0x24e0000 0x00 0x400>; 449 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&k3_clks 111 2>; 451 clock-names = "fck"; 452 assigned-clocks = <&k3_clks 111 2>; 453 assigned-clock-parents = <&k3_clks 111 3>; 454 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 455 ti,timer-pwm; 456 }; 457 458 main_timer15: timer@24f0000 { 459 compatible = "ti,am654-timer"; 460 reg = <0x00 0x24f0000 0x00 0x400>; 461 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&k3_clks 112 2>; 463 clock-names = "fck"; 464 assigned-clocks = <&k3_clks 112 2>; 465 assigned-clock-parents = <&k3_clks 112 3>; 466 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 467 ti,timer-pwm; 468 }; 469 470 main_timer16: timer@2500000 { 471 compatible = "ti,am654-timer"; 472 reg = <0x00 0x2500000 0x00 0x400>; 473 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&k3_clks 113 2>; 475 clock-names = "fck"; 476 assigned-clocks = <&k3_clks 113 2>; 477 assigned-clock-parents = <&k3_clks 113 3>; 478 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 479 ti,timer-pwm; 480 }; 481 482 main_timer17: timer@2510000 { 483 compatible = "ti,am654-timer"; 484 reg = <0x00 0x2510000 0x00 0x400>; 485 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&k3_clks 114 2>; 487 clock-names = "fck"; 488 assigned-clocks = <&k3_clks 114 2>; 489 assigned-clock-parents = <&k3_clks 114 3>; 490 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 491 ti,timer-pwm; 492 }; 493 494 main_timer18: timer@2520000 { 495 compatible = "ti,am654-timer"; 496 reg = <0x00 0x2520000 0x00 0x400>; 497 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&k3_clks 115 2>; 499 clock-names = "fck"; 500 assigned-clocks = <&k3_clks 115 2>; 501 assigned-clock-parents = <&k3_clks 115 3>; 502 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 503 ti,timer-pwm; 504 }; 505 506 main_timer19: timer@2530000 { 507 compatible = "ti,am654-timer"; 508 reg = <0x00 0x2530000 0x00 0x400>; 509 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&k3_clks 116 2>; 511 clock-names = "fck"; 512 assigned-clocks = <&k3_clks 116 2>; 513 assigned-clock-parents = <&k3_clks 116 3>; 514 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 515 ti,timer-pwm; 516 }; 517 518 main_uart0: serial@2800000 { 519 compatible = "ti,j721e-uart", "ti,am654-uart"; 520 reg = <0x00 0x02800000 0x00 0x200>; 521 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&k3_clks 146 0>; 523 clock-names = "fclk"; 524 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 525 status = "disabled"; 526 }; 527 528 main_uart1: serial@2810000 { 529 compatible = "ti,j721e-uart", "ti,am654-uart"; 530 reg = <0x00 0x02810000 0x00 0x200>; 531 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&k3_clks 388 0>; 533 clock-names = "fclk"; 534 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 535 status = "disabled"; 536 }; 537 538 main_uart2: serial@2820000 { 539 compatible = "ti,j721e-uart", "ti,am654-uart"; 540 reg = <0x00 0x02820000 0x00 0x200>; 541 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&k3_clks 389 0>; 543 clock-names = "fclk"; 544 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 545 status = "disabled"; 546 }; 547 548 main_uart3: serial@2830000 { 549 compatible = "ti,j721e-uart", "ti,am654-uart"; 550 reg = <0x00 0x02830000 0x00 0x200>; 551 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&k3_clks 390 0>; 553 clock-names = "fclk"; 554 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 555 status = "disabled"; 556 }; 557 558 main_uart4: serial@2840000 { 559 compatible = "ti,j721e-uart", "ti,am654-uart"; 560 reg = <0x00 0x02840000 0x00 0x200>; 561 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&k3_clks 391 0>; 563 clock-names = "fclk"; 564 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 565 status = "disabled"; 566 }; 567 568 main_uart5: serial@2850000 { 569 compatible = "ti,j721e-uart", "ti,am654-uart"; 570 reg = <0x00 0x02850000 0x00 0x200>; 571 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&k3_clks 392 0>; 573 clock-names = "fclk"; 574 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 575 status = "disabled"; 576 }; 577 578 main_uart6: serial@2860000 { 579 compatible = "ti,j721e-uart", "ti,am654-uart"; 580 reg = <0x00 0x02860000 0x00 0x200>; 581 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&k3_clks 393 0>; 583 clock-names = "fclk"; 584 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 585 status = "disabled"; 586 }; 587 588 main_uart7: serial@2870000 { 589 compatible = "ti,j721e-uart", "ti,am654-uart"; 590 reg = <0x00 0x02870000 0x00 0x200>; 591 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&k3_clks 394 0>; 593 clock-names = "fclk"; 594 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 595 status = "disabled"; 596 }; 597 598 main_uart8: serial@2880000 { 599 compatible = "ti,j721e-uart", "ti,am654-uart"; 600 reg = <0x00 0x02880000 0x00 0x200>; 601 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&k3_clks 395 0>; 603 clock-names = "fclk"; 604 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 605 status = "disabled"; 606 }; 607 608 main_uart9: serial@2890000 { 609 compatible = "ti,j721e-uart", "ti,am654-uart"; 610 reg = <0x00 0x02890000 0x00 0x200>; 611 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&k3_clks 396 0>; 613 clock-names = "fclk"; 614 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 615 status = "disabled"; 616 }; 617 618 main_gpio0: gpio@600000 { 619 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 620 reg = <0x00 0x00600000 0x00 0x100>; 621 gpio-controller; 622 #gpio-cells = <2>; 623 interrupt-parent = <&main_gpio_intr>; 624 interrupts = <145>, <146>, <147>, <148>, <149>; 625 interrupt-controller; 626 #interrupt-cells = <2>; 627 ti,ngpio = <66>; 628 ti,davinci-gpio-unbanked = <0>; 629 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 630 clocks = <&k3_clks 163 0>; 631 clock-names = "gpio"; 632 status = "disabled"; 633 }; 634 635 main_gpio2: gpio@610000 { 636 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 637 reg = <0x00 0x00610000 0x00 0x100>; 638 gpio-controller; 639 #gpio-cells = <2>; 640 interrupt-parent = <&main_gpio_intr>; 641 interrupts = <154>, <155>, <156>, <157>, <158>; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 ti,ngpio = <66>; 645 ti,davinci-gpio-unbanked = <0>; 646 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 647 clocks = <&k3_clks 164 0>; 648 clock-names = "gpio"; 649 status = "disabled"; 650 }; 651 652 main_gpio4: gpio@620000 { 653 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 654 reg = <0x00 0x00620000 0x00 0x100>; 655 gpio-controller; 656 #gpio-cells = <2>; 657 interrupt-parent = <&main_gpio_intr>; 658 interrupts = <163>, <164>, <165>, <166>, <167>; 659 interrupt-controller; 660 #interrupt-cells = <2>; 661 ti,ngpio = <66>; 662 ti,davinci-gpio-unbanked = <0>; 663 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 664 clocks = <&k3_clks 165 0>; 665 clock-names = "gpio"; 666 status = "disabled"; 667 }; 668 669 main_gpio6: gpio@630000 { 670 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 671 reg = <0x00 0x00630000 0x00 0x100>; 672 gpio-controller; 673 #gpio-cells = <2>; 674 interrupt-parent = <&main_gpio_intr>; 675 interrupts = <172>, <173>, <174>, <175>, <176>; 676 interrupt-controller; 677 #interrupt-cells = <2>; 678 ti,ngpio = <66>; 679 ti,davinci-gpio-unbanked = <0>; 680 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 681 clocks = <&k3_clks 166 0>; 682 clock-names = "gpio"; 683 status = "disabled"; 684 }; 685 686 usbss0: usb@4104000 { 687 bootph-all; 688 compatible = "ti,j721e-usb"; 689 reg = <0x00 0x4104000 0x00 0x100>; 690 dma-coherent; 691 power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; 692 clocks = <&k3_clks 398 21>, <&k3_clks 398 2>; 693 clock-names = "ref", "lpm"; 694 assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */ 695 assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */ 696 #address-cells = <2>; 697 #size-cells = <2>; 698 ranges; 699 700 status = "disabled"; /* Needs lane config */ 701 702 usb0: usb@6000000 { 703 bootph-all; 704 compatible = "cdns,usb3"; 705 reg = <0x00 0x6000000 0x00 0x10000>, 706 <0x00 0x6010000 0x00 0x10000>, 707 <0x00 0x6020000 0x00 0x10000>; 708 reg-names = "otg", "xhci", "dev"; 709 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 710 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 711 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 712 interrupt-names = "host", 713 "peripheral", 714 "otg"; 715 }; 716 }; 717 718 main_i2c0: i2c@2000000 { 719 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 720 reg = <0x00 0x02000000 0x00 0x100>; 721 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&k3_clks 270 2>; 725 clock-names = "fck"; 726 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 727 status = "disabled"; 728 }; 729 730 main_i2c1: i2c@2010000 { 731 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 732 reg = <0x00 0x02010000 0x00 0x100>; 733 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 clocks = <&k3_clks 271 2>; 737 clock-names = "fck"; 738 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 739 status = "disabled"; 740 }; 741 742 main_i2c2: i2c@2020000 { 743 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 744 reg = <0x00 0x02020000 0x00 0x100>; 745 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 clocks = <&k3_clks 272 2>; 749 clock-names = "fck"; 750 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 751 status = "disabled"; 752 }; 753 754 main_i2c3: i2c@2030000 { 755 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 756 reg = <0x00 0x02030000 0x00 0x100>; 757 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 clocks = <&k3_clks 273 2>; 761 clock-names = "fck"; 762 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 763 status = "disabled"; 764 }; 765 766 main_i2c4: i2c@2040000 { 767 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 768 reg = <0x00 0x02040000 0x00 0x100>; 769 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 clocks = <&k3_clks 274 2>; 773 clock-names = "fck"; 774 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 775 status = "disabled"; 776 }; 777 778 main_i2c5: i2c@2050000 { 779 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 780 reg = <0x00 0x02050000 0x00 0x100>; 781 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 clocks = <&k3_clks 275 2>; 785 clock-names = "fck"; 786 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 787 status = "disabled"; 788 }; 789 790 main_i2c6: i2c@2060000 { 791 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 792 reg = <0x00 0x02060000 0x00 0x100>; 793 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 clocks = <&k3_clks 276 2>; 797 clock-names = "fck"; 798 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 799 status = "disabled"; 800 }; 801 802 ti_csi2rx0: ticsi2rx@4500000 { 803 compatible = "ti,j721e-csi2rx-shim"; 804 reg = <0x00 0x04500000 0x00 0x00001000>; 805 ranges; 806 #address-cells = <2>; 807 #size-cells = <2>; 808 dmas = <&main_bcdma_csi 0 0x4940 0>; 809 dma-names = "rx0"; 810 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 811 status = "disabled"; 812 813 cdns_csi2rx0: csi-bridge@4504000 { 814 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 815 reg = <0x00 0x04504000 0x00 0x00001000>; 816 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, 817 <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; 818 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 819 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 820 phys = <&dphy0>; 821 phy-names = "dphy"; 822 823 ports { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 827 csi0_port0: port@0 { 828 reg = <0>; 829 status = "disabled"; 830 }; 831 832 csi0_port1: port@1 { 833 reg = <1>; 834 status = "disabled"; 835 }; 836 837 csi0_port2: port@2 { 838 reg = <2>; 839 status = "disabled"; 840 }; 841 842 csi0_port3: port@3 { 843 reg = <3>; 844 status = "disabled"; 845 }; 846 847 csi0_port4: port@4 { 848 reg = <4>; 849 status = "disabled"; 850 }; 851 }; 852 }; 853 }; 854 855 ti_csi2rx1: ticsi2rx@4510000 { 856 compatible = "ti,j721e-csi2rx-shim"; 857 reg = <0x00 0x04510000 0x00 0x1000>; 858 ranges; 859 #address-cells = <2>; 860 #size-cells = <2>; 861 dmas = <&main_bcdma_csi 0 0x4960 0>; 862 dma-names = "rx0"; 863 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 864 status = "disabled"; 865 866 cdns_csi2rx1: csi-bridge@4514000 { 867 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 868 reg = <0x00 0x04514000 0x00 0x00001000>; 869 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, 870 <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; 871 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 872 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 873 phys = <&dphy1>; 874 phy-names = "dphy"; 875 ports { 876 #address-cells = <1>; 877 #size-cells = <0>; 878 879 csi1_port0: port@0 { 880 reg = <0>; 881 status = "disabled"; 882 }; 883 884 csi1_port1: port@1 { 885 reg = <1>; 886 status = "disabled"; 887 }; 888 889 csi1_port2: port@2 { 890 reg = <2>; 891 status = "disabled"; 892 }; 893 894 csi1_port3: port@3 { 895 reg = <3>; 896 status = "disabled"; 897 }; 898 899 csi1_port4: port@4 { 900 reg = <4>; 901 status = "disabled"; 902 }; 903 }; 904 }; 905 }; 906 907 ti_csi2rx2: ticsi2rx@4520000 { 908 compatible = "ti,j721e-csi2rx-shim"; 909 reg = <0x00 0x04520000 0x00 0x00001000>; 910 ranges; 911 #address-cells = <2>; 912 #size-cells = <2>; 913 dmas = <&main_bcdma_csi 0 0x4980 0>; 914 dma-names = "rx0"; 915 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 916 status = "disabled"; 917 918 cdns_csi2rx2: csi-bridge@4524000 { 919 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 920 reg = <0x00 0x04524000 0x00 0x00001000>; 921 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, 922 <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; 923 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 924 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 925 phys = <&dphy2>; 926 phy-names = "dphy"; 927 928 ports { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 csi2_port0: port@0 { 933 reg = <0>; 934 status = "disabled"; 935 }; 936 937 csi2_port1: port@1 { 938 reg = <1>; 939 status = "disabled"; 940 }; 941 942 csi2_port2: port@2 { 943 reg = <2>; 944 status = "disabled"; 945 }; 946 947 csi2_port3: port@3 { 948 reg = <3>; 949 status = "disabled"; 950 }; 951 952 csi2_port4: port@4 { 953 reg = <4>; 954 status = "disabled"; 955 }; 956 }; 957 }; 958 }; 959 960 dphy0: phy@4580000 { 961 compatible = "cdns,dphy-rx"; 962 reg = <0x00 0x04580000 0x00 0x00001100>; 963 #phy-cells = <0>; 964 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; 965 status = "disabled"; 966 }; 967 968 dphy1: phy@4590000 { 969 compatible = "cdns,dphy-rx"; 970 reg = <0x00 0x04590000 0x00 0x00001100>; 971 #phy-cells = <0>; 972 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; 973 status = "disabled"; 974 }; 975 976 dphy2: phy@45a0000 { 977 compatible = "cdns,dphy-rx"; 978 reg = <0x00 0x045a0000 0x00 0x00001100>; 979 #phy-cells = <0>; 980 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 981 status = "disabled"; 982 }; 983 984 vpu0: video-codec@4210000 { 985 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 986 reg = <0x00 0x4210000 0x00 0x10000>; 987 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&k3_clks 241 2>; 989 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 990 }; 991 992 vpu1: video-codec@4220000 { 993 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 994 reg = <0x00 0x4220000 0x00 0x10000>; 995 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&k3_clks 242 2>; 997 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 998 }; 999 1000 main_sdhci0: mmc@4f80000 { 1001 compatible = "ti,j721e-sdhci-8bit"; 1002 reg = <0x00 0x04f80000 0x00 0x1000>, 1003 <0x00 0x04f88000 0x00 0x400>; 1004 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1005 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 1006 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 1007 clock-names = "clk_ahb", "clk_xin"; 1008 assigned-clocks = <&k3_clks 140 2>; 1009 assigned-clock-parents = <&k3_clks 140 3>; 1010 bus-width = <8>; 1011 ti,otap-del-sel-legacy = <0x0>; 1012 ti,otap-del-sel-mmc-hs = <0x0>; 1013 ti,otap-del-sel-ddr52 = <0x6>; 1014 ti,otap-del-sel-hs200 = <0x8>; 1015 ti,otap-del-sel-hs400 = <0x5>; 1016 ti,itap-del-sel-legacy = <0x10>; 1017 ti,itap-del-sel-mmc-hs = <0xa>; 1018 ti,strobe-sel = <0x77>; 1019 ti,clkbuf-sel = <0x7>; 1020 ti,trm-icp = <0x8>; 1021 mmc-ddr-1_8v; 1022 mmc-hs200-1_8v; 1023 mmc-hs400-1_8v; 1024 dma-coherent; 1025 status = "disabled"; 1026 }; 1027 1028 main_sdhci1: mmc@4fb0000 { 1029 compatible = "ti,j721e-sdhci-4bit"; 1030 reg = <0x00 0x04fb0000 0x00 0x1000>, 1031 <0x00 0x04fb8000 0x00 0x400>; 1032 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1033 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 1034 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 1035 clock-names = "clk_ahb", "clk_xin"; 1036 assigned-clocks = <&k3_clks 141 4>; 1037 assigned-clock-parents = <&k3_clks 141 5>; 1038 bus-width = <4>; 1039 ti,otap-del-sel-legacy = <0x0>; 1040 ti,otap-del-sel-sd-hs = <0x0>; 1041 ti,otap-del-sel-sdr12 = <0xf>; 1042 ti,otap-del-sel-sdr25 = <0xf>; 1043 ti,otap-del-sel-sdr50 = <0xc>; 1044 ti,otap-del-sel-sdr104 = <0x5>; 1045 ti,otap-del-sel-ddr50 = <0xc>; 1046 ti,itap-del-sel-legacy = <0x0>; 1047 ti,itap-del-sel-sd-hs = <0x0>; 1048 ti,itap-del-sel-sdr12 = <0x0>; 1049 ti,itap-del-sel-sdr25 = <0x0>; 1050 ti,itap-del-sel-ddr50 = <0x2>; 1051 ti,clkbuf-sel = <0x7>; 1052 ti,trm-icp = <0x8>; 1053 dma-coherent; 1054 status = "disabled"; 1055 }; 1056 1057 pcie0_rc: pcie@2900000 { 1058 compatible = "ti,j784s4-pcie-host"; 1059 reg = <0x00 0x02900000 0x00 0x1000>, 1060 <0x00 0x02907000 0x00 0x400>, 1061 <0x00 0x0d000000 0x00 0x00800000>, 1062 <0x00 0x10000000 0x00 0x00001000>; 1063 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1064 interrupt-names = "link_state"; 1065 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 1066 device_type = "pci"; 1067 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 1068 max-link-speed = <3>; 1069 num-lanes = <4>; 1070 power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; 1071 clocks = <&k3_clks 332 0>; 1072 clock-names = "fck"; 1073 #address-cells = <3>; 1074 #size-cells = <2>; 1075 bus-range = <0x0 0xff>; 1076 vendor-id = <0x104c>; 1077 device-id = <0xb012>; 1078 msi-map = <0x0 &gic_its 0x0 0x10000>; 1079 dma-coherent; 1080 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 1081 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 1082 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1083 status = "disabled"; 1084 }; 1085 1086 pcie1_rc: pcie@2910000 { 1087 compatible = "ti,j784s4-pcie-host"; 1088 reg = <0x00 0x02910000 0x00 0x1000>, 1089 <0x00 0x02917000 0x00 0x400>, 1090 <0x00 0x0d800000 0x00 0x00800000>, 1091 <0x00 0x18000000 0x00 0x00001000>; 1092 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1093 interrupt-names = "link_state"; 1094 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1095 device_type = "pci"; 1096 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 1097 max-link-speed = <3>; 1098 num-lanes = <4>; 1099 power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; 1100 clocks = <&k3_clks 333 0>; 1101 clock-names = "fck"; 1102 #address-cells = <3>; 1103 #size-cells = <2>; 1104 bus-range = <0x0 0xff>; 1105 vendor-id = <0x104c>; 1106 device-id = <0xb012>; 1107 msi-map = <0x0 &gic_its 0x10000 0x10000>; 1108 dma-coherent; 1109 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1110 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1111 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1112 status = "disabled"; 1113 }; 1114 1115 pcie2_rc: pcie@2920000 { 1116 compatible = "ti,j784s4-pcie-host"; 1117 reg = <0x00 0x02920000 0x00 0x1000>, 1118 <0x00 0x02927000 0x00 0x400>, 1119 <0x00 0x0e000000 0x00 0x00800000>, 1120 <0x44 0x00000000 0x00 0x00001000>; 1121 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1122 interrupt-names = "link_state"; 1123 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 1124 device_type = "pci"; 1125 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; 1126 max-link-speed = <3>; 1127 num-lanes = <2>; 1128 power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; 1129 clocks = <&k3_clks 334 0>; 1130 clock-names = "fck"; 1131 #address-cells = <3>; 1132 #size-cells = <2>; 1133 bus-range = <0x0 0xff>; 1134 vendor-id = <0x104c>; 1135 device-id = <0xb012>; 1136 msi-map = <0x0 &gic_its 0x20000 0x10000>; 1137 dma-coherent; 1138 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 1139 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 1140 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1141 status = "disabled"; 1142 }; 1143 1144 pcie3_rc: pcie@2930000 { 1145 compatible = "ti,j784s4-pcie-host"; 1146 reg = <0x00 0x02930000 0x00 0x1000>, 1147 <0x00 0x02937000 0x00 0x400>, 1148 <0x00 0x0e800000 0x00 0x00800000>, 1149 <0x44 0x10000000 0x00 0x00001000>; 1150 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1151 interrupt-names = "link_state"; 1152 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 1153 device_type = "pci"; 1154 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; 1155 max-link-speed = <3>; 1156 num-lanes = <2>; 1157 power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; 1158 clocks = <&k3_clks 335 0>; 1159 clock-names = "fck"; 1160 #address-cells = <3>; 1161 #size-cells = <2>; 1162 bus-range = <0x0 0xff>; 1163 vendor-id = <0x104c>; 1164 device-id = <0xb012>; 1165 msi-map = <0x0 &gic_its 0x30000 0x10000>; 1166 dma-coherent; 1167 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 1168 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 1169 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1170 status = "disabled"; 1171 }; 1172 1173 serdes_wiz0: wiz@5060000 { 1174 compatible = "ti,j784s4-wiz-10g"; 1175 #address-cells = <1>; 1176 #size-cells = <1>; 1177 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 1178 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 1179 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1180 assigned-clocks = <&k3_clks 404 6>; 1181 assigned-clock-parents = <&k3_clks 404 10>; 1182 num-lanes = <4>; 1183 #reset-cells = <1>; 1184 #clock-cells = <1>; 1185 ranges = <0x5060000 0x00 0x5060000 0x10000>; 1186 status = "disabled"; 1187 1188 serdes0: serdes@5060000 { 1189 compatible = "ti,j721e-serdes-10g"; 1190 reg = <0x05060000 0x010000>; 1191 reg-names = "torrent_phy"; 1192 resets = <&serdes_wiz0 0>; 1193 reset-names = "torrent_reset"; 1194 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1195 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1196 clock-names = "refclk", "phy_en_refclk"; 1197 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1198 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1199 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1200 assigned-clock-parents = <&k3_clks 404 6>, 1201 <&k3_clks 404 6>, 1202 <&k3_clks 404 6>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 #clock-cells = <1>; 1206 status = "disabled"; 1207 }; 1208 }; 1209 1210 serdes_wiz1: wiz@5070000 { 1211 compatible = "ti,j784s4-wiz-10g"; 1212 #address-cells = <1>; 1213 #size-cells = <1>; 1214 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 1215 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 1216 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1217 assigned-clocks = <&k3_clks 405 6>; 1218 assigned-clock-parents = <&k3_clks 405 10>; 1219 num-lanes = <4>; 1220 #reset-cells = <1>; 1221 #clock-cells = <1>; 1222 ranges = <0x05070000 0x00 0x05070000 0x10000>; 1223 status = "disabled"; 1224 1225 serdes1: serdes@5070000 { 1226 compatible = "ti,j721e-serdes-10g"; 1227 reg = <0x05070000 0x010000>; 1228 reg-names = "torrent_phy"; 1229 resets = <&serdes_wiz1 0>; 1230 reset-names = "torrent_reset"; 1231 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1232 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 1233 clock-names = "refclk", "phy_en_refclk"; 1234 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1235 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 1236 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 1237 assigned-clock-parents = <&k3_clks 405 6>, 1238 <&k3_clks 405 6>, 1239 <&k3_clks 405 6>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 #clock-cells = <1>; 1243 status = "disabled"; 1244 }; 1245 }; 1246 1247 serdes_wiz2: wiz@5020000 { 1248 compatible = "ti,j784s4-wiz-10g"; 1249 #address-cells = <1>; 1250 #size-cells = <1>; 1251 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; 1252 clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; 1253 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1254 assigned-clocks = <&k3_clks 406 6>; 1255 assigned-clock-parents = <&k3_clks 406 10>; 1256 num-lanes = <4>; 1257 #reset-cells = <1>; 1258 #clock-cells = <1>; 1259 ranges = <0x05020000 0x00 0x05020000 0x10000>; 1260 status = "disabled"; 1261 1262 serdes2: serdes@5020000 { 1263 compatible = "ti,j721e-serdes-10g"; 1264 reg = <0x05020000 0x010000>; 1265 reg-names = "torrent_phy"; 1266 resets = <&serdes_wiz2 0>; 1267 reset-names = "torrent_reset"; 1268 clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 1269 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; 1270 clock-names = "refclk", "phy_en_refclk"; 1271 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 1272 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, 1273 <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; 1274 assigned-clock-parents = <&k3_clks 406 6>, 1275 <&k3_clks 406 6>, 1276 <&k3_clks 406 6>; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 #clock-cells = <1>; 1280 status = "disabled"; 1281 }; 1282 }; 1283 1284 serdes_wiz4: wiz@5050000 { 1285 compatible = "ti,j784s4-wiz-10g"; 1286 #address-cells = <1>; 1287 #size-cells = <1>; 1288 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 1289 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 1290 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1291 assigned-clocks = <&k3_clks 407 6>; 1292 assigned-clock-parents = <&k3_clks 407 10>; 1293 num-lanes = <4>; 1294 #reset-cells = <1>; 1295 #clock-cells = <1>; 1296 ranges = <0x05050000 0x00 0x05050000 0x10000>, 1297 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 1298 status = "disabled"; 1299 1300 serdes4: serdes@5050000 { 1301 /* 1302 * Note: we also map DPTX PHY registers as the Torrent 1303 * needs to manage those. 1304 */ 1305 compatible = "ti,j721e-serdes-10g"; 1306 reg = <0x05050000 0x010000>, 1307 <0x0a030a00 0x40>; /* DPTX PHY */ 1308 reg-names = "torrent_phy"; 1309 resets = <&serdes_wiz4 0>; 1310 reset-names = "torrent_reset"; 1311 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1312 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 1313 clock-names = "refclk", "phy_en_refclk"; 1314 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1315 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1316 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1317 assigned-clock-parents = <&k3_clks 407 6>, 1318 <&k3_clks 407 6>, 1319 <&k3_clks 407 6>; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 #clock-cells = <1>; 1323 status = "disabled"; 1324 }; 1325 }; 1326 1327 main_navss: bus@30000000 { 1328 bootph-all; 1329 compatible = "simple-bus"; 1330 #address-cells = <2>; 1331 #size-cells = <2>; 1332 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 1333 ti,sci-dev-id = <280>; 1334 dma-coherent; 1335 dma-ranges; 1336 1337 main_navss_intr: interrupt-controller@310e0000 { 1338 compatible = "ti,sci-intr"; 1339 reg = <0x00 0x310e0000 0x00 0x4000>; 1340 ti,intr-trigger-type = <4>; 1341 interrupt-controller; 1342 interrupt-parent = <&gic500>; 1343 #interrupt-cells = <1>; 1344 ti,sci = <&sms>; 1345 ti,sci-dev-id = <283>; 1346 ti,interrupt-ranges = <0 64 64>, 1347 <64 448 64>, 1348 <128 672 64>; 1349 }; 1350 1351 main_udmass_inta: msi-controller@33d00000 { 1352 compatible = "ti,sci-inta"; 1353 reg = <0x00 0x33d00000 0x00 0x100000>; 1354 interrupt-controller; 1355 #interrupt-cells = <0>; 1356 interrupt-parent = <&main_navss_intr>; 1357 msi-controller; 1358 ti,sci = <&sms>; 1359 ti,sci-dev-id = <321>; 1360 ti,interrupt-ranges = <0 0 256>; 1361 ti,unmapped-event-sources = <&main_bcdma_csi>; 1362 }; 1363 1364 secure_proxy_main: mailbox@32c00000 { 1365 bootph-all; 1366 compatible = "ti,am654-secure-proxy"; 1367 #mbox-cells = <1>; 1368 reg-names = "target_data", "rt", "scfg"; 1369 reg = <0x00 0x32c00000 0x00 0x100000>, 1370 <0x00 0x32400000 0x00 0x100000>, 1371 <0x00 0x32800000 0x00 0x100000>; 1372 interrupt-names = "rx_011"; 1373 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1374 }; 1375 1376 hwspinlock: hwlock@30e00000 { 1377 compatible = "ti,am654-hwspinlock"; 1378 reg = <0x00 0x30e00000 0x00 0x1000>; 1379 #hwlock-cells = <1>; 1380 }; 1381 1382 mailbox0_cluster0: mailbox@31f80000 { 1383 compatible = "ti,am654-mailbox"; 1384 reg = <0x00 0x31f80000 0x00 0x200>; 1385 #mbox-cells = <1>; 1386 ti,mbox-num-users = <4>; 1387 ti,mbox-num-fifos = <16>; 1388 interrupt-parent = <&main_navss_intr>; 1389 status = "disabled"; 1390 }; 1391 1392 mailbox0_cluster1: mailbox@31f81000 { 1393 compatible = "ti,am654-mailbox"; 1394 reg = <0x00 0x31f81000 0x00 0x200>; 1395 #mbox-cells = <1>; 1396 ti,mbox-num-users = <4>; 1397 ti,mbox-num-fifos = <16>; 1398 interrupt-parent = <&main_navss_intr>; 1399 status = "disabled"; 1400 }; 1401 1402 mailbox0_cluster2: mailbox@31f82000 { 1403 compatible = "ti,am654-mailbox"; 1404 reg = <0x00 0x31f82000 0x00 0x200>; 1405 #mbox-cells = <1>; 1406 ti,mbox-num-users = <4>; 1407 ti,mbox-num-fifos = <16>; 1408 interrupt-parent = <&main_navss_intr>; 1409 status = "disabled"; 1410 }; 1411 1412 mailbox0_cluster3: mailbox@31f83000 { 1413 compatible = "ti,am654-mailbox"; 1414 reg = <0x00 0x31f83000 0x00 0x200>; 1415 #mbox-cells = <1>; 1416 ti,mbox-num-users = <4>; 1417 ti,mbox-num-fifos = <16>; 1418 interrupt-parent = <&main_navss_intr>; 1419 status = "disabled"; 1420 }; 1421 1422 mailbox0_cluster4: mailbox@31f84000 { 1423 compatible = "ti,am654-mailbox"; 1424 reg = <0x00 0x31f84000 0x00 0x200>; 1425 #mbox-cells = <1>; 1426 ti,mbox-num-users = <4>; 1427 ti,mbox-num-fifos = <16>; 1428 interrupt-parent = <&main_navss_intr>; 1429 status = "disabled"; 1430 }; 1431 1432 mailbox0_cluster5: mailbox@31f85000 { 1433 compatible = "ti,am654-mailbox"; 1434 reg = <0x00 0x31f85000 0x00 0x200>; 1435 #mbox-cells = <1>; 1436 ti,mbox-num-users = <4>; 1437 ti,mbox-num-fifos = <16>; 1438 interrupt-parent = <&main_navss_intr>; 1439 status = "disabled"; 1440 }; 1441 1442 mailbox0_cluster6: mailbox@31f86000 { 1443 compatible = "ti,am654-mailbox"; 1444 reg = <0x00 0x31f86000 0x00 0x200>; 1445 #mbox-cells = <1>; 1446 ti,mbox-num-users = <4>; 1447 ti,mbox-num-fifos = <16>; 1448 interrupt-parent = <&main_navss_intr>; 1449 status = "disabled"; 1450 }; 1451 1452 mailbox0_cluster7: mailbox@31f87000 { 1453 compatible = "ti,am654-mailbox"; 1454 reg = <0x00 0x31f87000 0x00 0x200>; 1455 #mbox-cells = <1>; 1456 ti,mbox-num-users = <4>; 1457 ti,mbox-num-fifos = <16>; 1458 interrupt-parent = <&main_navss_intr>; 1459 status = "disabled"; 1460 }; 1461 1462 mailbox0_cluster8: mailbox@31f88000 { 1463 compatible = "ti,am654-mailbox"; 1464 reg = <0x00 0x31f88000 0x00 0x200>; 1465 #mbox-cells = <1>; 1466 ti,mbox-num-users = <4>; 1467 ti,mbox-num-fifos = <16>; 1468 interrupt-parent = <&main_navss_intr>; 1469 status = "disabled"; 1470 }; 1471 1472 mailbox0_cluster9: mailbox@31f89000 { 1473 compatible = "ti,am654-mailbox"; 1474 reg = <0x00 0x31f89000 0x00 0x200>; 1475 #mbox-cells = <1>; 1476 ti,mbox-num-users = <4>; 1477 ti,mbox-num-fifos = <16>; 1478 interrupt-parent = <&main_navss_intr>; 1479 status = "disabled"; 1480 }; 1481 1482 mailbox0_cluster10: mailbox@31f8a000 { 1483 compatible = "ti,am654-mailbox"; 1484 reg = <0x00 0x31f8a000 0x00 0x200>; 1485 #mbox-cells = <1>; 1486 ti,mbox-num-users = <4>; 1487 ti,mbox-num-fifos = <16>; 1488 interrupt-parent = <&main_navss_intr>; 1489 status = "disabled"; 1490 }; 1491 1492 mailbox0_cluster11: mailbox@31f8b000 { 1493 compatible = "ti,am654-mailbox"; 1494 reg = <0x00 0x31f8b000 0x00 0x200>; 1495 #mbox-cells = <1>; 1496 ti,mbox-num-users = <4>; 1497 ti,mbox-num-fifos = <16>; 1498 interrupt-parent = <&main_navss_intr>; 1499 status = "disabled"; 1500 }; 1501 1502 mailbox1_cluster0: mailbox@31f90000 { 1503 compatible = "ti,am654-mailbox"; 1504 reg = <0x00 0x31f90000 0x00 0x200>; 1505 #mbox-cells = <1>; 1506 ti,mbox-num-users = <4>; 1507 ti,mbox-num-fifos = <16>; 1508 interrupt-parent = <&main_navss_intr>; 1509 status = "disabled"; 1510 }; 1511 1512 mailbox1_cluster1: mailbox@31f91000 { 1513 compatible = "ti,am654-mailbox"; 1514 reg = <0x00 0x31f91000 0x00 0x200>; 1515 #mbox-cells = <1>; 1516 ti,mbox-num-users = <4>; 1517 ti,mbox-num-fifos = <16>; 1518 interrupt-parent = <&main_navss_intr>; 1519 status = "disabled"; 1520 }; 1521 1522 mailbox1_cluster2: mailbox@31f92000 { 1523 compatible = "ti,am654-mailbox"; 1524 reg = <0x00 0x31f92000 0x00 0x200>; 1525 #mbox-cells = <1>; 1526 ti,mbox-num-users = <4>; 1527 ti,mbox-num-fifos = <16>; 1528 interrupt-parent = <&main_navss_intr>; 1529 status = "disabled"; 1530 }; 1531 1532 mailbox1_cluster3: mailbox@31f93000 { 1533 compatible = "ti,am654-mailbox"; 1534 reg = <0x00 0x31f93000 0x00 0x200>; 1535 #mbox-cells = <1>; 1536 ti,mbox-num-users = <4>; 1537 ti,mbox-num-fifos = <16>; 1538 interrupt-parent = <&main_navss_intr>; 1539 status = "disabled"; 1540 }; 1541 1542 mailbox1_cluster4: mailbox@31f94000 { 1543 compatible = "ti,am654-mailbox"; 1544 reg = <0x00 0x31f94000 0x00 0x200>; 1545 #mbox-cells = <1>; 1546 ti,mbox-num-users = <4>; 1547 ti,mbox-num-fifos = <16>; 1548 interrupt-parent = <&main_navss_intr>; 1549 status = "disabled"; 1550 }; 1551 1552 mailbox1_cluster5: mailbox@31f95000 { 1553 compatible = "ti,am654-mailbox"; 1554 reg = <0x00 0x31f95000 0x00 0x200>; 1555 #mbox-cells = <1>; 1556 ti,mbox-num-users = <4>; 1557 ti,mbox-num-fifos = <16>; 1558 interrupt-parent = <&main_navss_intr>; 1559 status = "disabled"; 1560 }; 1561 1562 mailbox1_cluster6: mailbox@31f96000 { 1563 compatible = "ti,am654-mailbox"; 1564 reg = <0x00 0x31f96000 0x00 0x200>; 1565 #mbox-cells = <1>; 1566 ti,mbox-num-users = <4>; 1567 ti,mbox-num-fifos = <16>; 1568 interrupt-parent = <&main_navss_intr>; 1569 status = "disabled"; 1570 }; 1571 1572 mailbox1_cluster7: mailbox@31f97000 { 1573 compatible = "ti,am654-mailbox"; 1574 reg = <0x00 0x31f97000 0x00 0x200>; 1575 #mbox-cells = <1>; 1576 ti,mbox-num-users = <4>; 1577 ti,mbox-num-fifos = <16>; 1578 interrupt-parent = <&main_navss_intr>; 1579 status = "disabled"; 1580 }; 1581 1582 mailbox1_cluster8: mailbox@31f98000 { 1583 compatible = "ti,am654-mailbox"; 1584 reg = <0x00 0x31f98000 0x00 0x200>; 1585 #mbox-cells = <1>; 1586 ti,mbox-num-users = <4>; 1587 ti,mbox-num-fifos = <16>; 1588 interrupt-parent = <&main_navss_intr>; 1589 status = "disabled"; 1590 }; 1591 1592 mailbox1_cluster9: mailbox@31f99000 { 1593 compatible = "ti,am654-mailbox"; 1594 reg = <0x00 0x31f99000 0x00 0x200>; 1595 #mbox-cells = <1>; 1596 ti,mbox-num-users = <4>; 1597 ti,mbox-num-fifos = <16>; 1598 interrupt-parent = <&main_navss_intr>; 1599 status = "disabled"; 1600 }; 1601 1602 mailbox1_cluster10: mailbox@31f9a000 { 1603 compatible = "ti,am654-mailbox"; 1604 reg = <0x00 0x31f9a000 0x00 0x200>; 1605 #mbox-cells = <1>; 1606 ti,mbox-num-users = <4>; 1607 ti,mbox-num-fifos = <16>; 1608 interrupt-parent = <&main_navss_intr>; 1609 status = "disabled"; 1610 }; 1611 1612 mailbox1_cluster11: mailbox@31f9b000 { 1613 compatible = "ti,am654-mailbox"; 1614 reg = <0x00 0x31f9b000 0x00 0x200>; 1615 #mbox-cells = <1>; 1616 ti,mbox-num-users = <4>; 1617 ti,mbox-num-fifos = <16>; 1618 interrupt-parent = <&main_navss_intr>; 1619 status = "disabled"; 1620 }; 1621 1622 main_ringacc: ringacc@3c000000 { 1623 compatible = "ti,am654-navss-ringacc"; 1624 reg = <0x00 0x3c000000 0x00 0x400000>, 1625 <0x00 0x38000000 0x00 0x400000>, 1626 <0x00 0x31120000 0x00 0x100>, 1627 <0x00 0x33000000 0x00 0x40000>, 1628 <0x00 0x31080000 0x00 0x40000>; 1629 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1630 ti,num-rings = <1024>; 1631 ti,sci-rm-range-gp-rings = <0x1>; 1632 ti,sci = <&sms>; 1633 ti,sci-dev-id = <315>; 1634 msi-parent = <&main_udmass_inta>; 1635 }; 1636 1637 main_udmap: dma-controller@31150000 { 1638 compatible = "ti,j721e-navss-main-udmap"; 1639 reg = <0x00 0x31150000 0x00 0x100>, 1640 <0x00 0x34000000 0x00 0x80000>, 1641 <0x00 0x35000000 0x00 0x200000>, 1642 <0x00 0x30b00000 0x00 0x20000>, 1643 <0x00 0x30c00000 0x00 0x8000>, 1644 <0x00 0x30d00000 0x00 0x4000>; 1645 reg-names = "gcfg", "rchanrt", "tchanrt", 1646 "tchan", "rchan", "rflow"; 1647 msi-parent = <&main_udmass_inta>; 1648 #dma-cells = <1>; 1649 1650 ti,sci = <&sms>; 1651 ti,sci-dev-id = <319>; 1652 ti,ringacc = <&main_ringacc>; 1653 1654 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1655 <0x0f>, /* TX_HCHAN */ 1656 <0x10>; /* TX_UHCHAN */ 1657 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1658 <0x0b>, /* RX_HCHAN */ 1659 <0x0c>; /* RX_UHCHAN */ 1660 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1661 }; 1662 1663 main_bcdma_csi: dma-controller@311a0000 { 1664 compatible = "ti,j721s2-dmss-bcdma-csi"; 1665 reg = <0x00 0x311a0000 0x00 0x100>, 1666 <0x00 0x35d00000 0x00 0x20000>, 1667 <0x00 0x35c00000 0x00 0x10000>, 1668 <0x00 0x35e00000 0x00 0x80000>; 1669 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1670 msi-parent = <&main_udmass_inta>; 1671 #dma-cells = <3>; 1672 ti,sci = <&sms>; 1673 ti,sci-dev-id = <281>; 1674 ti,sci-rm-range-rchan = <0x21>; 1675 ti,sci-rm-range-tchan = <0x22>; 1676 }; 1677 1678 cpts@310d0000 { 1679 compatible = "ti,j721e-cpts"; 1680 reg = <0x00 0x310d0000 0x00 0x400>; 1681 reg-names = "cpts"; 1682 clocks = <&k3_clks 282 0>; 1683 clock-names = "cpts"; 1684 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1685 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1686 interrupts-extended = <&main_navss_intr 391>; 1687 interrupt-names = "cpts"; 1688 ti,cpts-periodic-outputs = <6>; 1689 ti,cpts-ext-ts-inputs = <8>; 1690 }; 1691 }; 1692 1693 main_cpsw0: ethernet@c000000 { 1694 compatible = "ti,j784s4-cpswxg-nuss"; 1695 reg = <0x00 0xc000000 0x00 0x200000>; 1696 reg-names = "cpsw_nuss"; 1697 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 1698 #address-cells = <2>; 1699 #size-cells = <2>; 1700 dma-coherent; 1701 clocks = <&k3_clks 64 0>; 1702 clock-names = "fck"; 1703 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1704 1705 dmas = <&main_udmap 0xca00>, 1706 <&main_udmap 0xca01>, 1707 <&main_udmap 0xca02>, 1708 <&main_udmap 0xca03>, 1709 <&main_udmap 0xca04>, 1710 <&main_udmap 0xca05>, 1711 <&main_udmap 0xca06>, 1712 <&main_udmap 0xca07>, 1713 <&main_udmap 0x4a00>; 1714 dma-names = "tx0", "tx1", "tx2", "tx3", 1715 "tx4", "tx5", "tx6", "tx7", 1716 "rx"; 1717 1718 status = "disabled"; 1719 1720 ethernet-ports { 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 main_cpsw0_port1: port@1 { 1725 reg = <1>; 1726 label = "port1"; 1727 ti,mac-only; 1728 status = "disabled"; 1729 }; 1730 1731 main_cpsw0_port2: port@2 { 1732 reg = <2>; 1733 label = "port2"; 1734 ti,mac-only; 1735 status = "disabled"; 1736 }; 1737 1738 main_cpsw0_port3: port@3 { 1739 reg = <3>; 1740 label = "port3"; 1741 ti,mac-only; 1742 status = "disabled"; 1743 }; 1744 1745 main_cpsw0_port4: port@4 { 1746 reg = <4>; 1747 label = "port4"; 1748 ti,mac-only; 1749 status = "disabled"; 1750 }; 1751 1752 main_cpsw0_port5: port@5 { 1753 reg = <5>; 1754 label = "port5"; 1755 ti,mac-only; 1756 status = "disabled"; 1757 }; 1758 1759 main_cpsw0_port6: port@6 { 1760 reg = <6>; 1761 label = "port6"; 1762 ti,mac-only; 1763 status = "disabled"; 1764 }; 1765 1766 main_cpsw0_port7: port@7 { 1767 reg = <7>; 1768 label = "port7"; 1769 ti,mac-only; 1770 status = "disabled"; 1771 }; 1772 1773 main_cpsw0_port8: port@8 { 1774 reg = <8>; 1775 label = "port8"; 1776 ti,mac-only; 1777 status = "disabled"; 1778 }; 1779 }; 1780 1781 main_cpsw0_mdio: mdio@f00 { 1782 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1783 reg = <0x00 0xf00 0x00 0x100>; 1784 #address-cells = <1>; 1785 #size-cells = <0>; 1786 clocks = <&k3_clks 64 0>; 1787 clock-names = "fck"; 1788 bus_freq = <1000000>; 1789 status = "disabled"; 1790 }; 1791 1792 cpts@3d000 { 1793 compatible = "ti,am65-cpts"; 1794 reg = <0x00 0x3d000 0x00 0x400>; 1795 clocks = <&k3_clks 64 3>; 1796 clock-names = "cpts"; 1797 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1798 interrupt-names = "cpts"; 1799 ti,cpts-ext-ts-inputs = <4>; 1800 ti,cpts-periodic-outputs = <2>; 1801 }; 1802 }; 1803 1804 main_cpsw1: ethernet@c200000 { 1805 compatible = "ti,j721e-cpsw-nuss"; 1806 reg = <0x00 0xc200000 0x00 0x200000>; 1807 reg-names = "cpsw_nuss"; 1808 ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; 1809 #address-cells = <2>; 1810 #size-cells = <2>; 1811 dma-coherent; 1812 clocks = <&k3_clks 62 0>; 1813 clock-names = "fck"; 1814 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1815 1816 dmas = <&main_udmap 0xc640>, 1817 <&main_udmap 0xc641>, 1818 <&main_udmap 0xc642>, 1819 <&main_udmap 0xc643>, 1820 <&main_udmap 0xc644>, 1821 <&main_udmap 0xc645>, 1822 <&main_udmap 0xc646>, 1823 <&main_udmap 0xc647>, 1824 <&main_udmap 0x4640>; 1825 dma-names = "tx0", "tx1", "tx2", "tx3", 1826 "tx4", "tx5", "tx6", "tx7", 1827 "rx"; 1828 1829 status = "disabled"; 1830 1831 ethernet-ports { 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 1835 main_cpsw1_port1: port@1 { 1836 reg = <1>; 1837 label = "port1"; 1838 phys = <&cpsw1_phy_gmii_sel 1>; 1839 ti,mac-only; 1840 status = "disabled"; 1841 }; 1842 }; 1843 1844 main_cpsw1_mdio: mdio@f00 { 1845 compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; 1846 reg = <0x00 0xf00 0x00 0x100>; 1847 #address-cells = <1>; 1848 #size-cells = <0>; 1849 clocks = <&k3_clks 62 0>; 1850 clock-names = "fck"; 1851 bus_freq = <1000000>; 1852 status = "disabled"; 1853 }; 1854 1855 cpts@3d000 { 1856 compatible = "ti,am65-cpts"; 1857 reg = <0x00 0x3d000 0x00 0x400>; 1858 clocks = <&k3_clks 62 3>; 1859 clock-names = "cpts"; 1860 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1861 interrupt-names = "cpts"; 1862 ti,cpts-ext-ts-inputs = <4>; 1863 ti,cpts-periodic-outputs = <2>; 1864 }; 1865 }; 1866 1867 main_mcan0: can@2701000 { 1868 compatible = "bosch,m_can"; 1869 reg = <0x00 0x02701000 0x00 0x200>, 1870 <0x00 0x02708000 0x00 0x8000>; 1871 reg-names = "m_can", "message_ram"; 1872 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1873 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1874 clock-names = "hclk", "cclk"; 1875 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1877 interrupt-names = "int0", "int1"; 1878 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1879 status = "disabled"; 1880 }; 1881 1882 main_mcan1: can@2711000 { 1883 compatible = "bosch,m_can"; 1884 reg = <0x00 0x02711000 0x00 0x200>, 1885 <0x00 0x02718000 0x00 0x8000>; 1886 reg-names = "m_can", "message_ram"; 1887 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1888 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1889 clock-names = "hclk", "cclk"; 1890 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1892 interrupt-names = "int0", "int1"; 1893 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1894 status = "disabled"; 1895 }; 1896 1897 main_mcan2: can@2721000 { 1898 compatible = "bosch,m_can"; 1899 reg = <0x00 0x02721000 0x00 0x200>, 1900 <0x00 0x02728000 0x00 0x8000>; 1901 reg-names = "m_can", "message_ram"; 1902 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1903 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1904 clock-names = "hclk", "cclk"; 1905 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1907 interrupt-names = "int0", "int1"; 1908 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1909 status = "disabled"; 1910 }; 1911 1912 main_mcan3: can@2731000 { 1913 compatible = "bosch,m_can"; 1914 reg = <0x00 0x02731000 0x00 0x200>, 1915 <0x00 0x02738000 0x00 0x8000>; 1916 reg-names = "m_can", "message_ram"; 1917 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1918 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1919 clock-names = "hclk", "cclk"; 1920 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1922 interrupt-names = "int0", "int1"; 1923 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1924 status = "disabled"; 1925 }; 1926 1927 main_mcan4: can@2741000 { 1928 compatible = "bosch,m_can"; 1929 reg = <0x00 0x02741000 0x00 0x200>, 1930 <0x00 0x02748000 0x00 0x8000>; 1931 reg-names = "m_can", "message_ram"; 1932 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1933 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1934 clock-names = "hclk", "cclk"; 1935 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1937 interrupt-names = "int0", "int1"; 1938 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1939 status = "disabled"; 1940 }; 1941 1942 main_mcan5: can@2751000 { 1943 compatible = "bosch,m_can"; 1944 reg = <0x00 0x02751000 0x00 0x200>, 1945 <0x00 0x02758000 0x00 0x8000>; 1946 reg-names = "m_can", "message_ram"; 1947 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1948 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1949 clock-names = "hclk", "cclk"; 1950 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1952 interrupt-names = "int0", "int1"; 1953 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1954 status = "disabled"; 1955 }; 1956 1957 main_mcan6: can@2761000 { 1958 compatible = "bosch,m_can"; 1959 reg = <0x00 0x02761000 0x00 0x200>, 1960 <0x00 0x02768000 0x00 0x8000>; 1961 reg-names = "m_can", "message_ram"; 1962 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1963 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1964 clock-names = "hclk", "cclk"; 1965 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1967 interrupt-names = "int0", "int1"; 1968 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1969 status = "disabled"; 1970 }; 1971 1972 main_mcan7: can@2771000 { 1973 compatible = "bosch,m_can"; 1974 reg = <0x00 0x02771000 0x00 0x200>, 1975 <0x00 0x02778000 0x00 0x8000>; 1976 reg-names = "m_can", "message_ram"; 1977 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1978 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1979 clock-names = "hclk", "cclk"; 1980 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1982 interrupt-names = "int0", "int1"; 1983 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1984 status = "disabled"; 1985 }; 1986 1987 main_mcan8: can@2781000 { 1988 compatible = "bosch,m_can"; 1989 reg = <0x00 0x02781000 0x00 0x200>, 1990 <0x00 0x02788000 0x00 0x8000>; 1991 reg-names = "m_can", "message_ram"; 1992 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1993 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1994 clock-names = "hclk", "cclk"; 1995 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1997 interrupt-names = "int0", "int1"; 1998 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1999 status = "disabled"; 2000 }; 2001 2002 main_mcan9: can@2791000 { 2003 compatible = "bosch,m_can"; 2004 reg = <0x00 0x02791000 0x00 0x200>, 2005 <0x00 0x02798000 0x00 0x8000>; 2006 reg-names = "m_can", "message_ram"; 2007 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 2008 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 2009 clock-names = "hclk", "cclk"; 2010 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2012 interrupt-names = "int0", "int1"; 2013 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2014 status = "disabled"; 2015 }; 2016 2017 main_mcan10: can@27a1000 { 2018 compatible = "bosch,m_can"; 2019 reg = <0x00 0x027a1000 0x00 0x200>, 2020 <0x00 0x027a8000 0x00 0x8000>; 2021 reg-names = "m_can", "message_ram"; 2022 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 2023 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 2024 clock-names = "hclk", "cclk"; 2025 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2027 interrupt-names = "int0", "int1"; 2028 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2029 status = "disabled"; 2030 }; 2031 2032 main_mcan11: can@27b1000 { 2033 compatible = "bosch,m_can"; 2034 reg = <0x00 0x027b1000 0x00 0x200>, 2035 <0x00 0x027b8000 0x00 0x8000>; 2036 reg-names = "m_can", "message_ram"; 2037 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 2038 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 2039 clock-names = "hclk", "cclk"; 2040 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2042 interrupt-names = "int0", "int1"; 2043 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2044 status = "disabled"; 2045 }; 2046 2047 main_mcan12: can@27c1000 { 2048 compatible = "bosch,m_can"; 2049 reg = <0x00 0x027c1000 0x00 0x200>, 2050 <0x00 0x027c8000 0x00 0x8000>; 2051 reg-names = "m_can", "message_ram"; 2052 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 2053 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 2054 clock-names = "hclk", "cclk"; 2055 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2057 interrupt-names = "int0", "int1"; 2058 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2059 status = "disabled"; 2060 }; 2061 2062 main_mcan13: can@27d1000 { 2063 compatible = "bosch,m_can"; 2064 reg = <0x00 0x027d1000 0x00 0x200>, 2065 <0x00 0x027d8000 0x00 0x8000>; 2066 reg-names = "m_can", "message_ram"; 2067 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 2068 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 2069 clock-names = "hclk", "cclk"; 2070 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2072 interrupt-names = "int0", "int1"; 2073 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2074 status = "disabled"; 2075 }; 2076 2077 main_mcan14: can@2681000 { 2078 compatible = "bosch,m_can"; 2079 reg = <0x00 0x02681000 0x00 0x200>, 2080 <0x00 0x02688000 0x00 0x8000>; 2081 reg-names = "m_can", "message_ram"; 2082 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 2083 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 2084 clock-names = "hclk", "cclk"; 2085 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 2087 interrupt-names = "int0", "int1"; 2088 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2089 status = "disabled"; 2090 }; 2091 2092 main_mcan15: can@2691000 { 2093 compatible = "bosch,m_can"; 2094 reg = <0x00 0x02691000 0x00 0x200>, 2095 <0x00 0x02698000 0x00 0x8000>; 2096 reg-names = "m_can", "message_ram"; 2097 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 2098 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 2099 clock-names = "hclk", "cclk"; 2100 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 2102 interrupt-names = "int0", "int1"; 2103 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2104 status = "disabled"; 2105 }; 2106 2107 main_mcan16: can@26a1000 { 2108 compatible = "bosch,m_can"; 2109 reg = <0x00 0x026a1000 0x00 0x200>, 2110 <0x00 0x026a8000 0x00 0x8000>; 2111 reg-names = "m_can", "message_ram"; 2112 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 2113 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 2114 clock-names = "hclk", "cclk"; 2115 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2117 interrupt-names = "int0", "int1"; 2118 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2119 status = "disabled"; 2120 }; 2121 2122 main_mcan17: can@26b1000 { 2123 compatible = "bosch,m_can"; 2124 reg = <0x00 0x026b1000 0x00 0x200>, 2125 <0x00 0x026b8000 0x00 0x8000>; 2126 reg-names = "m_can", "message_ram"; 2127 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 2128 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 2129 clock-names = "hclk", "cclk"; 2130 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 2132 interrupt-names = "int0", "int1"; 2133 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2134 status = "disabled"; 2135 }; 2136 2137 main_spi0: spi@2100000 { 2138 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2139 reg = <0x00 0x02100000 0x00 0x400>; 2140 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 2144 clocks = <&k3_clks 376 1>; 2145 status = "disabled"; 2146 }; 2147 2148 main_spi1: spi@2110000 { 2149 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2150 reg = <0x00 0x02110000 0x00 0x400>; 2151 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 2155 clocks = <&k3_clks 377 1>; 2156 status = "disabled"; 2157 }; 2158 2159 main_spi2: spi@2120000 { 2160 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2161 reg = <0x00 0x02120000 0x00 0x400>; 2162 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 2166 clocks = <&k3_clks 378 1>; 2167 status = "disabled"; 2168 }; 2169 2170 main_spi3: spi@2130000 { 2171 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2172 reg = <0x00 0x02130000 0x00 0x400>; 2173 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2174 #address-cells = <1>; 2175 #size-cells = <0>; 2176 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 2177 clocks = <&k3_clks 379 1>; 2178 status = "disabled"; 2179 }; 2180 2181 main_spi4: spi@2140000 { 2182 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2183 reg = <0x00 0x02140000 0x00 0x400>; 2184 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2185 #address-cells = <1>; 2186 #size-cells = <0>; 2187 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 2188 clocks = <&k3_clks 380 1>; 2189 status = "disabled"; 2190 }; 2191 2192 main_spi5: spi@2150000 { 2193 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2194 reg = <0x00 0x02150000 0x00 0x400>; 2195 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2196 #address-cells = <1>; 2197 #size-cells = <0>; 2198 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 2199 clocks = <&k3_clks 381 1>; 2200 status = "disabled"; 2201 }; 2202 2203 main_spi6: spi@2160000 { 2204 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2205 reg = <0x00 0x02160000 0x00 0x400>; 2206 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 2210 clocks = <&k3_clks 382 1>; 2211 status = "disabled"; 2212 }; 2213 2214 main_spi7: spi@2170000 { 2215 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2216 reg = <0x00 0x02170000 0x00 0x400>; 2217 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 2221 clocks = <&k3_clks 383 1>; 2222 status = "disabled"; 2223 }; 2224 2225 ufs_wrapper: ufs-wrapper@4e80000 { 2226 compatible = "ti,j721e-ufs"; 2227 reg = <0x00 0x4e80000 0x00 0x100>; 2228 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 2229 clocks = <&k3_clks 387 3>; 2230 assigned-clocks = <&k3_clks 387 3>; 2231 assigned-clock-parents = <&k3_clks 387 6>; 2232 ranges; 2233 #address-cells = <2>; 2234 #size-cells = <2>; 2235 status = "disabled"; 2236 2237 ufs@4e84000 { 2238 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 2239 reg = <0x00 0x4e84000 0x00 0x10000>; 2240 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2241 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 2242 <19200000 19200000>; 2243 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 2244 clock-names = "core_clk", "phy_clk", "ref_clk"; 2245 dma-coherent; 2246 }; 2247 }; 2248 2249 main_r5fss0: r5fss@5c00000 { 2250 compatible = "ti,j721s2-r5fss"; 2251 ti,cluster-mode = <1>; 2252 #address-cells = <1>; 2253 #size-cells = <1>; 2254 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2255 <0x5d00000 0x00 0x5d00000 0x20000>; 2256 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 2257 2258 main_r5fss0_core0: r5f@5c00000 { 2259 compatible = "ti,j721s2-r5f"; 2260 reg = <0x5c00000 0x00010000>, 2261 <0x5c10000 0x00010000>; 2262 reg-names = "atcm", "btcm"; 2263 ti,sci = <&sms>; 2264 ti,sci-dev-id = <339>; 2265 ti,sci-proc-ids = <0x06 0xff>; 2266 resets = <&k3_reset 339 1>; 2267 firmware-name = "j784s4-main-r5f0_0-fw"; 2268 ti,atcm-enable = <1>; 2269 ti,btcm-enable = <1>; 2270 ti,loczrama = <1>; 2271 }; 2272 2273 main_r5fss0_core1: r5f@5d00000 { 2274 compatible = "ti,j721s2-r5f"; 2275 reg = <0x5d00000 0x00010000>, 2276 <0x5d10000 0x00010000>; 2277 reg-names = "atcm", "btcm"; 2278 ti,sci = <&sms>; 2279 ti,sci-dev-id = <340>; 2280 ti,sci-proc-ids = <0x07 0xff>; 2281 resets = <&k3_reset 340 1>; 2282 firmware-name = "j784s4-main-r5f0_1-fw"; 2283 ti,atcm-enable = <1>; 2284 ti,btcm-enable = <1>; 2285 ti,loczrama = <1>; 2286 }; 2287 }; 2288 2289 main_r5fss1: r5fss@5e00000 { 2290 compatible = "ti,j721s2-r5fss"; 2291 ti,cluster-mode = <1>; 2292 #address-cells = <1>; 2293 #size-cells = <1>; 2294 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2295 <0x5f00000 0x00 0x5f00000 0x20000>; 2296 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 2297 2298 main_r5fss1_core0: r5f@5e00000 { 2299 compatible = "ti,j721s2-r5f"; 2300 reg = <0x5e00000 0x00010000>, 2301 <0x5e10000 0x00010000>; 2302 reg-names = "atcm", "btcm"; 2303 ti,sci = <&sms>; 2304 ti,sci-dev-id = <341>; 2305 ti,sci-proc-ids = <0x08 0xff>; 2306 resets = <&k3_reset 341 1>; 2307 firmware-name = "j784s4-main-r5f1_0-fw"; 2308 ti,atcm-enable = <1>; 2309 ti,btcm-enable = <1>; 2310 ti,loczrama = <1>; 2311 }; 2312 2313 main_r5fss1_core1: r5f@5f00000 { 2314 compatible = "ti,j721s2-r5f"; 2315 reg = <0x5f00000 0x00010000>, 2316 <0x5f10000 0x00010000>; 2317 reg-names = "atcm", "btcm"; 2318 ti,sci = <&sms>; 2319 ti,sci-dev-id = <342>; 2320 ti,sci-proc-ids = <0x09 0xff>; 2321 resets = <&k3_reset 342 1>; 2322 firmware-name = "j784s4-main-r5f1_1-fw"; 2323 ti,atcm-enable = <1>; 2324 ti,btcm-enable = <1>; 2325 ti,loczrama = <1>; 2326 }; 2327 }; 2328 2329 main_r5fss2: r5fss@5900000 { 2330 compatible = "ti,j721s2-r5fss"; 2331 ti,cluster-mode = <1>; 2332 #address-cells = <1>; 2333 #size-cells = <1>; 2334 ranges = <0x5900000 0x00 0x5900000 0x20000>, 2335 <0x5a00000 0x00 0x5a00000 0x20000>; 2336 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 2337 2338 main_r5fss2_core0: r5f@5900000 { 2339 compatible = "ti,j721s2-r5f"; 2340 reg = <0x5900000 0x00010000>, 2341 <0x5910000 0x00010000>; 2342 reg-names = "atcm", "btcm"; 2343 ti,sci = <&sms>; 2344 ti,sci-dev-id = <343>; 2345 ti,sci-proc-ids = <0x0a 0xff>; 2346 resets = <&k3_reset 343 1>; 2347 firmware-name = "j784s4-main-r5f2_0-fw"; 2348 ti,atcm-enable = <1>; 2349 ti,btcm-enable = <1>; 2350 ti,loczrama = <1>; 2351 }; 2352 2353 main_r5fss2_core1: r5f@5a00000 { 2354 compatible = "ti,j721s2-r5f"; 2355 reg = <0x5a00000 0x00010000>, 2356 <0x5a10000 0x00010000>; 2357 reg-names = "atcm", "btcm"; 2358 ti,sci = <&sms>; 2359 ti,sci-dev-id = <344>; 2360 ti,sci-proc-ids = <0x0b 0xff>; 2361 resets = <&k3_reset 344 1>; 2362 firmware-name = "j784s4-main-r5f2_1-fw"; 2363 ti,atcm-enable = <1>; 2364 ti,btcm-enable = <1>; 2365 ti,loczrama = <1>; 2366 }; 2367 }; 2368 2369 c71_0: dsp@64800000 { 2370 compatible = "ti,j721s2-c71-dsp"; 2371 reg = <0x00 0x64800000 0x00 0x00080000>, 2372 <0x00 0x64e00000 0x00 0x0000c000>; 2373 reg-names = "l2sram", "l1dram"; 2374 ti,sci = <&sms>; 2375 ti,sci-dev-id = <30>; 2376 ti,sci-proc-ids = <0x30 0xff>; 2377 resets = <&k3_reset 30 1>; 2378 firmware-name = "j784s4-c71_0-fw"; 2379 status = "disabled"; 2380 }; 2381 2382 c71_1: dsp@65800000 { 2383 compatible = "ti,j721s2-c71-dsp"; 2384 reg = <0x00 0x65800000 0x00 0x00080000>, 2385 <0x00 0x65e00000 0x00 0x0000c000>; 2386 reg-names = "l2sram", "l1dram"; 2387 ti,sci = <&sms>; 2388 ti,sci-dev-id = <33>; 2389 ti,sci-proc-ids = <0x31 0xff>; 2390 resets = <&k3_reset 33 1>; 2391 firmware-name = "j784s4-c71_1-fw"; 2392 status = "disabled"; 2393 }; 2394 2395 c71_2: dsp@66800000 { 2396 compatible = "ti,j721s2-c71-dsp"; 2397 reg = <0x00 0x66800000 0x00 0x00080000>, 2398 <0x00 0x66e00000 0x00 0x0000c000>; 2399 reg-names = "l2sram", "l1dram"; 2400 ti,sci = <&sms>; 2401 ti,sci-dev-id = <37>; 2402 ti,sci-proc-ids = <0x32 0xff>; 2403 resets = <&k3_reset 37 1>; 2404 firmware-name = "j784s4-c71_2-fw"; 2405 status = "disabled"; 2406 }; 2407 2408 c71_3: dsp@67800000 { 2409 compatible = "ti,j721s2-c71-dsp"; 2410 reg = <0x00 0x67800000 0x00 0x00080000>, 2411 <0x00 0x67e00000 0x00 0x0000c000>; 2412 reg-names = "l2sram", "l1dram"; 2413 ti,sci = <&sms>; 2414 ti,sci-dev-id = <40>; 2415 ti,sci-proc-ids = <0x33 0xff>; 2416 resets = <&k3_reset 40 1>; 2417 firmware-name = "j784s4-c71_3-fw"; 2418 status = "disabled"; 2419 }; 2420 2421 main_esm: esm@700000 { 2422 compatible = "ti,j721e-esm"; 2423 reg = <0x00 0x700000 0x00 0x1000>; 2424 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 2425 <695>; 2426 bootph-pre-ram; 2427 }; 2428 2429 watchdog0: watchdog@2200000 { 2430 compatible = "ti,j7-rti-wdt"; 2431 reg = <0x00 0x2200000 0x00 0x100>; 2432 clocks = <&k3_clks 348 0>; 2433 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 2434 assigned-clocks = <&k3_clks 348 0>; 2435 assigned-clock-parents = <&k3_clks 348 4>; 2436 }; 2437 2438 watchdog1: watchdog@2210000 { 2439 compatible = "ti,j7-rti-wdt"; 2440 reg = <0x00 0x2210000 0x00 0x100>; 2441 clocks = <&k3_clks 349 0>; 2442 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 2443 assigned-clocks = <&k3_clks 349 0>; 2444 assigned-clock-parents = <&k3_clks 349 4>; 2445 }; 2446 2447 watchdog2: watchdog@2220000 { 2448 compatible = "ti,j7-rti-wdt"; 2449 reg = <0x00 0x2220000 0x00 0x100>; 2450 clocks = <&k3_clks 350 0>; 2451 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 2452 assigned-clocks = <&k3_clks 350 0>; 2453 assigned-clock-parents = <&k3_clks 350 4>; 2454 }; 2455 2456 watchdog3: watchdog@2230000 { 2457 compatible = "ti,j7-rti-wdt"; 2458 reg = <0x00 0x2230000 0x00 0x100>; 2459 clocks = <&k3_clks 351 0>; 2460 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 2461 assigned-clocks = <&k3_clks 351 0>; 2462 assigned-clock-parents = <&k3_clks 351 4>; 2463 }; 2464 2465 watchdog4: watchdog@2240000 { 2466 compatible = "ti,j7-rti-wdt"; 2467 reg = <0x00 0x2240000 0x00 0x100>; 2468 clocks = <&k3_clks 352 0>; 2469 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 2470 assigned-clocks = <&k3_clks 352 0>; 2471 assigned-clock-parents = <&k3_clks 352 4>; 2472 }; 2473 2474 watchdog5: watchdog@2250000 { 2475 compatible = "ti,j7-rti-wdt"; 2476 reg = <0x00 0x2250000 0x00 0x100>; 2477 clocks = <&k3_clks 353 0>; 2478 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 2479 assigned-clocks = <&k3_clks 353 0>; 2480 assigned-clock-parents = <&k3_clks 353 4>; 2481 }; 2482 2483 watchdog6: watchdog@2260000 { 2484 compatible = "ti,j7-rti-wdt"; 2485 reg = <0x00 0x2260000 0x00 0x100>; 2486 clocks = <&k3_clks 354 0>; 2487 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 2488 assigned-clocks = <&k3_clks 354 0>; 2489 assigned-clock-parents = <&k3_clks 354 4>; 2490 }; 2491 2492 watchdog7: watchdog@2270000 { 2493 compatible = "ti,j7-rti-wdt"; 2494 reg = <0x00 0x2270000 0x00 0x100>; 2495 clocks = <&k3_clks 355 0>; 2496 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 2497 assigned-clocks = <&k3_clks 355 0>; 2498 assigned-clock-parents = <&k3_clks 355 4>; 2499 }; 2500 2501 /* 2502 * The following RTI instances are coupled with MCU R5Fs, c7x and 2503 * GPU so keeping them reserved as these will be used by their 2504 * respective firmware 2505 */ 2506 watchdog8: watchdog@22f0000 { 2507 compatible = "ti,j7-rti-wdt"; 2508 reg = <0x00 0x22f0000 0x00 0x100>; 2509 clocks = <&k3_clks 360 0>; 2510 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 2511 assigned-clocks = <&k3_clks 360 0>; 2512 assigned-clock-parents = <&k3_clks 360 4>; 2513 /* reserved for GPU */ 2514 status = "reserved"; 2515 }; 2516 2517 watchdog9: watchdog@2300000 { 2518 compatible = "ti,j7-rti-wdt"; 2519 reg = <0x00 0x2300000 0x00 0x100>; 2520 clocks = <&k3_clks 356 0>; 2521 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 2522 assigned-clocks = <&k3_clks 356 0>; 2523 assigned-clock-parents = <&k3_clks 356 4>; 2524 /* reserved for C7X_0 DSP */ 2525 status = "reserved"; 2526 }; 2527 2528 watchdog10: watchdog@2310000 { 2529 compatible = "ti,j7-rti-wdt"; 2530 reg = <0x00 0x2310000 0x00 0x100>; 2531 clocks = <&k3_clks 357 0>; 2532 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 2533 assigned-clocks = <&k3_clks 357 0>; 2534 assigned-clock-parents = <&k3_clks 357 4>; 2535 /* reserved for C7X_1 DSP */ 2536 status = "reserved"; 2537 }; 2538 2539 watchdog11: watchdog@2320000 { 2540 compatible = "ti,j7-rti-wdt"; 2541 reg = <0x00 0x2320000 0x00 0x100>; 2542 clocks = <&k3_clks 358 0>; 2543 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 2544 assigned-clocks = <&k3_clks 358 0>; 2545 assigned-clock-parents = <&k3_clks 358 4>; 2546 /* reserved for C7X_2 DSP */ 2547 status = "reserved"; 2548 }; 2549 2550 watchdog12: watchdog@2330000 { 2551 compatible = "ti,j7-rti-wdt"; 2552 reg = <0x00 0x2330000 0x00 0x100>; 2553 clocks = <&k3_clks 359 0>; 2554 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 2555 assigned-clocks = <&k3_clks 359 0>; 2556 assigned-clock-parents = <&k3_clks 359 4>; 2557 /* reserved for C7X_3 DSP */ 2558 status = "reserved"; 2559 }; 2560 2561 watchdog13: watchdog@23c0000 { 2562 compatible = "ti,j7-rti-wdt"; 2563 reg = <0x00 0x23c0000 0x00 0x100>; 2564 clocks = <&k3_clks 361 0>; 2565 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 2566 assigned-clocks = <&k3_clks 361 0>; 2567 assigned-clock-parents = <&k3_clks 361 4>; 2568 /* reserved for MAIN_R5F0_0 */ 2569 status = "reserved"; 2570 }; 2571 2572 watchdog14: watchdog@23d0000 { 2573 compatible = "ti,j7-rti-wdt"; 2574 reg = <0x00 0x23d0000 0x00 0x100>; 2575 clocks = <&k3_clks 362 0>; 2576 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 2577 assigned-clocks = <&k3_clks 362 0>; 2578 assigned-clock-parents = <&k3_clks 362 4>; 2579 /* reserved for MAIN_R5F0_1 */ 2580 status = "reserved"; 2581 }; 2582 2583 watchdog15: watchdog@23e0000 { 2584 compatible = "ti,j7-rti-wdt"; 2585 reg = <0x00 0x23e0000 0x00 0x100>; 2586 clocks = <&k3_clks 363 0>; 2587 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 2588 assigned-clocks = <&k3_clks 363 0>; 2589 assigned-clock-parents = <&k3_clks 363 4>; 2590 /* reserved for MAIN_R5F1_0 */ 2591 status = "reserved"; 2592 }; 2593 2594 watchdog16: watchdog@23f0000 { 2595 compatible = "ti,j7-rti-wdt"; 2596 reg = <0x00 0x23f0000 0x00 0x100>; 2597 clocks = <&k3_clks 364 0>; 2598 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 2599 assigned-clocks = <&k3_clks 364 0>; 2600 assigned-clock-parents = <&k3_clks 364 4>; 2601 /* reserved for MAIN_R5F1_1 */ 2602 status = "reserved"; 2603 }; 2604 2605 watchdog17: watchdog@2540000 { 2606 compatible = "ti,j7-rti-wdt"; 2607 reg = <0x00 0x2540000 0x00 0x100>; 2608 clocks = <&k3_clks 365 0>; 2609 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 2610 assigned-clocks = <&k3_clks 365 0>; 2611 assigned-clock-parents = <&k3_clks 366 4>; 2612 /* reserved for MAIN_R5F2_0 */ 2613 status = "reserved"; 2614 }; 2615 2616 watchdog18: watchdog@2550000 { 2617 compatible = "ti,j7-rti-wdt"; 2618 reg = <0x00 0x2550000 0x00 0x100>; 2619 clocks = <&k3_clks 366 0>; 2620 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 2621 assigned-clocks = <&k3_clks 366 0>; 2622 assigned-clock-parents = <&k3_clks 366 4>; 2623 /* reserved for MAIN_R5F2_1 */ 2624 status = "reserved"; 2625 }; 2626 2627 mhdp: bridge@a000000 { 2628 compatible = "ti,j721e-mhdp8546"; 2629 reg = <0x0 0xa000000 0x0 0x30a00>, 2630 <0x0 0x4f40000 0x0 0x20>; 2631 reg-names = "mhdptx", "j721e-intg"; 2632 clocks = <&k3_clks 217 11>; 2633 interrupt-parent = <&gic500>; 2634 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2635 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2636 status = "disabled"; 2637 2638 dp0_ports: ports { 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 /* Remote-endpoints are on the boards so 2642 * ports are defined in the platform dt file. 2643 */ 2644 }; 2645 }; 2646 2647 dss: dss@4a00000 { 2648 compatible = "ti,j721e-dss"; 2649 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2650 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2651 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2652 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2653 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2654 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2655 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2656 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2657 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2658 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2659 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2660 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2661 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2662 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2663 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2664 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2665 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2666 reg-names = "common_m", "common_s0", 2667 "common_s1", "common_s2", 2668 "vidl1", "vidl2","vid1","vid2", 2669 "ovr1", "ovr2", "ovr3", "ovr4", 2670 "vp1", "vp2", "vp3", "vp4", 2671 "wb"; 2672 clocks = <&k3_clks 218 0>, 2673 <&k3_clks 218 2>, 2674 <&k3_clks 218 5>, 2675 <&k3_clks 218 14>, 2676 <&k3_clks 218 18>; 2677 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2678 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2679 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2680 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2681 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2682 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2683 interrupt-names = "common_m", 2684 "common_s0", 2685 "common_s1", 2686 "common_s2"; 2687 status = "disabled"; 2688 2689 dss_ports: ports { 2690 /* Ports that DSS drives are platform specific 2691 * so they are defined in platform dt file. 2692 */ 2693 }; 2694 }; 2695 2696 mcasp0: mcasp@2b00000 { 2697 compatible = "ti,am33xx-mcasp-audio"; 2698 reg = <0x00 0x02b00000 0x00 0x2000>, 2699 <0x00 0x02b08000 0x00 0x1000>; 2700 reg-names = "mpu","dat"; 2701 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 2703 interrupt-names = "tx", "rx"; 2704 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 2705 dma-names = "tx", "rx"; 2706 clocks = <&k3_clks 265 0>; 2707 clock-names = "fck"; 2708 assigned-clocks = <&k3_clks 265 0>; 2709 assigned-clock-parents = <&k3_clks 265 1>; 2710 power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>; 2711 status = "disabled"; 2712 }; 2713 2714 mcasp1: mcasp@2b10000 { 2715 compatible = "ti,am33xx-mcasp-audio"; 2716 reg = <0x00 0x02b10000 0x00 0x2000>, 2717 <0x00 0x02b18000 0x00 0x1000>; 2718 reg-names = "mpu","dat"; 2719 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 2721 interrupt-names = "tx", "rx"; 2722 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 2723 dma-names = "tx", "rx"; 2724 clocks = <&k3_clks 266 0>; 2725 clock-names = "fck"; 2726 assigned-clocks = <&k3_clks 266 0>; 2727 assigned-clock-parents = <&k3_clks 266 1>; 2728 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2729 status = "disabled"; 2730 }; 2731 2732 mcasp2: mcasp@2b20000 { 2733 compatible = "ti,am33xx-mcasp-audio"; 2734 reg = <0x00 0x02b20000 0x00 0x2000>, 2735 <0x00 0x02b28000 0x00 0x1000>; 2736 reg-names = "mpu","dat"; 2737 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 2738 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 2739 interrupt-names = "tx", "rx"; 2740 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 2741 dma-names = "tx", "rx"; 2742 clocks = <&k3_clks 267 0>; 2743 clock-names = "fck"; 2744 assigned-clocks = <&k3_clks 267 0>; 2745 assigned-clock-parents = <&k3_clks 267 1>; 2746 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2747 status = "disabled"; 2748 }; 2749 2750 mcasp3: mcasp@2b30000 { 2751 compatible = "ti,am33xx-mcasp-audio"; 2752 reg = <0x00 0x02b30000 0x00 0x2000>, 2753 <0x00 0x02b38000 0x00 0x1000>; 2754 reg-names = "mpu","dat"; 2755 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 2757 interrupt-names = "tx", "rx"; 2758 dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>; 2759 dma-names = "tx", "rx"; 2760 clocks = <&k3_clks 268 0>; 2761 clock-names = "fck"; 2762 assigned-clocks = <&k3_clks 268 0>; 2763 assigned-clock-parents = <&k3_clks 268 1>; 2764 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2765 status = "disabled"; 2766 }; 2767 2768 mcasp4: mcasp@2b40000 { 2769 compatible = "ti,am33xx-mcasp-audio"; 2770 reg = <0x00 0x02b40000 0x00 0x2000>, 2771 <0x00 0x02b48000 0x00 0x1000>; 2772 reg-names = "mpu","dat"; 2773 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 2775 interrupt-names = "tx", "rx"; 2776 dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>; 2777 dma-names = "tx", "rx"; 2778 clocks = <&k3_clks 269 0>; 2779 clock-names = "fck"; 2780 assigned-clocks = <&k3_clks 269 0>; 2781 assigned-clock-parents = <&k3_clks 269 1>; 2782 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2783 status = "disabled"; 2784 }; 2785}; 2786