1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 msmc_ram: sram@70000000 { 25 compatible = "mmio-sram"; 26 reg = <0x00 0x70000000 0x00 0x800000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x00 0x00 0x70000000 0x800000>; 30 31 atf-sram@0 { 32 reg = <0x00 0x20000>; 33 }; 34 35 tifs-sram@1f0000 { 36 reg = <0x1f0000 0x10000>; 37 }; 38 39 l3cache-sram@200000 { 40 reg = <0x200000 0x200000>; 41 }; 42 }; 43 44 scm_conf: bus@100000 { 45 compatible = "simple-bus"; 46 reg = <0x00 0x00100000 0x00 0x1c000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x1c000>; 50 51 serdes_ln_ctrl: mux-controller@4080 { 52 compatible = "reg-mux"; 53 reg = <0x00004080 0x30>; 54 #mux-control-cells = <1>; 55 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 56 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ 57 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 58 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ 59 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 60 <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ 61 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 62 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 63 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 64 <J784S4_SERDES0_LANE3_USB>, 65 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 66 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 67 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 68 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 69 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 70 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 71 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 72 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 73 <J784S4_SERDES4_LANE0_EDP_LANE0>, 74 <J784S4_SERDES4_LANE1_EDP_LANE1>, 75 <J784S4_SERDES4_LANE2_EDP_LANE2>, 76 <J784S4_SERDES4_LANE3_EDP_LANE3>; 77 }; 78 }; 79 80 gic500: interrupt-controller@1800000 { 81 compatible = "arm,gic-v3"; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 #interrupt-cells = <3>; 86 interrupt-controller; 87 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 88 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 89 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 90 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 91 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 92 93 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 94 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 95 96 gic_its: msi-controller@1820000 { 97 compatible = "arm,gic-v3-its"; 98 reg = <0x00 0x01820000 0x00 0x10000>; 99 socionext,synquacer-pre-its = <0x1000000 0x400000>; 100 msi-controller; 101 #msi-cells = <1>; 102 }; 103 }; 104 105 main_gpio_intr: interrupt-controller@a00000 { 106 compatible = "ti,sci-intr"; 107 reg = <0x00 0x00a00000 0x00 0x800>; 108 ti,intr-trigger-type = <1>; 109 interrupt-controller; 110 interrupt-parent = <&gic500>; 111 #interrupt-cells = <1>; 112 ti,sci = <&sms>; 113 ti,sci-dev-id = <10>; 114 ti,interrupt-ranges = <8 392 56>; 115 }; 116 117 main_pmx0: pinctrl@11c000 { 118 compatible = "pinctrl-single"; 119 /* Proxy 0 addressing */ 120 reg = <0x00 0x11c000 0x00 0x120>; 121 #pinctrl-cells = <1>; 122 pinctrl-single,register-width = <32>; 123 pinctrl-single,function-mask = <0xffffffff>; 124 }; 125 126 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 127 main_timerio_input: pinctrl@104200 { 128 compatible = "pinctrl-single"; 129 reg = <0x00 0x104200 0x00 0x50>; 130 #pinctrl-cells = <1>; 131 pinctrl-single,register-width = <32>; 132 pinctrl-single,function-mask = <0x00000007>; 133 }; 134 135 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 136 main_timerio_output: pinctrl@104280 { 137 compatible = "pinctrl-single"; 138 reg = <0x00 0x104280 0x00 0x20>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0x0000001f>; 142 }; 143 144 main_crypto: crypto@4e00000 { 145 compatible = "ti,j721e-sa2ul"; 146 reg = <0x00 0x4e00000 0x00 0x1200>; 147 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 151 152 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 153 <&main_udmap 0x4a41>; 154 dma-names = "tx", "rx1", "rx2"; 155 156 rng: rng@4e10000 { 157 compatible = "inside-secure,safexcel-eip76"; 158 reg = <0x00 0x4e10000 0x00 0x7d>; 159 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 }; 162 163 main_timer0: timer@2400000 { 164 compatible = "ti,am654-timer"; 165 reg = <0x00 0x2400000 0x00 0x400>; 166 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&k3_clks 97 2>; 168 clock-names = "fck"; 169 assigned-clocks = <&k3_clks 97 2>; 170 assigned-clock-parents = <&k3_clks 97 3>; 171 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 172 ti,timer-pwm; 173 }; 174 175 main_timer1: timer@2410000 { 176 compatible = "ti,am654-timer"; 177 reg = <0x00 0x2410000 0x00 0x400>; 178 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&k3_clks 98 2>; 180 clock-names = "fck"; 181 assigned-clocks = <&k3_clks 98 2>; 182 assigned-clock-parents = <&k3_clks 98 3>; 183 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 184 ti,timer-pwm; 185 }; 186 187 main_timer2: timer@2420000 { 188 compatible = "ti,am654-timer"; 189 reg = <0x00 0x2420000 0x00 0x400>; 190 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&k3_clks 99 2>; 192 clock-names = "fck"; 193 assigned-clocks = <&k3_clks 99 2>; 194 assigned-clock-parents = <&k3_clks 99 3>; 195 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 196 ti,timer-pwm; 197 }; 198 199 main_timer3: timer@2430000 { 200 compatible = "ti,am654-timer"; 201 reg = <0x00 0x2430000 0x00 0x400>; 202 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&k3_clks 100 2>; 204 clock-names = "fck"; 205 assigned-clocks = <&k3_clks 100 2>; 206 assigned-clock-parents = <&k3_clks 100 3>; 207 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 208 ti,timer-pwm; 209 }; 210 211 main_timer4: timer@2440000 { 212 compatible = "ti,am654-timer"; 213 reg = <0x00 0x2440000 0x00 0x400>; 214 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&k3_clks 101 2>; 216 clock-names = "fck"; 217 assigned-clocks = <&k3_clks 101 2>; 218 assigned-clock-parents = <&k3_clks 101 3>; 219 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 220 ti,timer-pwm; 221 }; 222 223 main_timer5: timer@2450000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x2450000 0x00 0x400>; 226 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 102 2>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 102 2>; 230 assigned-clock-parents = <&k3_clks 102 3>; 231 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 }; 234 235 main_timer6: timer@2460000 { 236 compatible = "ti,am654-timer"; 237 reg = <0x00 0x2460000 0x00 0x400>; 238 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&k3_clks 103 2>; 240 clock-names = "fck"; 241 assigned-clocks = <&k3_clks 103 2>; 242 assigned-clock-parents = <&k3_clks 103 3>; 243 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 244 ti,timer-pwm; 245 }; 246 247 main_timer7: timer@2470000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x2470000 0x00 0x400>; 250 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 104 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 104 2>; 254 assigned-clock-parents = <&k3_clks 104 3>; 255 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 }; 258 259 main_timer8: timer@2480000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x2480000 0x00 0x400>; 262 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 105 2>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 105 2>; 266 assigned-clock-parents = <&k3_clks 105 3>; 267 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 }; 270 271 main_timer9: timer@2490000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2490000 0x00 0x400>; 274 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 106 2>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 106 2>; 278 assigned-clock-parents = <&k3_clks 106 3>; 279 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 }; 282 283 main_timer10: timer@24a0000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x24a0000 0x00 0x400>; 286 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 107 2>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 107 2>; 290 assigned-clock-parents = <&k3_clks 107 3>; 291 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 }; 294 295 main_timer11: timer@24b0000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x24b0000 0x00 0x400>; 298 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 108 2>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 108 2>; 302 assigned-clock-parents = <&k3_clks 108 3>; 303 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 }; 306 307 main_timer12: timer@24c0000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x24c0000 0x00 0x400>; 310 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 109 2>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 109 2>; 314 assigned-clock-parents = <&k3_clks 109 3>; 315 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer13: timer@24d0000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x24d0000 0x00 0x400>; 322 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 110 2>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 110 2>; 326 assigned-clock-parents = <&k3_clks 110 3>; 327 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_timer14: timer@24e0000 { 332 compatible = "ti,am654-timer"; 333 reg = <0x00 0x24e0000 0x00 0x400>; 334 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&k3_clks 111 2>; 336 clock-names = "fck"; 337 assigned-clocks = <&k3_clks 111 2>; 338 assigned-clock-parents = <&k3_clks 111 3>; 339 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 340 ti,timer-pwm; 341 }; 342 343 main_timer15: timer@24f0000 { 344 compatible = "ti,am654-timer"; 345 reg = <0x00 0x24f0000 0x00 0x400>; 346 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&k3_clks 112 2>; 348 clock-names = "fck"; 349 assigned-clocks = <&k3_clks 112 2>; 350 assigned-clock-parents = <&k3_clks 112 3>; 351 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 352 ti,timer-pwm; 353 }; 354 355 main_timer16: timer@2500000 { 356 compatible = "ti,am654-timer"; 357 reg = <0x00 0x2500000 0x00 0x400>; 358 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 113 2>; 360 clock-names = "fck"; 361 assigned-clocks = <&k3_clks 113 2>; 362 assigned-clock-parents = <&k3_clks 113 3>; 363 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 364 ti,timer-pwm; 365 }; 366 367 main_timer17: timer@2510000 { 368 compatible = "ti,am654-timer"; 369 reg = <0x00 0x2510000 0x00 0x400>; 370 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&k3_clks 114 2>; 372 clock-names = "fck"; 373 assigned-clocks = <&k3_clks 114 2>; 374 assigned-clock-parents = <&k3_clks 114 3>; 375 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 376 ti,timer-pwm; 377 }; 378 379 main_timer18: timer@2520000 { 380 compatible = "ti,am654-timer"; 381 reg = <0x00 0x2520000 0x00 0x400>; 382 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&k3_clks 115 2>; 384 clock-names = "fck"; 385 assigned-clocks = <&k3_clks 115 2>; 386 assigned-clock-parents = <&k3_clks 115 3>; 387 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 388 ti,timer-pwm; 389 }; 390 391 main_timer19: timer@2530000 { 392 compatible = "ti,am654-timer"; 393 reg = <0x00 0x2530000 0x00 0x400>; 394 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&k3_clks 116 2>; 396 clock-names = "fck"; 397 assigned-clocks = <&k3_clks 116 2>; 398 assigned-clock-parents = <&k3_clks 116 3>; 399 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 400 ti,timer-pwm; 401 }; 402 403 main_uart0: serial@2800000 { 404 compatible = "ti,j721e-uart", "ti,am654-uart"; 405 reg = <0x00 0x02800000 0x00 0x200>; 406 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 407 current-speed = <115200>; 408 clocks = <&k3_clks 146 0>; 409 clock-names = "fclk"; 410 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 411 status = "disabled"; 412 }; 413 414 main_uart1: serial@2810000 { 415 compatible = "ti,j721e-uart", "ti,am654-uart"; 416 reg = <0x00 0x02810000 0x00 0x200>; 417 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 418 current-speed = <115200>; 419 clocks = <&k3_clks 388 0>; 420 clock-names = "fclk"; 421 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 422 status = "disabled"; 423 }; 424 425 main_uart2: serial@2820000 { 426 compatible = "ti,j721e-uart", "ti,am654-uart"; 427 reg = <0x00 0x02820000 0x00 0x200>; 428 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 429 current-speed = <115200>; 430 clocks = <&k3_clks 389 0>; 431 clock-names = "fclk"; 432 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 433 status = "disabled"; 434 }; 435 436 main_uart3: serial@2830000 { 437 compatible = "ti,j721e-uart", "ti,am654-uart"; 438 reg = <0x00 0x02830000 0x00 0x200>; 439 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 440 current-speed = <115200>; 441 clocks = <&k3_clks 390 0>; 442 clock-names = "fclk"; 443 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 444 status = "disabled"; 445 }; 446 447 main_uart4: serial@2840000 { 448 compatible = "ti,j721e-uart", "ti,am654-uart"; 449 reg = <0x00 0x02840000 0x00 0x200>; 450 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 451 current-speed = <115200>; 452 clocks = <&k3_clks 391 0>; 453 clock-names = "fclk"; 454 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 455 status = "disabled"; 456 }; 457 458 main_uart5: serial@2850000 { 459 compatible = "ti,j721e-uart", "ti,am654-uart"; 460 reg = <0x00 0x02850000 0x00 0x200>; 461 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 462 current-speed = <115200>; 463 clocks = <&k3_clks 392 0>; 464 clock-names = "fclk"; 465 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 466 status = "disabled"; 467 }; 468 469 main_uart6: serial@2860000 { 470 compatible = "ti,j721e-uart", "ti,am654-uart"; 471 reg = <0x00 0x02860000 0x00 0x200>; 472 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 473 current-speed = <115200>; 474 clocks = <&k3_clks 393 0>; 475 clock-names = "fclk"; 476 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 477 status = "disabled"; 478 }; 479 480 main_uart7: serial@2870000 { 481 compatible = "ti,j721e-uart", "ti,am654-uart"; 482 reg = <0x00 0x02870000 0x00 0x200>; 483 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 484 current-speed = <115200>; 485 clocks = <&k3_clks 394 0>; 486 clock-names = "fclk"; 487 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 488 status = "disabled"; 489 }; 490 491 main_uart8: serial@2880000 { 492 compatible = "ti,j721e-uart", "ti,am654-uart"; 493 reg = <0x00 0x02880000 0x00 0x200>; 494 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 495 current-speed = <115200>; 496 clocks = <&k3_clks 395 0>; 497 clock-names = "fclk"; 498 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 499 status = "disabled"; 500 }; 501 502 main_uart9: serial@2890000 { 503 compatible = "ti,j721e-uart", "ti,am654-uart"; 504 reg = <0x00 0x02890000 0x00 0x200>; 505 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 506 current-speed = <115200>; 507 clocks = <&k3_clks 396 0>; 508 clock-names = "fclk"; 509 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 510 status = "disabled"; 511 }; 512 513 main_gpio0: gpio@600000 { 514 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 515 reg = <0x00 0x00600000 0x00 0x100>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-parent = <&main_gpio_intr>; 519 interrupts = <145>, <146>, <147>, <148>, <149>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 ti,ngpio = <66>; 523 ti,davinci-gpio-unbanked = <0>; 524 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 525 clocks = <&k3_clks 163 0>; 526 clock-names = "gpio"; 527 status = "disabled"; 528 }; 529 530 main_gpio2: gpio@610000 { 531 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 532 reg = <0x00 0x00610000 0x00 0x100>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-parent = <&main_gpio_intr>; 536 interrupts = <154>, <155>, <156>, <157>, <158>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 ti,ngpio = <66>; 540 ti,davinci-gpio-unbanked = <0>; 541 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 542 clocks = <&k3_clks 164 0>; 543 clock-names = "gpio"; 544 status = "disabled"; 545 }; 546 547 main_gpio4: gpio@620000 { 548 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 549 reg = <0x00 0x00620000 0x00 0x100>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 interrupt-parent = <&main_gpio_intr>; 553 interrupts = <163>, <164>, <165>, <166>, <167>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 ti,ngpio = <66>; 557 ti,davinci-gpio-unbanked = <0>; 558 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 559 clocks = <&k3_clks 165 0>; 560 clock-names = "gpio"; 561 status = "disabled"; 562 }; 563 564 main_gpio6: gpio@630000 { 565 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 566 reg = <0x00 0x00630000 0x00 0x100>; 567 gpio-controller; 568 #gpio-cells = <2>; 569 interrupt-parent = <&main_gpio_intr>; 570 interrupts = <172>, <173>, <174>, <175>, <176>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 ti,ngpio = <66>; 574 ti,davinci-gpio-unbanked = <0>; 575 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 576 clocks = <&k3_clks 166 0>; 577 clock-names = "gpio"; 578 status = "disabled"; 579 }; 580 581 main_i2c0: i2c@2000000 { 582 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 583 reg = <0x00 0x02000000 0x00 0x100>; 584 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 clocks = <&k3_clks 270 2>; 588 clock-names = "fck"; 589 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 590 status = "disabled"; 591 }; 592 593 main_i2c1: i2c@2010000 { 594 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 595 reg = <0x00 0x02010000 0x00 0x100>; 596 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 clocks = <&k3_clks 271 2>; 600 clock-names = "fck"; 601 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 602 status = "disabled"; 603 }; 604 605 main_i2c2: i2c@2020000 { 606 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 607 reg = <0x00 0x02020000 0x00 0x100>; 608 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clocks = <&k3_clks 272 2>; 612 clock-names = "fck"; 613 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 614 status = "disabled"; 615 }; 616 617 main_i2c3: i2c@2030000 { 618 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 619 reg = <0x00 0x02030000 0x00 0x100>; 620 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 clocks = <&k3_clks 273 2>; 624 clock-names = "fck"; 625 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 626 status = "disabled"; 627 }; 628 629 main_i2c4: i2c@2040000 { 630 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 631 reg = <0x00 0x02040000 0x00 0x100>; 632 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 clocks = <&k3_clks 274 2>; 636 clock-names = "fck"; 637 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 638 status = "disabled"; 639 }; 640 641 main_i2c5: i2c@2050000 { 642 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 643 reg = <0x00 0x02050000 0x00 0x100>; 644 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 clocks = <&k3_clks 275 2>; 648 clock-names = "fck"; 649 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 650 status = "disabled"; 651 }; 652 653 main_i2c6: i2c@2060000 { 654 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 655 reg = <0x00 0x02060000 0x00 0x100>; 656 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&k3_clks 276 2>; 660 clock-names = "fck"; 661 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 662 status = "disabled"; 663 }; 664 665 ti_csi2rx0: ticsi2rx@4500000 { 666 compatible = "ti,j721e-csi2rx-shim"; 667 reg = <0x00 0x04500000 0x00 0x00001000>; 668 ranges; 669 #address-cells = <2>; 670 #size-cells = <2>; 671 dmas = <&main_bcdma_csi 0 0x4940 0>; 672 dma-names = "rx0"; 673 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 674 status = "disabled"; 675 676 cdns_csi2rx0: csi-bridge@4504000 { 677 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 678 reg = <0x00 0x04504000 0x00 0x00001000>; 679 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, 680 <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; 681 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 682 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 683 phys = <&dphy0>; 684 phy-names = "dphy"; 685 686 ports { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 690 csi0_port0: port@0 { 691 reg = <0>; 692 status = "disabled"; 693 }; 694 695 csi0_port1: port@1 { 696 reg = <1>; 697 status = "disabled"; 698 }; 699 700 csi0_port2: port@2 { 701 reg = <2>; 702 status = "disabled"; 703 }; 704 705 csi0_port3: port@3 { 706 reg = <3>; 707 status = "disabled"; 708 }; 709 710 csi0_port4: port@4 { 711 reg = <4>; 712 status = "disabled"; 713 }; 714 }; 715 }; 716 }; 717 718 ti_csi2rx1: ticsi2rx@4510000 { 719 compatible = "ti,j721e-csi2rx-shim"; 720 reg = <0x00 0x04510000 0x00 0x1000>; 721 ranges; 722 #address-cells = <2>; 723 #size-cells = <2>; 724 dmas = <&main_bcdma_csi 0 0x4960 0>; 725 dma-names = "rx0"; 726 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 727 status = "disabled"; 728 729 cdns_csi2rx1: csi-bridge@4514000 { 730 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 731 reg = <0x00 0x04514000 0x00 0x00001000>; 732 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, 733 <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; 734 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 735 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 736 phys = <&dphy1>; 737 phy-names = "dphy"; 738 ports { 739 #address-cells = <1>; 740 #size-cells = <0>; 741 742 csi1_port0: port@0 { 743 reg = <0>; 744 status = "disabled"; 745 }; 746 747 csi1_port1: port@1 { 748 reg = <1>; 749 status = "disabled"; 750 }; 751 752 csi1_port2: port@2 { 753 reg = <2>; 754 status = "disabled"; 755 }; 756 757 csi1_port3: port@3 { 758 reg = <3>; 759 status = "disabled"; 760 }; 761 762 csi1_port4: port@4 { 763 reg = <4>; 764 status = "disabled"; 765 }; 766 }; 767 }; 768 }; 769 770 ti_csi2rx2: ticsi2rx@4520000 { 771 compatible = "ti,j721e-csi2rx-shim"; 772 reg = <0x00 0x04520000 0x00 0x00001000>; 773 ranges; 774 #address-cells = <2>; 775 #size-cells = <2>; 776 dmas = <&main_bcdma_csi 0 0x4980 0>; 777 dma-names = "rx0"; 778 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 779 status = "disabled"; 780 781 cdns_csi2rx2: csi-bridge@4524000 { 782 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 783 reg = <0x00 0x04524000 0x00 0x00001000>; 784 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, 785 <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; 786 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 787 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 788 phys = <&dphy2>; 789 phy-names = "dphy"; 790 791 ports { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 795 csi2_port0: port@0 { 796 reg = <0>; 797 status = "disabled"; 798 }; 799 800 csi2_port1: port@1 { 801 reg = <1>; 802 status = "disabled"; 803 }; 804 805 csi2_port2: port@2 { 806 reg = <2>; 807 status = "disabled"; 808 }; 809 810 csi2_port3: port@3 { 811 reg = <3>; 812 status = "disabled"; 813 }; 814 815 csi2_port4: port@4 { 816 reg = <4>; 817 status = "disabled"; 818 }; 819 }; 820 }; 821 }; 822 823 dphy0: phy@4580000 { 824 compatible = "cdns,dphy-rx"; 825 reg = <0x00 0x04580000 0x00 0x00001100>; 826 #phy-cells = <0>; 827 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; 828 status = "disabled"; 829 }; 830 831 dphy1: phy@4590000 { 832 compatible = "cdns,dphy-rx"; 833 reg = <0x00 0x04590000 0x00 0x00001100>; 834 #phy-cells = <0>; 835 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; 836 status = "disabled"; 837 }; 838 839 dphy2: phy@45a0000 { 840 compatible = "cdns,dphy-rx"; 841 reg = <0x00 0x045a0000 0x00 0x00001100>; 842 #phy-cells = <0>; 843 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 844 status = "disabled"; 845 }; 846 847 vpu0: video-codec@4210000 { 848 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 849 reg = <0x00 0x4210000 0x00 0x10000>; 850 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&k3_clks 241 2>; 852 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 853 }; 854 855 vpu1: video-codec@4220000 { 856 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 857 reg = <0x00 0x4220000 0x00 0x10000>; 858 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&k3_clks 242 2>; 860 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 861 }; 862 863 main_sdhci0: mmc@4f80000 { 864 compatible = "ti,j721e-sdhci-8bit"; 865 reg = <0x00 0x04f80000 0x00 0x1000>, 866 <0x00 0x04f88000 0x00 0x400>; 867 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 868 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 869 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 870 clock-names = "clk_ahb", "clk_xin"; 871 assigned-clocks = <&k3_clks 140 2>; 872 assigned-clock-parents = <&k3_clks 140 3>; 873 bus-width = <8>; 874 ti,otap-del-sel-legacy = <0x0>; 875 ti,otap-del-sel-mmc-hs = <0x0>; 876 ti,otap-del-sel-ddr52 = <0x6>; 877 ti,otap-del-sel-hs200 = <0x8>; 878 ti,otap-del-sel-hs400 = <0x5>; 879 ti,itap-del-sel-legacy = <0x10>; 880 ti,itap-del-sel-mmc-hs = <0xa>; 881 ti,strobe-sel = <0x77>; 882 ti,clkbuf-sel = <0x7>; 883 ti,trm-icp = <0x8>; 884 mmc-ddr-1_8v; 885 mmc-hs200-1_8v; 886 mmc-hs400-1_8v; 887 dma-coherent; 888 status = "disabled"; 889 }; 890 891 main_sdhci1: mmc@4fb0000 { 892 compatible = "ti,j721e-sdhci-4bit"; 893 reg = <0x00 0x04fb0000 0x00 0x1000>, 894 <0x00 0x04fb8000 0x00 0x400>; 895 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 896 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 897 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 898 clock-names = "clk_ahb", "clk_xin"; 899 assigned-clocks = <&k3_clks 141 4>; 900 assigned-clock-parents = <&k3_clks 141 5>; 901 bus-width = <4>; 902 ti,otap-del-sel-legacy = <0x0>; 903 ti,otap-del-sel-sd-hs = <0x0>; 904 ti,otap-del-sel-sdr12 = <0xf>; 905 ti,otap-del-sel-sdr25 = <0xf>; 906 ti,otap-del-sel-sdr50 = <0xc>; 907 ti,otap-del-sel-sdr104 = <0x5>; 908 ti,otap-del-sel-ddr50 = <0xc>; 909 ti,itap-del-sel-legacy = <0x0>; 910 ti,itap-del-sel-sd-hs = <0x0>; 911 ti,itap-del-sel-sdr12 = <0x0>; 912 ti,itap-del-sel-sdr25 = <0x0>; 913 ti,itap-del-sel-ddr50 = <0x2>; 914 ti,clkbuf-sel = <0x7>; 915 ti,trm-icp = <0x8>; 916 dma-coherent; 917 sdhci-caps-mask = <0x00000003 0x00000000>; 918 no-1-8-v; 919 status = "disabled"; 920 }; 921 922 serdes_wiz0: wiz@5060000 { 923 compatible = "ti,j784s4-wiz-10g"; 924 #address-cells = <1>; 925 #size-cells = <1>; 926 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 927 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 928 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 929 assigned-clocks = <&k3_clks 404 6>; 930 assigned-clock-parents = <&k3_clks 404 10>; 931 num-lanes = <4>; 932 #reset-cells = <1>; 933 #clock-cells = <1>; 934 ranges = <0x5060000 0x00 0x5060000 0x10000>; 935 status = "disabled"; 936 937 serdes0: serdes@5060000 { 938 compatible = "ti,j721e-serdes-10g"; 939 reg = <0x05060000 0x010000>; 940 reg-names = "torrent_phy"; 941 resets = <&serdes_wiz0 0>; 942 reset-names = "torrent_reset"; 943 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 944 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 945 clock-names = "refclk", "phy_en_refclk"; 946 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 947 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 948 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 949 assigned-clock-parents = <&k3_clks 404 6>, 950 <&k3_clks 404 6>, 951 <&k3_clks 404 6>; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 #clock-cells = <1>; 955 status = "disabled"; 956 }; 957 }; 958 959 serdes_wiz1: wiz@5070000 { 960 compatible = "ti,j784s4-wiz-10g"; 961 #address-cells = <1>; 962 #size-cells = <1>; 963 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 964 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 965 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 966 assigned-clocks = <&k3_clks 405 6>; 967 assigned-clock-parents = <&k3_clks 405 10>; 968 num-lanes = <4>; 969 #reset-cells = <1>; 970 #clock-cells = <1>; 971 ranges = <0x05070000 0x00 0x05070000 0x10000>; 972 status = "disabled"; 973 974 serdes1: serdes@5070000 { 975 compatible = "ti,j721e-serdes-10g"; 976 reg = <0x05070000 0x010000>; 977 reg-names = "torrent_phy"; 978 resets = <&serdes_wiz1 0>; 979 reset-names = "torrent_reset"; 980 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 981 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 982 clock-names = "refclk", "phy_en_refclk"; 983 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 984 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 985 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 986 assigned-clock-parents = <&k3_clks 405 6>, 987 <&k3_clks 405 6>, 988 <&k3_clks 405 6>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 #clock-cells = <1>; 992 status = "disabled"; 993 }; 994 }; 995 996 serdes_wiz2: wiz@5020000 { 997 compatible = "ti,j784s4-wiz-10g"; 998 #address-cells = <1>; 999 #size-cells = <1>; 1000 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; 1001 clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; 1002 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1003 assigned-clocks = <&k3_clks 406 6>; 1004 assigned-clock-parents = <&k3_clks 406 10>; 1005 num-lanes = <4>; 1006 #reset-cells = <1>; 1007 #clock-cells = <1>; 1008 ranges = <0x05020000 0x00 0x05020000 0x10000>; 1009 status = "disabled"; 1010 1011 serdes2: serdes@5020000 { 1012 compatible = "ti,j721e-serdes-10g"; 1013 reg = <0x05020000 0x010000>; 1014 reg-names = "torrent_phy"; 1015 resets = <&serdes_wiz2 0>; 1016 reset-names = "torrent_reset"; 1017 clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 1018 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; 1019 clock-names = "refclk", "phy_en_refclk"; 1020 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 1021 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, 1022 <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; 1023 assigned-clock-parents = <&k3_clks 406 6>, 1024 <&k3_clks 406 6>, 1025 <&k3_clks 406 6>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 #clock-cells = <1>; 1029 status = "disabled"; 1030 }; 1031 }; 1032 1033 serdes_wiz4: wiz@5050000 { 1034 compatible = "ti,j784s4-wiz-10g"; 1035 #address-cells = <1>; 1036 #size-cells = <1>; 1037 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 1038 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 1039 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1040 assigned-clocks = <&k3_clks 407 6>; 1041 assigned-clock-parents = <&k3_clks 407 10>; 1042 num-lanes = <4>; 1043 #reset-cells = <1>; 1044 #clock-cells = <1>; 1045 ranges = <0x05050000 0x00 0x05050000 0x10000>, 1046 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 1047 status = "disabled"; 1048 1049 serdes4: serdes@5050000 { 1050 /* 1051 * Note: we also map DPTX PHY registers as the Torrent 1052 * needs to manage those. 1053 */ 1054 compatible = "ti,j721e-serdes-10g"; 1055 reg = <0x05050000 0x010000>, 1056 <0x0a030a00 0x40>; /* DPTX PHY */ 1057 reg-names = "torrent_phy"; 1058 resets = <&serdes_wiz4 0>; 1059 reset-names = "torrent_reset"; 1060 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1061 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 1062 clock-names = "refclk", "phy_en_refclk"; 1063 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1064 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1065 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1066 assigned-clock-parents = <&k3_clks 407 6>, 1067 <&k3_clks 407 6>, 1068 <&k3_clks 407 6>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 #clock-cells = <1>; 1072 status = "disabled"; 1073 }; 1074 }; 1075 1076 main_navss: bus@30000000 { 1077 bootph-all; 1078 compatible = "simple-bus"; 1079 #address-cells = <2>; 1080 #size-cells = <2>; 1081 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 1082 ti,sci-dev-id = <280>; 1083 dma-coherent; 1084 dma-ranges; 1085 1086 main_navss_intr: interrupt-controller@310e0000 { 1087 compatible = "ti,sci-intr"; 1088 reg = <0x00 0x310e0000 0x00 0x4000>; 1089 ti,intr-trigger-type = <4>; 1090 interrupt-controller; 1091 interrupt-parent = <&gic500>; 1092 #interrupt-cells = <1>; 1093 ti,sci = <&sms>; 1094 ti,sci-dev-id = <283>; 1095 ti,interrupt-ranges = <0 64 64>, 1096 <64 448 64>, 1097 <128 672 64>; 1098 }; 1099 1100 main_udmass_inta: msi-controller@33d00000 { 1101 compatible = "ti,sci-inta"; 1102 reg = <0x00 0x33d00000 0x00 0x100000>; 1103 interrupt-controller; 1104 #interrupt-cells = <0>; 1105 interrupt-parent = <&main_navss_intr>; 1106 msi-controller; 1107 ti,sci = <&sms>; 1108 ti,sci-dev-id = <321>; 1109 ti,interrupt-ranges = <0 0 256>; 1110 ti,unmapped-event-sources = <&main_bcdma_csi>; 1111 }; 1112 1113 secure_proxy_main: mailbox@32c00000 { 1114 bootph-all; 1115 compatible = "ti,am654-secure-proxy"; 1116 #mbox-cells = <1>; 1117 reg-names = "target_data", "rt", "scfg"; 1118 reg = <0x00 0x32c00000 0x00 0x100000>, 1119 <0x00 0x32400000 0x00 0x100000>, 1120 <0x00 0x32800000 0x00 0x100000>; 1121 interrupt-names = "rx_011"; 1122 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1123 }; 1124 1125 hwspinlock: hwlock@30e00000 { 1126 compatible = "ti,am654-hwspinlock"; 1127 reg = <0x00 0x30e00000 0x00 0x1000>; 1128 #hwlock-cells = <1>; 1129 }; 1130 1131 mailbox0_cluster0: mailbox@31f80000 { 1132 compatible = "ti,am654-mailbox"; 1133 reg = <0x00 0x31f80000 0x00 0x200>; 1134 #mbox-cells = <1>; 1135 ti,mbox-num-users = <4>; 1136 ti,mbox-num-fifos = <16>; 1137 interrupt-parent = <&main_navss_intr>; 1138 status = "disabled"; 1139 }; 1140 1141 mailbox0_cluster1: mailbox@31f81000 { 1142 compatible = "ti,am654-mailbox"; 1143 reg = <0x00 0x31f81000 0x00 0x200>; 1144 #mbox-cells = <1>; 1145 ti,mbox-num-users = <4>; 1146 ti,mbox-num-fifos = <16>; 1147 interrupt-parent = <&main_navss_intr>; 1148 status = "disabled"; 1149 }; 1150 1151 mailbox0_cluster2: mailbox@31f82000 { 1152 compatible = "ti,am654-mailbox"; 1153 reg = <0x00 0x31f82000 0x00 0x200>; 1154 #mbox-cells = <1>; 1155 ti,mbox-num-users = <4>; 1156 ti,mbox-num-fifos = <16>; 1157 interrupt-parent = <&main_navss_intr>; 1158 status = "disabled"; 1159 }; 1160 1161 mailbox0_cluster3: mailbox@31f83000 { 1162 compatible = "ti,am654-mailbox"; 1163 reg = <0x00 0x31f83000 0x00 0x200>; 1164 #mbox-cells = <1>; 1165 ti,mbox-num-users = <4>; 1166 ti,mbox-num-fifos = <16>; 1167 interrupt-parent = <&main_navss_intr>; 1168 status = "disabled"; 1169 }; 1170 1171 mailbox0_cluster4: mailbox@31f84000 { 1172 compatible = "ti,am654-mailbox"; 1173 reg = <0x00 0x31f84000 0x00 0x200>; 1174 #mbox-cells = <1>; 1175 ti,mbox-num-users = <4>; 1176 ti,mbox-num-fifos = <16>; 1177 interrupt-parent = <&main_navss_intr>; 1178 status = "disabled"; 1179 }; 1180 1181 mailbox0_cluster5: mailbox@31f85000 { 1182 compatible = "ti,am654-mailbox"; 1183 reg = <0x00 0x31f85000 0x00 0x200>; 1184 #mbox-cells = <1>; 1185 ti,mbox-num-users = <4>; 1186 ti,mbox-num-fifos = <16>; 1187 interrupt-parent = <&main_navss_intr>; 1188 status = "disabled"; 1189 }; 1190 1191 mailbox0_cluster6: mailbox@31f86000 { 1192 compatible = "ti,am654-mailbox"; 1193 reg = <0x00 0x31f86000 0x00 0x200>; 1194 #mbox-cells = <1>; 1195 ti,mbox-num-users = <4>; 1196 ti,mbox-num-fifos = <16>; 1197 interrupt-parent = <&main_navss_intr>; 1198 status = "disabled"; 1199 }; 1200 1201 mailbox0_cluster7: mailbox@31f87000 { 1202 compatible = "ti,am654-mailbox"; 1203 reg = <0x00 0x31f87000 0x00 0x200>; 1204 #mbox-cells = <1>; 1205 ti,mbox-num-users = <4>; 1206 ti,mbox-num-fifos = <16>; 1207 interrupt-parent = <&main_navss_intr>; 1208 status = "disabled"; 1209 }; 1210 1211 mailbox0_cluster8: mailbox@31f88000 { 1212 compatible = "ti,am654-mailbox"; 1213 reg = <0x00 0x31f88000 0x00 0x200>; 1214 #mbox-cells = <1>; 1215 ti,mbox-num-users = <4>; 1216 ti,mbox-num-fifos = <16>; 1217 interrupt-parent = <&main_navss_intr>; 1218 status = "disabled"; 1219 }; 1220 1221 mailbox0_cluster9: mailbox@31f89000 { 1222 compatible = "ti,am654-mailbox"; 1223 reg = <0x00 0x31f89000 0x00 0x200>; 1224 #mbox-cells = <1>; 1225 ti,mbox-num-users = <4>; 1226 ti,mbox-num-fifos = <16>; 1227 interrupt-parent = <&main_navss_intr>; 1228 status = "disabled"; 1229 }; 1230 1231 mailbox0_cluster10: mailbox@31f8a000 { 1232 compatible = "ti,am654-mailbox"; 1233 reg = <0x00 0x31f8a000 0x00 0x200>; 1234 #mbox-cells = <1>; 1235 ti,mbox-num-users = <4>; 1236 ti,mbox-num-fifos = <16>; 1237 interrupt-parent = <&main_navss_intr>; 1238 status = "disabled"; 1239 }; 1240 1241 mailbox0_cluster11: mailbox@31f8b000 { 1242 compatible = "ti,am654-mailbox"; 1243 reg = <0x00 0x31f8b000 0x00 0x200>; 1244 #mbox-cells = <1>; 1245 ti,mbox-num-users = <4>; 1246 ti,mbox-num-fifos = <16>; 1247 interrupt-parent = <&main_navss_intr>; 1248 status = "disabled"; 1249 }; 1250 1251 mailbox1_cluster0: mailbox@31f90000 { 1252 compatible = "ti,am654-mailbox"; 1253 reg = <0x00 0x31f90000 0x00 0x200>; 1254 #mbox-cells = <1>; 1255 ti,mbox-num-users = <4>; 1256 ti,mbox-num-fifos = <16>; 1257 interrupt-parent = <&main_navss_intr>; 1258 status = "disabled"; 1259 }; 1260 1261 mailbox1_cluster1: mailbox@31f91000 { 1262 compatible = "ti,am654-mailbox"; 1263 reg = <0x00 0x31f91000 0x00 0x200>; 1264 #mbox-cells = <1>; 1265 ti,mbox-num-users = <4>; 1266 ti,mbox-num-fifos = <16>; 1267 interrupt-parent = <&main_navss_intr>; 1268 status = "disabled"; 1269 }; 1270 1271 mailbox1_cluster2: mailbox@31f92000 { 1272 compatible = "ti,am654-mailbox"; 1273 reg = <0x00 0x31f92000 0x00 0x200>; 1274 #mbox-cells = <1>; 1275 ti,mbox-num-users = <4>; 1276 ti,mbox-num-fifos = <16>; 1277 interrupt-parent = <&main_navss_intr>; 1278 status = "disabled"; 1279 }; 1280 1281 mailbox1_cluster3: mailbox@31f93000 { 1282 compatible = "ti,am654-mailbox"; 1283 reg = <0x00 0x31f93000 0x00 0x200>; 1284 #mbox-cells = <1>; 1285 ti,mbox-num-users = <4>; 1286 ti,mbox-num-fifos = <16>; 1287 interrupt-parent = <&main_navss_intr>; 1288 status = "disabled"; 1289 }; 1290 1291 mailbox1_cluster4: mailbox@31f94000 { 1292 compatible = "ti,am654-mailbox"; 1293 reg = <0x00 0x31f94000 0x00 0x200>; 1294 #mbox-cells = <1>; 1295 ti,mbox-num-users = <4>; 1296 ti,mbox-num-fifos = <16>; 1297 interrupt-parent = <&main_navss_intr>; 1298 status = "disabled"; 1299 }; 1300 1301 mailbox1_cluster5: mailbox@31f95000 { 1302 compatible = "ti,am654-mailbox"; 1303 reg = <0x00 0x31f95000 0x00 0x200>; 1304 #mbox-cells = <1>; 1305 ti,mbox-num-users = <4>; 1306 ti,mbox-num-fifos = <16>; 1307 interrupt-parent = <&main_navss_intr>; 1308 status = "disabled"; 1309 }; 1310 1311 mailbox1_cluster6: mailbox@31f96000 { 1312 compatible = "ti,am654-mailbox"; 1313 reg = <0x00 0x31f96000 0x00 0x200>; 1314 #mbox-cells = <1>; 1315 ti,mbox-num-users = <4>; 1316 ti,mbox-num-fifos = <16>; 1317 interrupt-parent = <&main_navss_intr>; 1318 status = "disabled"; 1319 }; 1320 1321 mailbox1_cluster7: mailbox@31f97000 { 1322 compatible = "ti,am654-mailbox"; 1323 reg = <0x00 0x31f97000 0x00 0x200>; 1324 #mbox-cells = <1>; 1325 ti,mbox-num-users = <4>; 1326 ti,mbox-num-fifos = <16>; 1327 interrupt-parent = <&main_navss_intr>; 1328 status = "disabled"; 1329 }; 1330 1331 mailbox1_cluster8: mailbox@31f98000 { 1332 compatible = "ti,am654-mailbox"; 1333 reg = <0x00 0x31f98000 0x00 0x200>; 1334 #mbox-cells = <1>; 1335 ti,mbox-num-users = <4>; 1336 ti,mbox-num-fifos = <16>; 1337 interrupt-parent = <&main_navss_intr>; 1338 status = "disabled"; 1339 }; 1340 1341 mailbox1_cluster9: mailbox@31f99000 { 1342 compatible = "ti,am654-mailbox"; 1343 reg = <0x00 0x31f99000 0x00 0x200>; 1344 #mbox-cells = <1>; 1345 ti,mbox-num-users = <4>; 1346 ti,mbox-num-fifos = <16>; 1347 interrupt-parent = <&main_navss_intr>; 1348 status = "disabled"; 1349 }; 1350 1351 mailbox1_cluster10: mailbox@31f9a000 { 1352 compatible = "ti,am654-mailbox"; 1353 reg = <0x00 0x31f9a000 0x00 0x200>; 1354 #mbox-cells = <1>; 1355 ti,mbox-num-users = <4>; 1356 ti,mbox-num-fifos = <16>; 1357 interrupt-parent = <&main_navss_intr>; 1358 status = "disabled"; 1359 }; 1360 1361 mailbox1_cluster11: mailbox@31f9b000 { 1362 compatible = "ti,am654-mailbox"; 1363 reg = <0x00 0x31f9b000 0x00 0x200>; 1364 #mbox-cells = <1>; 1365 ti,mbox-num-users = <4>; 1366 ti,mbox-num-fifos = <16>; 1367 interrupt-parent = <&main_navss_intr>; 1368 status = "disabled"; 1369 }; 1370 1371 main_ringacc: ringacc@3c000000 { 1372 compatible = "ti,am654-navss-ringacc"; 1373 reg = <0x00 0x3c000000 0x00 0x400000>, 1374 <0x00 0x38000000 0x00 0x400000>, 1375 <0x00 0x31120000 0x00 0x100>, 1376 <0x00 0x33000000 0x00 0x40000>, 1377 <0x00 0x31080000 0x00 0x40000>; 1378 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1379 ti,num-rings = <1024>; 1380 ti,sci-rm-range-gp-rings = <0x1>; 1381 ti,sci = <&sms>; 1382 ti,sci-dev-id = <315>; 1383 msi-parent = <&main_udmass_inta>; 1384 }; 1385 1386 main_udmap: dma-controller@31150000 { 1387 compatible = "ti,j721e-navss-main-udmap"; 1388 reg = <0x00 0x31150000 0x00 0x100>, 1389 <0x00 0x34000000 0x00 0x80000>, 1390 <0x00 0x35000000 0x00 0x200000>, 1391 <0x00 0x30b00000 0x00 0x20000>, 1392 <0x00 0x30c00000 0x00 0x8000>, 1393 <0x00 0x30d00000 0x00 0x4000>; 1394 reg-names = "gcfg", "rchanrt", "tchanrt", 1395 "tchan", "rchan", "rflow"; 1396 msi-parent = <&main_udmass_inta>; 1397 #dma-cells = <1>; 1398 1399 ti,sci = <&sms>; 1400 ti,sci-dev-id = <319>; 1401 ti,ringacc = <&main_ringacc>; 1402 1403 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1404 <0x0f>, /* TX_HCHAN */ 1405 <0x10>; /* TX_UHCHAN */ 1406 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1407 <0x0b>, /* RX_HCHAN */ 1408 <0x0c>; /* RX_UHCHAN */ 1409 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1410 }; 1411 1412 main_bcdma_csi: dma-controller@311a0000 { 1413 compatible = "ti,j721s2-dmss-bcdma-csi"; 1414 reg = <0x00 0x311a0000 0x00 0x100>, 1415 <0x00 0x35d00000 0x00 0x20000>, 1416 <0x00 0x35c00000 0x00 0x10000>, 1417 <0x00 0x35e00000 0x00 0x80000>; 1418 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1419 msi-parent = <&main_udmass_inta>; 1420 #dma-cells = <3>; 1421 ti,sci = <&sms>; 1422 ti,sci-dev-id = <281>; 1423 ti,sci-rm-range-rchan = <0x21>; 1424 ti,sci-rm-range-tchan = <0x22>; 1425 }; 1426 1427 cpts@310d0000 { 1428 compatible = "ti,j721e-cpts"; 1429 reg = <0x00 0x310d0000 0x00 0x400>; 1430 reg-names = "cpts"; 1431 clocks = <&k3_clks 282 0>; 1432 clock-names = "cpts"; 1433 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1434 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1435 interrupts-extended = <&main_navss_intr 391>; 1436 interrupt-names = "cpts"; 1437 ti,cpts-periodic-outputs = <6>; 1438 ti,cpts-ext-ts-inputs = <8>; 1439 }; 1440 }; 1441 1442 main_mcan0: can@2701000 { 1443 compatible = "bosch,m_can"; 1444 reg = <0x00 0x02701000 0x00 0x200>, 1445 <0x00 0x02708000 0x00 0x8000>; 1446 reg-names = "m_can", "message_ram"; 1447 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1448 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1449 clock-names = "hclk", "cclk"; 1450 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1452 interrupt-names = "int0", "int1"; 1453 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1454 status = "disabled"; 1455 }; 1456 1457 main_mcan1: can@2711000 { 1458 compatible = "bosch,m_can"; 1459 reg = <0x00 0x02711000 0x00 0x200>, 1460 <0x00 0x02718000 0x00 0x8000>; 1461 reg-names = "m_can", "message_ram"; 1462 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1463 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1464 clock-names = "hclk", "cclk"; 1465 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1467 interrupt-names = "int0", "int1"; 1468 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1469 status = "disabled"; 1470 }; 1471 1472 main_mcan2: can@2721000 { 1473 compatible = "bosch,m_can"; 1474 reg = <0x00 0x02721000 0x00 0x200>, 1475 <0x00 0x02728000 0x00 0x8000>; 1476 reg-names = "m_can", "message_ram"; 1477 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1478 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1479 clock-names = "hclk", "cclk"; 1480 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1482 interrupt-names = "int0", "int1"; 1483 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1484 status = "disabled"; 1485 }; 1486 1487 main_mcan3: can@2731000 { 1488 compatible = "bosch,m_can"; 1489 reg = <0x00 0x02731000 0x00 0x200>, 1490 <0x00 0x02738000 0x00 0x8000>; 1491 reg-names = "m_can", "message_ram"; 1492 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1493 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1494 clock-names = "hclk", "cclk"; 1495 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1497 interrupt-names = "int0", "int1"; 1498 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1499 status = "disabled"; 1500 }; 1501 1502 main_mcan4: can@2741000 { 1503 compatible = "bosch,m_can"; 1504 reg = <0x00 0x02741000 0x00 0x200>, 1505 <0x00 0x02748000 0x00 0x8000>; 1506 reg-names = "m_can", "message_ram"; 1507 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1508 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1509 clock-names = "hclk", "cclk"; 1510 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1512 interrupt-names = "int0", "int1"; 1513 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1514 status = "disabled"; 1515 }; 1516 1517 main_mcan5: can@2751000 { 1518 compatible = "bosch,m_can"; 1519 reg = <0x00 0x02751000 0x00 0x200>, 1520 <0x00 0x02758000 0x00 0x8000>; 1521 reg-names = "m_can", "message_ram"; 1522 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1523 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1524 clock-names = "hclk", "cclk"; 1525 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1527 interrupt-names = "int0", "int1"; 1528 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1529 status = "disabled"; 1530 }; 1531 1532 main_mcan6: can@2761000 { 1533 compatible = "bosch,m_can"; 1534 reg = <0x00 0x02761000 0x00 0x200>, 1535 <0x00 0x02768000 0x00 0x8000>; 1536 reg-names = "m_can", "message_ram"; 1537 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1538 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1539 clock-names = "hclk", "cclk"; 1540 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1542 interrupt-names = "int0", "int1"; 1543 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1544 status = "disabled"; 1545 }; 1546 1547 main_mcan7: can@2771000 { 1548 compatible = "bosch,m_can"; 1549 reg = <0x00 0x02771000 0x00 0x200>, 1550 <0x00 0x02778000 0x00 0x8000>; 1551 reg-names = "m_can", "message_ram"; 1552 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1553 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1554 clock-names = "hclk", "cclk"; 1555 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1557 interrupt-names = "int0", "int1"; 1558 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1559 status = "disabled"; 1560 }; 1561 1562 main_mcan8: can@2781000 { 1563 compatible = "bosch,m_can"; 1564 reg = <0x00 0x02781000 0x00 0x200>, 1565 <0x00 0x02788000 0x00 0x8000>; 1566 reg-names = "m_can", "message_ram"; 1567 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1568 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1569 clock-names = "hclk", "cclk"; 1570 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1572 interrupt-names = "int0", "int1"; 1573 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1574 status = "disabled"; 1575 }; 1576 1577 main_mcan9: can@2791000 { 1578 compatible = "bosch,m_can"; 1579 reg = <0x00 0x02791000 0x00 0x200>, 1580 <0x00 0x02798000 0x00 0x8000>; 1581 reg-names = "m_can", "message_ram"; 1582 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1583 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1584 clock-names = "hclk", "cclk"; 1585 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1587 interrupt-names = "int0", "int1"; 1588 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1589 status = "disabled"; 1590 }; 1591 1592 main_mcan10: can@27a1000 { 1593 compatible = "bosch,m_can"; 1594 reg = <0x00 0x027a1000 0x00 0x200>, 1595 <0x00 0x027a8000 0x00 0x8000>; 1596 reg-names = "m_can", "message_ram"; 1597 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1598 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1599 clock-names = "hclk", "cclk"; 1600 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1602 interrupt-names = "int0", "int1"; 1603 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1604 status = "disabled"; 1605 }; 1606 1607 main_mcan11: can@27b1000 { 1608 compatible = "bosch,m_can"; 1609 reg = <0x00 0x027b1000 0x00 0x200>, 1610 <0x00 0x027b8000 0x00 0x8000>; 1611 reg-names = "m_can", "message_ram"; 1612 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1613 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1614 clock-names = "hclk", "cclk"; 1615 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1617 interrupt-names = "int0", "int1"; 1618 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1619 status = "disabled"; 1620 }; 1621 1622 main_mcan12: can@27c1000 { 1623 compatible = "bosch,m_can"; 1624 reg = <0x00 0x027c1000 0x00 0x200>, 1625 <0x00 0x027c8000 0x00 0x8000>; 1626 reg-names = "m_can", "message_ram"; 1627 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1628 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1629 clock-names = "hclk", "cclk"; 1630 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1632 interrupt-names = "int0", "int1"; 1633 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1634 status = "disabled"; 1635 }; 1636 1637 main_mcan13: can@27d1000 { 1638 compatible = "bosch,m_can"; 1639 reg = <0x00 0x027d1000 0x00 0x200>, 1640 <0x00 0x027d8000 0x00 0x8000>; 1641 reg-names = "m_can", "message_ram"; 1642 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1643 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1644 clock-names = "hclk", "cclk"; 1645 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1647 interrupt-names = "int0", "int1"; 1648 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1649 status = "disabled"; 1650 }; 1651 1652 main_mcan14: can@2681000 { 1653 compatible = "bosch,m_can"; 1654 reg = <0x00 0x02681000 0x00 0x200>, 1655 <0x00 0x02688000 0x00 0x8000>; 1656 reg-names = "m_can", "message_ram"; 1657 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1658 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1659 clock-names = "hclk", "cclk"; 1660 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1662 interrupt-names = "int0", "int1"; 1663 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1664 status = "disabled"; 1665 }; 1666 1667 main_mcan15: can@2691000 { 1668 compatible = "bosch,m_can"; 1669 reg = <0x00 0x02691000 0x00 0x200>, 1670 <0x00 0x02698000 0x00 0x8000>; 1671 reg-names = "m_can", "message_ram"; 1672 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1673 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 1674 clock-names = "hclk", "cclk"; 1675 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1677 interrupt-names = "int0", "int1"; 1678 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1679 status = "disabled"; 1680 }; 1681 1682 main_mcan16: can@26a1000 { 1683 compatible = "bosch,m_can"; 1684 reg = <0x00 0x026a1000 0x00 0x200>, 1685 <0x00 0x026a8000 0x00 0x8000>; 1686 reg-names = "m_can", "message_ram"; 1687 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 1688 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 1689 clock-names = "hclk", "cclk"; 1690 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1692 interrupt-names = "int0", "int1"; 1693 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1694 status = "disabled"; 1695 }; 1696 1697 main_mcan17: can@26b1000 { 1698 compatible = "bosch,m_can"; 1699 reg = <0x00 0x026b1000 0x00 0x200>, 1700 <0x00 0x026b8000 0x00 0x8000>; 1701 reg-names = "m_can", "message_ram"; 1702 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 1703 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 1704 clock-names = "hclk", "cclk"; 1705 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1707 interrupt-names = "int0", "int1"; 1708 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1709 status = "disabled"; 1710 }; 1711 1712 main_spi0: spi@2100000 { 1713 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1714 reg = <0x00 0x02100000 0x00 0x400>; 1715 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 1719 clocks = <&k3_clks 376 1>; 1720 status = "disabled"; 1721 }; 1722 1723 main_spi1: spi@2110000 { 1724 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1725 reg = <0x00 0x02110000 0x00 0x400>; 1726 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 1730 clocks = <&k3_clks 377 1>; 1731 status = "disabled"; 1732 }; 1733 1734 main_spi2: spi@2120000 { 1735 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1736 reg = <0x00 0x02120000 0x00 0x400>; 1737 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 1741 clocks = <&k3_clks 378 1>; 1742 status = "disabled"; 1743 }; 1744 1745 main_spi3: spi@2130000 { 1746 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1747 reg = <0x00 0x02130000 0x00 0x400>; 1748 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 1752 clocks = <&k3_clks 379 1>; 1753 status = "disabled"; 1754 }; 1755 1756 main_spi4: spi@2140000 { 1757 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1758 reg = <0x00 0x02140000 0x00 0x400>; 1759 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 1763 clocks = <&k3_clks 380 1>; 1764 status = "disabled"; 1765 }; 1766 1767 main_spi5: spi@2150000 { 1768 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1769 reg = <0x00 0x02150000 0x00 0x400>; 1770 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 1774 clocks = <&k3_clks 381 1>; 1775 status = "disabled"; 1776 }; 1777 1778 main_spi6: spi@2160000 { 1779 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1780 reg = <0x00 0x02160000 0x00 0x400>; 1781 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 1785 clocks = <&k3_clks 382 1>; 1786 status = "disabled"; 1787 }; 1788 1789 main_spi7: spi@2170000 { 1790 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1791 reg = <0x00 0x02170000 0x00 0x400>; 1792 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 1796 clocks = <&k3_clks 383 1>; 1797 status = "disabled"; 1798 }; 1799 1800 ufs_wrapper: ufs-wrapper@4e80000 { 1801 compatible = "ti,j721e-ufs"; 1802 reg = <0x00 0x4e80000 0x00 0x100>; 1803 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 1804 clocks = <&k3_clks 387 3>; 1805 assigned-clocks = <&k3_clks 387 3>; 1806 assigned-clock-parents = <&k3_clks 387 6>; 1807 ranges; 1808 #address-cells = <2>; 1809 #size-cells = <2>; 1810 status = "disabled"; 1811 1812 ufs@4e84000 { 1813 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1814 reg = <0x00 0x4e84000 0x00 0x10000>; 1815 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1816 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 1817 <19200000 19200000>; 1818 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 1819 clock-names = "core_clk", "phy_clk", "ref_clk"; 1820 dma-coherent; 1821 }; 1822 }; 1823 1824 main_r5fss0: r5fss@5c00000 { 1825 compatible = "ti,j721s2-r5fss"; 1826 ti,cluster-mode = <1>; 1827 #address-cells = <1>; 1828 #size-cells = <1>; 1829 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1830 <0x5d00000 0x00 0x5d00000 0x20000>; 1831 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 1832 1833 main_r5fss0_core0: r5f@5c00000 { 1834 compatible = "ti,j721s2-r5f"; 1835 reg = <0x5c00000 0x00010000>, 1836 <0x5c10000 0x00010000>; 1837 reg-names = "atcm", "btcm"; 1838 ti,sci = <&sms>; 1839 ti,sci-dev-id = <339>; 1840 ti,sci-proc-ids = <0x06 0xff>; 1841 resets = <&k3_reset 339 1>; 1842 firmware-name = "j784s4-main-r5f0_0-fw"; 1843 ti,atcm-enable = <1>; 1844 ti,btcm-enable = <1>; 1845 ti,loczrama = <1>; 1846 }; 1847 1848 main_r5fss0_core1: r5f@5d00000 { 1849 compatible = "ti,j721s2-r5f"; 1850 reg = <0x5d00000 0x00010000>, 1851 <0x5d10000 0x00010000>; 1852 reg-names = "atcm", "btcm"; 1853 ti,sci = <&sms>; 1854 ti,sci-dev-id = <340>; 1855 ti,sci-proc-ids = <0x07 0xff>; 1856 resets = <&k3_reset 340 1>; 1857 firmware-name = "j784s4-main-r5f0_1-fw"; 1858 ti,atcm-enable = <1>; 1859 ti,btcm-enable = <1>; 1860 ti,loczrama = <1>; 1861 }; 1862 }; 1863 1864 main_r5fss1: r5fss@5e00000 { 1865 compatible = "ti,j721s2-r5fss"; 1866 ti,cluster-mode = <1>; 1867 #address-cells = <1>; 1868 #size-cells = <1>; 1869 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1870 <0x5f00000 0x00 0x5f00000 0x20000>; 1871 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 1872 1873 main_r5fss1_core0: r5f@5e00000 { 1874 compatible = "ti,j721s2-r5f"; 1875 reg = <0x5e00000 0x00010000>, 1876 <0x5e10000 0x00010000>; 1877 reg-names = "atcm", "btcm"; 1878 ti,sci = <&sms>; 1879 ti,sci-dev-id = <341>; 1880 ti,sci-proc-ids = <0x08 0xff>; 1881 resets = <&k3_reset 341 1>; 1882 firmware-name = "j784s4-main-r5f1_0-fw"; 1883 ti,atcm-enable = <1>; 1884 ti,btcm-enable = <1>; 1885 ti,loczrama = <1>; 1886 }; 1887 1888 main_r5fss1_core1: r5f@5f00000 { 1889 compatible = "ti,j721s2-r5f"; 1890 reg = <0x5f00000 0x00010000>, 1891 <0x5f10000 0x00010000>; 1892 reg-names = "atcm", "btcm"; 1893 ti,sci = <&sms>; 1894 ti,sci-dev-id = <342>; 1895 ti,sci-proc-ids = <0x09 0xff>; 1896 resets = <&k3_reset 342 1>; 1897 firmware-name = "j784s4-main-r5f1_1-fw"; 1898 ti,atcm-enable = <1>; 1899 ti,btcm-enable = <1>; 1900 ti,loczrama = <1>; 1901 }; 1902 }; 1903 1904 main_r5fss2: r5fss@5900000 { 1905 compatible = "ti,j721s2-r5fss"; 1906 ti,cluster-mode = <1>; 1907 #address-cells = <1>; 1908 #size-cells = <1>; 1909 ranges = <0x5900000 0x00 0x5900000 0x20000>, 1910 <0x5a00000 0x00 0x5a00000 0x20000>; 1911 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 1912 1913 main_r5fss2_core0: r5f@5900000 { 1914 compatible = "ti,j721s2-r5f"; 1915 reg = <0x5900000 0x00010000>, 1916 <0x5910000 0x00010000>; 1917 reg-names = "atcm", "btcm"; 1918 ti,sci = <&sms>; 1919 ti,sci-dev-id = <343>; 1920 ti,sci-proc-ids = <0x0a 0xff>; 1921 resets = <&k3_reset 343 1>; 1922 firmware-name = "j784s4-main-r5f2_0-fw"; 1923 ti,atcm-enable = <1>; 1924 ti,btcm-enable = <1>; 1925 ti,loczrama = <1>; 1926 }; 1927 1928 main_r5fss2_core1: r5f@5a00000 { 1929 compatible = "ti,j721s2-r5f"; 1930 reg = <0x5a00000 0x00010000>, 1931 <0x5a10000 0x00010000>; 1932 reg-names = "atcm", "btcm"; 1933 ti,sci = <&sms>; 1934 ti,sci-dev-id = <344>; 1935 ti,sci-proc-ids = <0x0b 0xff>; 1936 resets = <&k3_reset 344 1>; 1937 firmware-name = "j784s4-main-r5f2_1-fw"; 1938 ti,atcm-enable = <1>; 1939 ti,btcm-enable = <1>; 1940 ti,loczrama = <1>; 1941 }; 1942 }; 1943 1944 c71_0: dsp@64800000 { 1945 compatible = "ti,j721s2-c71-dsp"; 1946 reg = <0x00 0x64800000 0x00 0x00080000>, 1947 <0x00 0x64e00000 0x00 0x0000c000>; 1948 reg-names = "l2sram", "l1dram"; 1949 ti,sci = <&sms>; 1950 ti,sci-dev-id = <30>; 1951 ti,sci-proc-ids = <0x30 0xff>; 1952 resets = <&k3_reset 30 1>; 1953 firmware-name = "j784s4-c71_0-fw"; 1954 status = "disabled"; 1955 }; 1956 1957 c71_1: dsp@65800000 { 1958 compatible = "ti,j721s2-c71-dsp"; 1959 reg = <0x00 0x65800000 0x00 0x00080000>, 1960 <0x00 0x65e00000 0x00 0x0000c000>; 1961 reg-names = "l2sram", "l1dram"; 1962 ti,sci = <&sms>; 1963 ti,sci-dev-id = <33>; 1964 ti,sci-proc-ids = <0x31 0xff>; 1965 resets = <&k3_reset 33 1>; 1966 firmware-name = "j784s4-c71_1-fw"; 1967 status = "disabled"; 1968 }; 1969 1970 c71_2: dsp@66800000 { 1971 compatible = "ti,j721s2-c71-dsp"; 1972 reg = <0x00 0x66800000 0x00 0x00080000>, 1973 <0x00 0x66e00000 0x00 0x0000c000>; 1974 reg-names = "l2sram", "l1dram"; 1975 ti,sci = <&sms>; 1976 ti,sci-dev-id = <37>; 1977 ti,sci-proc-ids = <0x32 0xff>; 1978 resets = <&k3_reset 37 1>; 1979 firmware-name = "j784s4-c71_2-fw"; 1980 status = "disabled"; 1981 }; 1982 1983 c71_3: dsp@67800000 { 1984 compatible = "ti,j721s2-c71-dsp"; 1985 reg = <0x00 0x67800000 0x00 0x00080000>, 1986 <0x00 0x67e00000 0x00 0x0000c000>; 1987 reg-names = "l2sram", "l1dram"; 1988 ti,sci = <&sms>; 1989 ti,sci-dev-id = <40>; 1990 ti,sci-proc-ids = <0x33 0xff>; 1991 resets = <&k3_reset 40 1>; 1992 firmware-name = "j784s4-c71_3-fw"; 1993 status = "disabled"; 1994 }; 1995 1996 main_esm: esm@700000 { 1997 compatible = "ti,j721e-esm"; 1998 reg = <0x00 0x700000 0x00 0x1000>; 1999 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 2000 <695>; 2001 bootph-pre-ram; 2002 }; 2003 2004 watchdog0: watchdog@2200000 { 2005 compatible = "ti,j7-rti-wdt"; 2006 reg = <0x00 0x2200000 0x00 0x100>; 2007 clocks = <&k3_clks 348 1>; 2008 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 2009 assigned-clocks = <&k3_clks 348 0>; 2010 assigned-clock-parents = <&k3_clks 348 4>; 2011 }; 2012 2013 watchdog1: watchdog@2210000 { 2014 compatible = "ti,j7-rti-wdt"; 2015 reg = <0x00 0x2210000 0x00 0x100>; 2016 clocks = <&k3_clks 349 1>; 2017 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 2018 assigned-clocks = <&k3_clks 349 0>; 2019 assigned-clock-parents = <&k3_clks 349 4>; 2020 }; 2021 2022 watchdog2: watchdog@2220000 { 2023 compatible = "ti,j7-rti-wdt"; 2024 reg = <0x00 0x2220000 0x00 0x100>; 2025 clocks = <&k3_clks 350 1>; 2026 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 2027 assigned-clocks = <&k3_clks 350 0>; 2028 assigned-clock-parents = <&k3_clks 350 4>; 2029 }; 2030 2031 watchdog3: watchdog@2230000 { 2032 compatible = "ti,j7-rti-wdt"; 2033 reg = <0x00 0x2230000 0x00 0x100>; 2034 clocks = <&k3_clks 351 1>; 2035 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 2036 assigned-clocks = <&k3_clks 351 0>; 2037 assigned-clock-parents = <&k3_clks 351 4>; 2038 }; 2039 2040 watchdog4: watchdog@2240000 { 2041 compatible = "ti,j7-rti-wdt"; 2042 reg = <0x00 0x2240000 0x00 0x100>; 2043 clocks = <&k3_clks 352 1>; 2044 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 2045 assigned-clocks = <&k3_clks 352 0>; 2046 assigned-clock-parents = <&k3_clks 352 4>; 2047 }; 2048 2049 watchdog5: watchdog@2250000 { 2050 compatible = "ti,j7-rti-wdt"; 2051 reg = <0x00 0x2250000 0x00 0x100>; 2052 clocks = <&k3_clks 353 1>; 2053 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 2054 assigned-clocks = <&k3_clks 353 0>; 2055 assigned-clock-parents = <&k3_clks 353 4>; 2056 }; 2057 2058 watchdog6: watchdog@2260000 { 2059 compatible = "ti,j7-rti-wdt"; 2060 reg = <0x00 0x2260000 0x00 0x100>; 2061 clocks = <&k3_clks 354 1>; 2062 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 2063 assigned-clocks = <&k3_clks 354 0>; 2064 assigned-clock-parents = <&k3_clks 354 4>; 2065 }; 2066 2067 watchdog7: watchdog@2270000 { 2068 compatible = "ti,j7-rti-wdt"; 2069 reg = <0x00 0x2270000 0x00 0x100>; 2070 clocks = <&k3_clks 355 1>; 2071 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 2072 assigned-clocks = <&k3_clks 355 0>; 2073 assigned-clock-parents = <&k3_clks 355 4>; 2074 }; 2075 2076 /* 2077 * The following RTI instances are coupled with MCU R5Fs, c7x and 2078 * GPU so keeping them reserved as these will be used by their 2079 * respective firmware 2080 */ 2081 watchdog8: watchdog@22f0000 { 2082 compatible = "ti,j7-rti-wdt"; 2083 reg = <0x00 0x22f0000 0x00 0x100>; 2084 clocks = <&k3_clks 360 1>; 2085 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 2086 assigned-clocks = <&k3_clks 360 0>; 2087 assigned-clock-parents = <&k3_clks 360 4>; 2088 /* reserved for GPU */ 2089 status = "reserved"; 2090 }; 2091 2092 watchdog9: watchdog@2300000 { 2093 compatible = "ti,j7-rti-wdt"; 2094 reg = <0x00 0x2300000 0x00 0x100>; 2095 clocks = <&k3_clks 356 1>; 2096 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 2097 assigned-clocks = <&k3_clks 356 0>; 2098 assigned-clock-parents = <&k3_clks 356 4>; 2099 /* reserved for C7X_0 DSP */ 2100 status = "reserved"; 2101 }; 2102 2103 watchdog10: watchdog@2310000 { 2104 compatible = "ti,j7-rti-wdt"; 2105 reg = <0x00 0x2310000 0x00 0x100>; 2106 clocks = <&k3_clks 357 1>; 2107 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 2108 assigned-clocks = <&k3_clks 357 0>; 2109 assigned-clock-parents = <&k3_clks 357 4>; 2110 /* reserved for C7X_1 DSP */ 2111 status = "reserved"; 2112 }; 2113 2114 watchdog11: watchdog@2320000 { 2115 compatible = "ti,j7-rti-wdt"; 2116 reg = <0x00 0x2320000 0x00 0x100>; 2117 clocks = <&k3_clks 358 1>; 2118 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 2119 assigned-clocks = <&k3_clks 358 0>; 2120 assigned-clock-parents = <&k3_clks 358 4>; 2121 /* reserved for C7X_2 DSP */ 2122 status = "reserved"; 2123 }; 2124 2125 watchdog12: watchdog@2330000 { 2126 compatible = "ti,j7-rti-wdt"; 2127 reg = <0x00 0x2330000 0x00 0x100>; 2128 clocks = <&k3_clks 359 1>; 2129 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 2130 assigned-clocks = <&k3_clks 359 0>; 2131 assigned-clock-parents = <&k3_clks 359 4>; 2132 /* reserved for C7X_3 DSP */ 2133 status = "reserved"; 2134 }; 2135 2136 watchdog13: watchdog@23c0000 { 2137 compatible = "ti,j7-rti-wdt"; 2138 reg = <0x00 0x23c0000 0x00 0x100>; 2139 clocks = <&k3_clks 361 1>; 2140 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 2141 assigned-clocks = <&k3_clks 361 0>; 2142 assigned-clock-parents = <&k3_clks 361 4>; 2143 /* reserved for MAIN_R5F0_0 */ 2144 status = "reserved"; 2145 }; 2146 2147 watchdog14: watchdog@23d0000 { 2148 compatible = "ti,j7-rti-wdt"; 2149 reg = <0x00 0x23d0000 0x00 0x100>; 2150 clocks = <&k3_clks 362 1>; 2151 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 2152 assigned-clocks = <&k3_clks 362 0>; 2153 assigned-clock-parents = <&k3_clks 362 4>; 2154 /* reserved for MAIN_R5F0_1 */ 2155 status = "reserved"; 2156 }; 2157 2158 watchdog15: watchdog@23e0000 { 2159 compatible = "ti,j7-rti-wdt"; 2160 reg = <0x00 0x23e0000 0x00 0x100>; 2161 clocks = <&k3_clks 363 1>; 2162 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 2163 assigned-clocks = <&k3_clks 363 0>; 2164 assigned-clock-parents = <&k3_clks 363 4>; 2165 /* reserved for MAIN_R5F1_0 */ 2166 status = "reserved"; 2167 }; 2168 2169 watchdog16: watchdog@23f0000 { 2170 compatible = "ti,j7-rti-wdt"; 2171 reg = <0x00 0x23f0000 0x00 0x100>; 2172 clocks = <&k3_clks 364 1>; 2173 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 2174 assigned-clocks = <&k3_clks 364 0>; 2175 assigned-clock-parents = <&k3_clks 364 4>; 2176 /* reserved for MAIN_R5F1_1 */ 2177 status = "reserved"; 2178 }; 2179 2180 watchdog17: watchdog@2540000 { 2181 compatible = "ti,j7-rti-wdt"; 2182 reg = <0x00 0x2540000 0x00 0x100>; 2183 clocks = <&k3_clks 365 1>; 2184 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 2185 assigned-clocks = <&k3_clks 365 0>; 2186 assigned-clock-parents = <&k3_clks 366 4>; 2187 /* reserved for MAIN_R5F2_0 */ 2188 status = "reserved"; 2189 }; 2190 2191 watchdog18: watchdog@2550000 { 2192 compatible = "ti,j7-rti-wdt"; 2193 reg = <0x00 0x2550000 0x00 0x100>; 2194 clocks = <&k3_clks 366 1>; 2195 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 2196 assigned-clocks = <&k3_clks 366 0>; 2197 assigned-clock-parents = <&k3_clks 366 4>; 2198 /* reserved for MAIN_R5F2_1 */ 2199 status = "reserved"; 2200 }; 2201 2202 mhdp: bridge@a000000 { 2203 compatible = "ti,j721e-mhdp8546"; 2204 reg = <0x0 0xa000000 0x0 0x30a00>, 2205 <0x0 0x4f40000 0x0 0x20>; 2206 reg-names = "mhdptx", "j721e-intg"; 2207 clocks = <&k3_clks 217 11>; 2208 interrupt-parent = <&gic500>; 2209 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2210 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2211 status = "disabled"; 2212 2213 dp0_ports: ports { 2214 #address-cells = <1>; 2215 #size-cells = <0>; 2216 /* Remote-endpoints are on the boards so 2217 * ports are defined in the platform dt file. 2218 */ 2219 }; 2220 }; 2221 2222 dss: dss@4a00000 { 2223 compatible = "ti,j721e-dss"; 2224 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2225 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2226 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2227 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2228 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2229 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2230 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2231 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2232 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2233 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2234 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2235 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2236 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2237 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2238 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2239 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2240 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2241 reg-names = "common_m", "common_s0", 2242 "common_s1", "common_s2", 2243 "vidl1", "vidl2","vid1","vid2", 2244 "ovr1", "ovr2", "ovr3", "ovr4", 2245 "vp1", "vp2", "vp3", "vp4", 2246 "wb"; 2247 clocks = <&k3_clks 218 0>, 2248 <&k3_clks 218 2>, 2249 <&k3_clks 218 5>, 2250 <&k3_clks 218 14>, 2251 <&k3_clks 218 18>; 2252 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2253 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2254 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2258 interrupt-names = "common_m", 2259 "common_s0", 2260 "common_s1", 2261 "common_s2"; 2262 status = "disabled"; 2263 2264 dss_ports: ports { 2265 /* Ports that DSS drives are platform specific 2266 * so they are defined in platform dt file. 2267 */ 2268 }; 2269 }; 2270}; 2271