1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 msmc_ram: sram@70000000 { 25 compatible = "mmio-sram"; 26 reg = <0x00 0x70000000 0x00 0x800000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x00 0x00 0x70000000 0x800000>; 30 31 atf-sram@0 { 32 reg = <0x00 0x20000>; 33 }; 34 35 tifs-sram@1f0000 { 36 reg = <0x1f0000 0x10000>; 37 }; 38 39 l3cache-sram@200000 { 40 reg = <0x200000 0x200000>; 41 }; 42 }; 43 44 scm_conf: bus@100000 { 45 compatible = "simple-bus"; 46 reg = <0x00 0x00100000 0x00 0x1c000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x1c000>; 50 51 serdes_ln_ctrl: mux-controller@4080 { 52 compatible = "reg-mux"; 53 reg = <0x00004080 0x30>; 54 #mux-control-cells = <1>; 55 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 56 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ 57 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 58 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ 59 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 60 <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ 61 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 62 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 63 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 64 <J784S4_SERDES0_LANE3_USB>, 65 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 66 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 67 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 68 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 69 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 70 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 71 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 72 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 73 <J784S4_SERDES4_LANE0_EDP_LANE0>, 74 <J784S4_SERDES4_LANE1_EDP_LANE1>, 75 <J784S4_SERDES4_LANE2_EDP_LANE2>, 76 <J784S4_SERDES4_LANE3_EDP_LANE3>; 77 }; 78 }; 79 80 gic500: interrupt-controller@1800000 { 81 compatible = "arm,gic-v3"; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 #interrupt-cells = <3>; 86 interrupt-controller; 87 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 88 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 89 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 90 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 91 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 92 93 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 94 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 95 96 gic_its: msi-controller@1820000 { 97 compatible = "arm,gic-v3-its"; 98 reg = <0x00 0x01820000 0x00 0x10000>; 99 socionext,synquacer-pre-its = <0x1000000 0x400000>; 100 msi-controller; 101 #msi-cells = <1>; 102 }; 103 }; 104 105 main_gpio_intr: interrupt-controller@a00000 { 106 compatible = "ti,sci-intr"; 107 reg = <0x00 0x00a00000 0x00 0x800>; 108 ti,intr-trigger-type = <1>; 109 interrupt-controller; 110 interrupt-parent = <&gic500>; 111 #interrupt-cells = <1>; 112 ti,sci = <&sms>; 113 ti,sci-dev-id = <10>; 114 ti,interrupt-ranges = <8 392 56>; 115 }; 116 117 main_pmx0: pinctrl@11c000 { 118 compatible = "pinctrl-single"; 119 /* Proxy 0 addressing */ 120 reg = <0x00 0x11c000 0x00 0x120>; 121 #pinctrl-cells = <1>; 122 pinctrl-single,register-width = <32>; 123 pinctrl-single,function-mask = <0xffffffff>; 124 }; 125 126 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 127 main_timerio_input: pinctrl@104200 { 128 compatible = "pinctrl-single"; 129 reg = <0x00 0x104200 0x00 0x50>; 130 #pinctrl-cells = <1>; 131 pinctrl-single,register-width = <32>; 132 pinctrl-single,function-mask = <0x00000007>; 133 }; 134 135 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 136 main_timerio_output: pinctrl@104280 { 137 compatible = "pinctrl-single"; 138 reg = <0x00 0x104280 0x00 0x20>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0x0000001f>; 142 }; 143 144 main_crypto: crypto@4e00000 { 145 compatible = "ti,j721e-sa2ul"; 146 reg = <0x00 0x4e00000 0x00 0x1200>; 147 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 151 152 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 153 <&main_udmap 0x4a41>; 154 dma-names = "tx", "rx1", "rx2"; 155 156 rng: rng@4e10000 { 157 compatible = "inside-secure,safexcel-eip76"; 158 reg = <0x00 0x4e10000 0x00 0x7d>; 159 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 }; 162 163 main_timer0: timer@2400000 { 164 compatible = "ti,am654-timer"; 165 reg = <0x00 0x2400000 0x00 0x400>; 166 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&k3_clks 97 2>; 168 clock-names = "fck"; 169 assigned-clocks = <&k3_clks 97 2>; 170 assigned-clock-parents = <&k3_clks 97 3>; 171 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 172 ti,timer-pwm; 173 }; 174 175 main_timer1: timer@2410000 { 176 compatible = "ti,am654-timer"; 177 reg = <0x00 0x2410000 0x00 0x400>; 178 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&k3_clks 98 2>; 180 clock-names = "fck"; 181 assigned-clocks = <&k3_clks 98 2>; 182 assigned-clock-parents = <&k3_clks 98 3>; 183 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 184 ti,timer-pwm; 185 }; 186 187 main_timer2: timer@2420000 { 188 compatible = "ti,am654-timer"; 189 reg = <0x00 0x2420000 0x00 0x400>; 190 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&k3_clks 99 2>; 192 clock-names = "fck"; 193 assigned-clocks = <&k3_clks 99 2>; 194 assigned-clock-parents = <&k3_clks 99 3>; 195 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 196 ti,timer-pwm; 197 }; 198 199 main_timer3: timer@2430000 { 200 compatible = "ti,am654-timer"; 201 reg = <0x00 0x2430000 0x00 0x400>; 202 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&k3_clks 100 2>; 204 clock-names = "fck"; 205 assigned-clocks = <&k3_clks 100 2>; 206 assigned-clock-parents = <&k3_clks 100 3>; 207 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 208 ti,timer-pwm; 209 }; 210 211 main_timer4: timer@2440000 { 212 compatible = "ti,am654-timer"; 213 reg = <0x00 0x2440000 0x00 0x400>; 214 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&k3_clks 101 2>; 216 clock-names = "fck"; 217 assigned-clocks = <&k3_clks 101 2>; 218 assigned-clock-parents = <&k3_clks 101 3>; 219 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 220 ti,timer-pwm; 221 }; 222 223 main_timer5: timer@2450000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x2450000 0x00 0x400>; 226 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 102 2>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 102 2>; 230 assigned-clock-parents = <&k3_clks 102 3>; 231 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 }; 234 235 main_timer6: timer@2460000 { 236 compatible = "ti,am654-timer"; 237 reg = <0x00 0x2460000 0x00 0x400>; 238 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&k3_clks 103 2>; 240 clock-names = "fck"; 241 assigned-clocks = <&k3_clks 103 2>; 242 assigned-clock-parents = <&k3_clks 103 3>; 243 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 244 ti,timer-pwm; 245 }; 246 247 main_timer7: timer@2470000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x2470000 0x00 0x400>; 250 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 104 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 104 2>; 254 assigned-clock-parents = <&k3_clks 104 3>; 255 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 }; 258 259 main_timer8: timer@2480000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x2480000 0x00 0x400>; 262 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 105 2>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 105 2>; 266 assigned-clock-parents = <&k3_clks 105 3>; 267 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 }; 270 271 main_timer9: timer@2490000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2490000 0x00 0x400>; 274 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 106 2>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 106 2>; 278 assigned-clock-parents = <&k3_clks 106 3>; 279 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 }; 282 283 main_timer10: timer@24a0000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x24a0000 0x00 0x400>; 286 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 107 2>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 107 2>; 290 assigned-clock-parents = <&k3_clks 107 3>; 291 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 }; 294 295 main_timer11: timer@24b0000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x24b0000 0x00 0x400>; 298 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 108 2>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 108 2>; 302 assigned-clock-parents = <&k3_clks 108 3>; 303 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 }; 306 307 main_timer12: timer@24c0000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x24c0000 0x00 0x400>; 310 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 109 2>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 109 2>; 314 assigned-clock-parents = <&k3_clks 109 3>; 315 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer13: timer@24d0000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x24d0000 0x00 0x400>; 322 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 110 2>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 110 2>; 326 assigned-clock-parents = <&k3_clks 110 3>; 327 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_timer14: timer@24e0000 { 332 compatible = "ti,am654-timer"; 333 reg = <0x00 0x24e0000 0x00 0x400>; 334 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&k3_clks 111 2>; 336 clock-names = "fck"; 337 assigned-clocks = <&k3_clks 111 2>; 338 assigned-clock-parents = <&k3_clks 111 3>; 339 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 340 ti,timer-pwm; 341 }; 342 343 main_timer15: timer@24f0000 { 344 compatible = "ti,am654-timer"; 345 reg = <0x00 0x24f0000 0x00 0x400>; 346 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&k3_clks 112 2>; 348 clock-names = "fck"; 349 assigned-clocks = <&k3_clks 112 2>; 350 assigned-clock-parents = <&k3_clks 112 3>; 351 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 352 ti,timer-pwm; 353 }; 354 355 main_timer16: timer@2500000 { 356 compatible = "ti,am654-timer"; 357 reg = <0x00 0x2500000 0x00 0x400>; 358 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 113 2>; 360 clock-names = "fck"; 361 assigned-clocks = <&k3_clks 113 2>; 362 assigned-clock-parents = <&k3_clks 113 3>; 363 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 364 ti,timer-pwm; 365 }; 366 367 main_timer17: timer@2510000 { 368 compatible = "ti,am654-timer"; 369 reg = <0x00 0x2510000 0x00 0x400>; 370 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&k3_clks 114 2>; 372 clock-names = "fck"; 373 assigned-clocks = <&k3_clks 114 2>; 374 assigned-clock-parents = <&k3_clks 114 3>; 375 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 376 ti,timer-pwm; 377 }; 378 379 main_timer18: timer@2520000 { 380 compatible = "ti,am654-timer"; 381 reg = <0x00 0x2520000 0x00 0x400>; 382 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&k3_clks 115 2>; 384 clock-names = "fck"; 385 assigned-clocks = <&k3_clks 115 2>; 386 assigned-clock-parents = <&k3_clks 115 3>; 387 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 388 ti,timer-pwm; 389 }; 390 391 main_timer19: timer@2530000 { 392 compatible = "ti,am654-timer"; 393 reg = <0x00 0x2530000 0x00 0x400>; 394 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&k3_clks 116 2>; 396 clock-names = "fck"; 397 assigned-clocks = <&k3_clks 116 2>; 398 assigned-clock-parents = <&k3_clks 116 3>; 399 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 400 ti,timer-pwm; 401 }; 402 403 main_uart0: serial@2800000 { 404 compatible = "ti,j721e-uart", "ti,am654-uart"; 405 reg = <0x00 0x02800000 0x00 0x200>; 406 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&k3_clks 146 0>; 408 clock-names = "fclk"; 409 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 410 status = "disabled"; 411 }; 412 413 main_uart1: serial@2810000 { 414 compatible = "ti,j721e-uart", "ti,am654-uart"; 415 reg = <0x00 0x02810000 0x00 0x200>; 416 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&k3_clks 388 0>; 418 clock-names = "fclk"; 419 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 420 status = "disabled"; 421 }; 422 423 main_uart2: serial@2820000 { 424 compatible = "ti,j721e-uart", "ti,am654-uart"; 425 reg = <0x00 0x02820000 0x00 0x200>; 426 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&k3_clks 389 0>; 428 clock-names = "fclk"; 429 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 430 status = "disabled"; 431 }; 432 433 main_uart3: serial@2830000 { 434 compatible = "ti,j721e-uart", "ti,am654-uart"; 435 reg = <0x00 0x02830000 0x00 0x200>; 436 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&k3_clks 390 0>; 438 clock-names = "fclk"; 439 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 440 status = "disabled"; 441 }; 442 443 main_uart4: serial@2840000 { 444 compatible = "ti,j721e-uart", "ti,am654-uart"; 445 reg = <0x00 0x02840000 0x00 0x200>; 446 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&k3_clks 391 0>; 448 clock-names = "fclk"; 449 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 450 status = "disabled"; 451 }; 452 453 main_uart5: serial@2850000 { 454 compatible = "ti,j721e-uart", "ti,am654-uart"; 455 reg = <0x00 0x02850000 0x00 0x200>; 456 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&k3_clks 392 0>; 458 clock-names = "fclk"; 459 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 460 status = "disabled"; 461 }; 462 463 main_uart6: serial@2860000 { 464 compatible = "ti,j721e-uart", "ti,am654-uart"; 465 reg = <0x00 0x02860000 0x00 0x200>; 466 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&k3_clks 393 0>; 468 clock-names = "fclk"; 469 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 470 status = "disabled"; 471 }; 472 473 main_uart7: serial@2870000 { 474 compatible = "ti,j721e-uart", "ti,am654-uart"; 475 reg = <0x00 0x02870000 0x00 0x200>; 476 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&k3_clks 394 0>; 478 clock-names = "fclk"; 479 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 480 status = "disabled"; 481 }; 482 483 main_uart8: serial@2880000 { 484 compatible = "ti,j721e-uart", "ti,am654-uart"; 485 reg = <0x00 0x02880000 0x00 0x200>; 486 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&k3_clks 395 0>; 488 clock-names = "fclk"; 489 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 490 status = "disabled"; 491 }; 492 493 main_uart9: serial@2890000 { 494 compatible = "ti,j721e-uart", "ti,am654-uart"; 495 reg = <0x00 0x02890000 0x00 0x200>; 496 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&k3_clks 396 0>; 498 clock-names = "fclk"; 499 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 500 status = "disabled"; 501 }; 502 503 main_gpio0: gpio@600000 { 504 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 505 reg = <0x00 0x00600000 0x00 0x100>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-parent = <&main_gpio_intr>; 509 interrupts = <145>, <146>, <147>, <148>, <149>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 ti,ngpio = <66>; 513 ti,davinci-gpio-unbanked = <0>; 514 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 515 clocks = <&k3_clks 163 0>; 516 clock-names = "gpio"; 517 status = "disabled"; 518 }; 519 520 main_gpio2: gpio@610000 { 521 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 522 reg = <0x00 0x00610000 0x00 0x100>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 interrupt-parent = <&main_gpio_intr>; 526 interrupts = <154>, <155>, <156>, <157>, <158>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 ti,ngpio = <66>; 530 ti,davinci-gpio-unbanked = <0>; 531 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 532 clocks = <&k3_clks 164 0>; 533 clock-names = "gpio"; 534 status = "disabled"; 535 }; 536 537 main_gpio4: gpio@620000 { 538 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 539 reg = <0x00 0x00620000 0x00 0x100>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 interrupt-parent = <&main_gpio_intr>; 543 interrupts = <163>, <164>, <165>, <166>, <167>; 544 interrupt-controller; 545 #interrupt-cells = <2>; 546 ti,ngpio = <66>; 547 ti,davinci-gpio-unbanked = <0>; 548 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 549 clocks = <&k3_clks 165 0>; 550 clock-names = "gpio"; 551 status = "disabled"; 552 }; 553 554 main_gpio6: gpio@630000 { 555 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 556 reg = <0x00 0x00630000 0x00 0x100>; 557 gpio-controller; 558 #gpio-cells = <2>; 559 interrupt-parent = <&main_gpio_intr>; 560 interrupts = <172>, <173>, <174>, <175>, <176>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 ti,ngpio = <66>; 564 ti,davinci-gpio-unbanked = <0>; 565 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 566 clocks = <&k3_clks 166 0>; 567 clock-names = "gpio"; 568 status = "disabled"; 569 }; 570 571 main_i2c0: i2c@2000000 { 572 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 573 reg = <0x00 0x02000000 0x00 0x100>; 574 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 clocks = <&k3_clks 270 2>; 578 clock-names = "fck"; 579 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 580 status = "disabled"; 581 }; 582 583 main_i2c1: i2c@2010000 { 584 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 585 reg = <0x00 0x02010000 0x00 0x100>; 586 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 clocks = <&k3_clks 271 2>; 590 clock-names = "fck"; 591 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 592 status = "disabled"; 593 }; 594 595 main_i2c2: i2c@2020000 { 596 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 597 reg = <0x00 0x02020000 0x00 0x100>; 598 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 clocks = <&k3_clks 272 2>; 602 clock-names = "fck"; 603 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 604 status = "disabled"; 605 }; 606 607 main_i2c3: i2c@2030000 { 608 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 609 reg = <0x00 0x02030000 0x00 0x100>; 610 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 clocks = <&k3_clks 273 2>; 614 clock-names = "fck"; 615 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 616 status = "disabled"; 617 }; 618 619 main_i2c4: i2c@2040000 { 620 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 621 reg = <0x00 0x02040000 0x00 0x100>; 622 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 clocks = <&k3_clks 274 2>; 626 clock-names = "fck"; 627 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 628 status = "disabled"; 629 }; 630 631 main_i2c5: i2c@2050000 { 632 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 633 reg = <0x00 0x02050000 0x00 0x100>; 634 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 clocks = <&k3_clks 275 2>; 638 clock-names = "fck"; 639 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 640 status = "disabled"; 641 }; 642 643 main_i2c6: i2c@2060000 { 644 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 645 reg = <0x00 0x02060000 0x00 0x100>; 646 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 clocks = <&k3_clks 276 2>; 650 clock-names = "fck"; 651 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 652 status = "disabled"; 653 }; 654 655 ti_csi2rx0: ticsi2rx@4500000 { 656 compatible = "ti,j721e-csi2rx-shim"; 657 reg = <0x00 0x04500000 0x00 0x00001000>; 658 ranges; 659 #address-cells = <2>; 660 #size-cells = <2>; 661 dmas = <&main_bcdma_csi 0 0x4940 0>; 662 dma-names = "rx0"; 663 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 664 status = "disabled"; 665 666 cdns_csi2rx0: csi-bridge@4504000 { 667 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 668 reg = <0x00 0x04504000 0x00 0x00001000>; 669 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, 670 <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; 671 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 672 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 673 phys = <&dphy0>; 674 phy-names = "dphy"; 675 676 ports { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 680 csi0_port0: port@0 { 681 reg = <0>; 682 status = "disabled"; 683 }; 684 685 csi0_port1: port@1 { 686 reg = <1>; 687 status = "disabled"; 688 }; 689 690 csi0_port2: port@2 { 691 reg = <2>; 692 status = "disabled"; 693 }; 694 695 csi0_port3: port@3 { 696 reg = <3>; 697 status = "disabled"; 698 }; 699 700 csi0_port4: port@4 { 701 reg = <4>; 702 status = "disabled"; 703 }; 704 }; 705 }; 706 }; 707 708 ti_csi2rx1: ticsi2rx@4510000 { 709 compatible = "ti,j721e-csi2rx-shim"; 710 reg = <0x00 0x04510000 0x00 0x1000>; 711 ranges; 712 #address-cells = <2>; 713 #size-cells = <2>; 714 dmas = <&main_bcdma_csi 0 0x4960 0>; 715 dma-names = "rx0"; 716 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 717 status = "disabled"; 718 719 cdns_csi2rx1: csi-bridge@4514000 { 720 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 721 reg = <0x00 0x04514000 0x00 0x00001000>; 722 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, 723 <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; 724 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 725 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 726 phys = <&dphy1>; 727 phy-names = "dphy"; 728 ports { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 732 csi1_port0: port@0 { 733 reg = <0>; 734 status = "disabled"; 735 }; 736 737 csi1_port1: port@1 { 738 reg = <1>; 739 status = "disabled"; 740 }; 741 742 csi1_port2: port@2 { 743 reg = <2>; 744 status = "disabled"; 745 }; 746 747 csi1_port3: port@3 { 748 reg = <3>; 749 status = "disabled"; 750 }; 751 752 csi1_port4: port@4 { 753 reg = <4>; 754 status = "disabled"; 755 }; 756 }; 757 }; 758 }; 759 760 ti_csi2rx2: ticsi2rx@4520000 { 761 compatible = "ti,j721e-csi2rx-shim"; 762 reg = <0x00 0x04520000 0x00 0x00001000>; 763 ranges; 764 #address-cells = <2>; 765 #size-cells = <2>; 766 dmas = <&main_bcdma_csi 0 0x4980 0>; 767 dma-names = "rx0"; 768 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 769 status = "disabled"; 770 771 cdns_csi2rx2: csi-bridge@4524000 { 772 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 773 reg = <0x00 0x04524000 0x00 0x00001000>; 774 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, 775 <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; 776 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 777 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 778 phys = <&dphy2>; 779 phy-names = "dphy"; 780 781 ports { 782 #address-cells = <1>; 783 #size-cells = <0>; 784 785 csi2_port0: port@0 { 786 reg = <0>; 787 status = "disabled"; 788 }; 789 790 csi2_port1: port@1 { 791 reg = <1>; 792 status = "disabled"; 793 }; 794 795 csi2_port2: port@2 { 796 reg = <2>; 797 status = "disabled"; 798 }; 799 800 csi2_port3: port@3 { 801 reg = <3>; 802 status = "disabled"; 803 }; 804 805 csi2_port4: port@4 { 806 reg = <4>; 807 status = "disabled"; 808 }; 809 }; 810 }; 811 }; 812 813 dphy0: phy@4580000 { 814 compatible = "cdns,dphy-rx"; 815 reg = <0x00 0x04580000 0x00 0x00001100>; 816 #phy-cells = <0>; 817 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; 818 status = "disabled"; 819 }; 820 821 dphy1: phy@4590000 { 822 compatible = "cdns,dphy-rx"; 823 reg = <0x00 0x04590000 0x00 0x00001100>; 824 #phy-cells = <0>; 825 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; 826 status = "disabled"; 827 }; 828 829 dphy2: phy@45a0000 { 830 compatible = "cdns,dphy-rx"; 831 reg = <0x00 0x045a0000 0x00 0x00001100>; 832 #phy-cells = <0>; 833 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 834 status = "disabled"; 835 }; 836 837 vpu0: video-codec@4210000 { 838 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 839 reg = <0x00 0x4210000 0x00 0x10000>; 840 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&k3_clks 241 2>; 842 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 843 }; 844 845 vpu1: video-codec@4220000 { 846 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 847 reg = <0x00 0x4220000 0x00 0x10000>; 848 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&k3_clks 242 2>; 850 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 851 }; 852 853 main_sdhci0: mmc@4f80000 { 854 compatible = "ti,j721e-sdhci-8bit"; 855 reg = <0x00 0x04f80000 0x00 0x1000>, 856 <0x00 0x04f88000 0x00 0x400>; 857 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 858 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 859 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 860 clock-names = "clk_ahb", "clk_xin"; 861 assigned-clocks = <&k3_clks 140 2>; 862 assigned-clock-parents = <&k3_clks 140 3>; 863 bus-width = <8>; 864 ti,otap-del-sel-legacy = <0x0>; 865 ti,otap-del-sel-mmc-hs = <0x0>; 866 ti,otap-del-sel-ddr52 = <0x6>; 867 ti,otap-del-sel-hs200 = <0x8>; 868 ti,otap-del-sel-hs400 = <0x5>; 869 ti,itap-del-sel-legacy = <0x10>; 870 ti,itap-del-sel-mmc-hs = <0xa>; 871 ti,strobe-sel = <0x77>; 872 ti,clkbuf-sel = <0x7>; 873 ti,trm-icp = <0x8>; 874 mmc-ddr-1_8v; 875 mmc-hs200-1_8v; 876 mmc-hs400-1_8v; 877 dma-coherent; 878 status = "disabled"; 879 }; 880 881 main_sdhci1: mmc@4fb0000 { 882 compatible = "ti,j721e-sdhci-4bit"; 883 reg = <0x00 0x04fb0000 0x00 0x1000>, 884 <0x00 0x04fb8000 0x00 0x400>; 885 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 887 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 888 clock-names = "clk_ahb", "clk_xin"; 889 assigned-clocks = <&k3_clks 141 4>; 890 assigned-clock-parents = <&k3_clks 141 5>; 891 bus-width = <4>; 892 ti,otap-del-sel-legacy = <0x0>; 893 ti,otap-del-sel-sd-hs = <0x0>; 894 ti,otap-del-sel-sdr12 = <0xf>; 895 ti,otap-del-sel-sdr25 = <0xf>; 896 ti,otap-del-sel-sdr50 = <0xc>; 897 ti,otap-del-sel-sdr104 = <0x5>; 898 ti,otap-del-sel-ddr50 = <0xc>; 899 ti,itap-del-sel-legacy = <0x0>; 900 ti,itap-del-sel-sd-hs = <0x0>; 901 ti,itap-del-sel-sdr12 = <0x0>; 902 ti,itap-del-sel-sdr25 = <0x0>; 903 ti,itap-del-sel-ddr50 = <0x2>; 904 ti,clkbuf-sel = <0x7>; 905 ti,trm-icp = <0x8>; 906 dma-coherent; 907 status = "disabled"; 908 }; 909 910 serdes_wiz0: wiz@5060000 { 911 compatible = "ti,j784s4-wiz-10g"; 912 #address-cells = <1>; 913 #size-cells = <1>; 914 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 915 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 916 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 917 assigned-clocks = <&k3_clks 404 6>; 918 assigned-clock-parents = <&k3_clks 404 10>; 919 num-lanes = <4>; 920 #reset-cells = <1>; 921 #clock-cells = <1>; 922 ranges = <0x5060000 0x00 0x5060000 0x10000>; 923 status = "disabled"; 924 925 serdes0: serdes@5060000 { 926 compatible = "ti,j721e-serdes-10g"; 927 reg = <0x05060000 0x010000>; 928 reg-names = "torrent_phy"; 929 resets = <&serdes_wiz0 0>; 930 reset-names = "torrent_reset"; 931 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 932 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 933 clock-names = "refclk", "phy_en_refclk"; 934 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 935 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 936 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 937 assigned-clock-parents = <&k3_clks 404 6>, 938 <&k3_clks 404 6>, 939 <&k3_clks 404 6>; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 #clock-cells = <1>; 943 status = "disabled"; 944 }; 945 }; 946 947 serdes_wiz1: wiz@5070000 { 948 compatible = "ti,j784s4-wiz-10g"; 949 #address-cells = <1>; 950 #size-cells = <1>; 951 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 952 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 953 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 954 assigned-clocks = <&k3_clks 405 6>; 955 assigned-clock-parents = <&k3_clks 405 10>; 956 num-lanes = <4>; 957 #reset-cells = <1>; 958 #clock-cells = <1>; 959 ranges = <0x05070000 0x00 0x05070000 0x10000>; 960 status = "disabled"; 961 962 serdes1: serdes@5070000 { 963 compatible = "ti,j721e-serdes-10g"; 964 reg = <0x05070000 0x010000>; 965 reg-names = "torrent_phy"; 966 resets = <&serdes_wiz1 0>; 967 reset-names = "torrent_reset"; 968 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 969 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 970 clock-names = "refclk", "phy_en_refclk"; 971 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 972 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 973 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 974 assigned-clock-parents = <&k3_clks 405 6>, 975 <&k3_clks 405 6>, 976 <&k3_clks 405 6>; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 #clock-cells = <1>; 980 status = "disabled"; 981 }; 982 }; 983 984 serdes_wiz2: wiz@5020000 { 985 compatible = "ti,j784s4-wiz-10g"; 986 #address-cells = <1>; 987 #size-cells = <1>; 988 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; 989 clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; 990 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 991 assigned-clocks = <&k3_clks 406 6>; 992 assigned-clock-parents = <&k3_clks 406 10>; 993 num-lanes = <4>; 994 #reset-cells = <1>; 995 #clock-cells = <1>; 996 ranges = <0x05020000 0x00 0x05020000 0x10000>; 997 status = "disabled"; 998 999 serdes2: serdes@5020000 { 1000 compatible = "ti,j721e-serdes-10g"; 1001 reg = <0x05020000 0x010000>; 1002 reg-names = "torrent_phy"; 1003 resets = <&serdes_wiz2 0>; 1004 reset-names = "torrent_reset"; 1005 clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 1006 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; 1007 clock-names = "refclk", "phy_en_refclk"; 1008 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 1009 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, 1010 <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; 1011 assigned-clock-parents = <&k3_clks 406 6>, 1012 <&k3_clks 406 6>, 1013 <&k3_clks 406 6>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 #clock-cells = <1>; 1017 status = "disabled"; 1018 }; 1019 }; 1020 1021 serdes_wiz4: wiz@5050000 { 1022 compatible = "ti,j784s4-wiz-10g"; 1023 #address-cells = <1>; 1024 #size-cells = <1>; 1025 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 1026 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 1027 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1028 assigned-clocks = <&k3_clks 407 6>; 1029 assigned-clock-parents = <&k3_clks 407 10>; 1030 num-lanes = <4>; 1031 #reset-cells = <1>; 1032 #clock-cells = <1>; 1033 ranges = <0x05050000 0x00 0x05050000 0x10000>, 1034 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 1035 status = "disabled"; 1036 1037 serdes4: serdes@5050000 { 1038 /* 1039 * Note: we also map DPTX PHY registers as the Torrent 1040 * needs to manage those. 1041 */ 1042 compatible = "ti,j721e-serdes-10g"; 1043 reg = <0x05050000 0x010000>, 1044 <0x0a030a00 0x40>; /* DPTX PHY */ 1045 reg-names = "torrent_phy"; 1046 resets = <&serdes_wiz4 0>; 1047 reset-names = "torrent_reset"; 1048 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1049 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 1050 clock-names = "refclk", "phy_en_refclk"; 1051 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1052 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1053 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1054 assigned-clock-parents = <&k3_clks 407 6>, 1055 <&k3_clks 407 6>, 1056 <&k3_clks 407 6>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 #clock-cells = <1>; 1060 status = "disabled"; 1061 }; 1062 }; 1063 1064 main_navss: bus@30000000 { 1065 bootph-all; 1066 compatible = "simple-bus"; 1067 #address-cells = <2>; 1068 #size-cells = <2>; 1069 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 1070 ti,sci-dev-id = <280>; 1071 dma-coherent; 1072 dma-ranges; 1073 1074 main_navss_intr: interrupt-controller@310e0000 { 1075 compatible = "ti,sci-intr"; 1076 reg = <0x00 0x310e0000 0x00 0x4000>; 1077 ti,intr-trigger-type = <4>; 1078 interrupt-controller; 1079 interrupt-parent = <&gic500>; 1080 #interrupt-cells = <1>; 1081 ti,sci = <&sms>; 1082 ti,sci-dev-id = <283>; 1083 ti,interrupt-ranges = <0 64 64>, 1084 <64 448 64>, 1085 <128 672 64>; 1086 }; 1087 1088 main_udmass_inta: msi-controller@33d00000 { 1089 compatible = "ti,sci-inta"; 1090 reg = <0x00 0x33d00000 0x00 0x100000>; 1091 interrupt-controller; 1092 #interrupt-cells = <0>; 1093 interrupt-parent = <&main_navss_intr>; 1094 msi-controller; 1095 ti,sci = <&sms>; 1096 ti,sci-dev-id = <321>; 1097 ti,interrupt-ranges = <0 0 256>; 1098 ti,unmapped-event-sources = <&main_bcdma_csi>; 1099 }; 1100 1101 secure_proxy_main: mailbox@32c00000 { 1102 bootph-all; 1103 compatible = "ti,am654-secure-proxy"; 1104 #mbox-cells = <1>; 1105 reg-names = "target_data", "rt", "scfg"; 1106 reg = <0x00 0x32c00000 0x00 0x100000>, 1107 <0x00 0x32400000 0x00 0x100000>, 1108 <0x00 0x32800000 0x00 0x100000>; 1109 interrupt-names = "rx_011"; 1110 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1111 }; 1112 1113 hwspinlock: hwlock@30e00000 { 1114 compatible = "ti,am654-hwspinlock"; 1115 reg = <0x00 0x30e00000 0x00 0x1000>; 1116 #hwlock-cells = <1>; 1117 }; 1118 1119 mailbox0_cluster0: mailbox@31f80000 { 1120 compatible = "ti,am654-mailbox"; 1121 reg = <0x00 0x31f80000 0x00 0x200>; 1122 #mbox-cells = <1>; 1123 ti,mbox-num-users = <4>; 1124 ti,mbox-num-fifos = <16>; 1125 interrupt-parent = <&main_navss_intr>; 1126 status = "disabled"; 1127 }; 1128 1129 mailbox0_cluster1: mailbox@31f81000 { 1130 compatible = "ti,am654-mailbox"; 1131 reg = <0x00 0x31f81000 0x00 0x200>; 1132 #mbox-cells = <1>; 1133 ti,mbox-num-users = <4>; 1134 ti,mbox-num-fifos = <16>; 1135 interrupt-parent = <&main_navss_intr>; 1136 status = "disabled"; 1137 }; 1138 1139 mailbox0_cluster2: mailbox@31f82000 { 1140 compatible = "ti,am654-mailbox"; 1141 reg = <0x00 0x31f82000 0x00 0x200>; 1142 #mbox-cells = <1>; 1143 ti,mbox-num-users = <4>; 1144 ti,mbox-num-fifos = <16>; 1145 interrupt-parent = <&main_navss_intr>; 1146 status = "disabled"; 1147 }; 1148 1149 mailbox0_cluster3: mailbox@31f83000 { 1150 compatible = "ti,am654-mailbox"; 1151 reg = <0x00 0x31f83000 0x00 0x200>; 1152 #mbox-cells = <1>; 1153 ti,mbox-num-users = <4>; 1154 ti,mbox-num-fifos = <16>; 1155 interrupt-parent = <&main_navss_intr>; 1156 status = "disabled"; 1157 }; 1158 1159 mailbox0_cluster4: mailbox@31f84000 { 1160 compatible = "ti,am654-mailbox"; 1161 reg = <0x00 0x31f84000 0x00 0x200>; 1162 #mbox-cells = <1>; 1163 ti,mbox-num-users = <4>; 1164 ti,mbox-num-fifos = <16>; 1165 interrupt-parent = <&main_navss_intr>; 1166 status = "disabled"; 1167 }; 1168 1169 mailbox0_cluster5: mailbox@31f85000 { 1170 compatible = "ti,am654-mailbox"; 1171 reg = <0x00 0x31f85000 0x00 0x200>; 1172 #mbox-cells = <1>; 1173 ti,mbox-num-users = <4>; 1174 ti,mbox-num-fifos = <16>; 1175 interrupt-parent = <&main_navss_intr>; 1176 status = "disabled"; 1177 }; 1178 1179 mailbox0_cluster6: mailbox@31f86000 { 1180 compatible = "ti,am654-mailbox"; 1181 reg = <0x00 0x31f86000 0x00 0x200>; 1182 #mbox-cells = <1>; 1183 ti,mbox-num-users = <4>; 1184 ti,mbox-num-fifos = <16>; 1185 interrupt-parent = <&main_navss_intr>; 1186 status = "disabled"; 1187 }; 1188 1189 mailbox0_cluster7: mailbox@31f87000 { 1190 compatible = "ti,am654-mailbox"; 1191 reg = <0x00 0x31f87000 0x00 0x200>; 1192 #mbox-cells = <1>; 1193 ti,mbox-num-users = <4>; 1194 ti,mbox-num-fifos = <16>; 1195 interrupt-parent = <&main_navss_intr>; 1196 status = "disabled"; 1197 }; 1198 1199 mailbox0_cluster8: mailbox@31f88000 { 1200 compatible = "ti,am654-mailbox"; 1201 reg = <0x00 0x31f88000 0x00 0x200>; 1202 #mbox-cells = <1>; 1203 ti,mbox-num-users = <4>; 1204 ti,mbox-num-fifos = <16>; 1205 interrupt-parent = <&main_navss_intr>; 1206 status = "disabled"; 1207 }; 1208 1209 mailbox0_cluster9: mailbox@31f89000 { 1210 compatible = "ti,am654-mailbox"; 1211 reg = <0x00 0x31f89000 0x00 0x200>; 1212 #mbox-cells = <1>; 1213 ti,mbox-num-users = <4>; 1214 ti,mbox-num-fifos = <16>; 1215 interrupt-parent = <&main_navss_intr>; 1216 status = "disabled"; 1217 }; 1218 1219 mailbox0_cluster10: mailbox@31f8a000 { 1220 compatible = "ti,am654-mailbox"; 1221 reg = <0x00 0x31f8a000 0x00 0x200>; 1222 #mbox-cells = <1>; 1223 ti,mbox-num-users = <4>; 1224 ti,mbox-num-fifos = <16>; 1225 interrupt-parent = <&main_navss_intr>; 1226 status = "disabled"; 1227 }; 1228 1229 mailbox0_cluster11: mailbox@31f8b000 { 1230 compatible = "ti,am654-mailbox"; 1231 reg = <0x00 0x31f8b000 0x00 0x200>; 1232 #mbox-cells = <1>; 1233 ti,mbox-num-users = <4>; 1234 ti,mbox-num-fifos = <16>; 1235 interrupt-parent = <&main_navss_intr>; 1236 status = "disabled"; 1237 }; 1238 1239 mailbox1_cluster0: mailbox@31f90000 { 1240 compatible = "ti,am654-mailbox"; 1241 reg = <0x00 0x31f90000 0x00 0x200>; 1242 #mbox-cells = <1>; 1243 ti,mbox-num-users = <4>; 1244 ti,mbox-num-fifos = <16>; 1245 interrupt-parent = <&main_navss_intr>; 1246 status = "disabled"; 1247 }; 1248 1249 mailbox1_cluster1: mailbox@31f91000 { 1250 compatible = "ti,am654-mailbox"; 1251 reg = <0x00 0x31f91000 0x00 0x200>; 1252 #mbox-cells = <1>; 1253 ti,mbox-num-users = <4>; 1254 ti,mbox-num-fifos = <16>; 1255 interrupt-parent = <&main_navss_intr>; 1256 status = "disabled"; 1257 }; 1258 1259 mailbox1_cluster2: mailbox@31f92000 { 1260 compatible = "ti,am654-mailbox"; 1261 reg = <0x00 0x31f92000 0x00 0x200>; 1262 #mbox-cells = <1>; 1263 ti,mbox-num-users = <4>; 1264 ti,mbox-num-fifos = <16>; 1265 interrupt-parent = <&main_navss_intr>; 1266 status = "disabled"; 1267 }; 1268 1269 mailbox1_cluster3: mailbox@31f93000 { 1270 compatible = "ti,am654-mailbox"; 1271 reg = <0x00 0x31f93000 0x00 0x200>; 1272 #mbox-cells = <1>; 1273 ti,mbox-num-users = <4>; 1274 ti,mbox-num-fifos = <16>; 1275 interrupt-parent = <&main_navss_intr>; 1276 status = "disabled"; 1277 }; 1278 1279 mailbox1_cluster4: mailbox@31f94000 { 1280 compatible = "ti,am654-mailbox"; 1281 reg = <0x00 0x31f94000 0x00 0x200>; 1282 #mbox-cells = <1>; 1283 ti,mbox-num-users = <4>; 1284 ti,mbox-num-fifos = <16>; 1285 interrupt-parent = <&main_navss_intr>; 1286 status = "disabled"; 1287 }; 1288 1289 mailbox1_cluster5: mailbox@31f95000 { 1290 compatible = "ti,am654-mailbox"; 1291 reg = <0x00 0x31f95000 0x00 0x200>; 1292 #mbox-cells = <1>; 1293 ti,mbox-num-users = <4>; 1294 ti,mbox-num-fifos = <16>; 1295 interrupt-parent = <&main_navss_intr>; 1296 status = "disabled"; 1297 }; 1298 1299 mailbox1_cluster6: mailbox@31f96000 { 1300 compatible = "ti,am654-mailbox"; 1301 reg = <0x00 0x31f96000 0x00 0x200>; 1302 #mbox-cells = <1>; 1303 ti,mbox-num-users = <4>; 1304 ti,mbox-num-fifos = <16>; 1305 interrupt-parent = <&main_navss_intr>; 1306 status = "disabled"; 1307 }; 1308 1309 mailbox1_cluster7: mailbox@31f97000 { 1310 compatible = "ti,am654-mailbox"; 1311 reg = <0x00 0x31f97000 0x00 0x200>; 1312 #mbox-cells = <1>; 1313 ti,mbox-num-users = <4>; 1314 ti,mbox-num-fifos = <16>; 1315 interrupt-parent = <&main_navss_intr>; 1316 status = "disabled"; 1317 }; 1318 1319 mailbox1_cluster8: mailbox@31f98000 { 1320 compatible = "ti,am654-mailbox"; 1321 reg = <0x00 0x31f98000 0x00 0x200>; 1322 #mbox-cells = <1>; 1323 ti,mbox-num-users = <4>; 1324 ti,mbox-num-fifos = <16>; 1325 interrupt-parent = <&main_navss_intr>; 1326 status = "disabled"; 1327 }; 1328 1329 mailbox1_cluster9: mailbox@31f99000 { 1330 compatible = "ti,am654-mailbox"; 1331 reg = <0x00 0x31f99000 0x00 0x200>; 1332 #mbox-cells = <1>; 1333 ti,mbox-num-users = <4>; 1334 ti,mbox-num-fifos = <16>; 1335 interrupt-parent = <&main_navss_intr>; 1336 status = "disabled"; 1337 }; 1338 1339 mailbox1_cluster10: mailbox@31f9a000 { 1340 compatible = "ti,am654-mailbox"; 1341 reg = <0x00 0x31f9a000 0x00 0x200>; 1342 #mbox-cells = <1>; 1343 ti,mbox-num-users = <4>; 1344 ti,mbox-num-fifos = <16>; 1345 interrupt-parent = <&main_navss_intr>; 1346 status = "disabled"; 1347 }; 1348 1349 mailbox1_cluster11: mailbox@31f9b000 { 1350 compatible = "ti,am654-mailbox"; 1351 reg = <0x00 0x31f9b000 0x00 0x200>; 1352 #mbox-cells = <1>; 1353 ti,mbox-num-users = <4>; 1354 ti,mbox-num-fifos = <16>; 1355 interrupt-parent = <&main_navss_intr>; 1356 status = "disabled"; 1357 }; 1358 1359 main_ringacc: ringacc@3c000000 { 1360 compatible = "ti,am654-navss-ringacc"; 1361 reg = <0x00 0x3c000000 0x00 0x400000>, 1362 <0x00 0x38000000 0x00 0x400000>, 1363 <0x00 0x31120000 0x00 0x100>, 1364 <0x00 0x33000000 0x00 0x40000>, 1365 <0x00 0x31080000 0x00 0x40000>; 1366 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1367 ti,num-rings = <1024>; 1368 ti,sci-rm-range-gp-rings = <0x1>; 1369 ti,sci = <&sms>; 1370 ti,sci-dev-id = <315>; 1371 msi-parent = <&main_udmass_inta>; 1372 }; 1373 1374 main_udmap: dma-controller@31150000 { 1375 compatible = "ti,j721e-navss-main-udmap"; 1376 reg = <0x00 0x31150000 0x00 0x100>, 1377 <0x00 0x34000000 0x00 0x80000>, 1378 <0x00 0x35000000 0x00 0x200000>, 1379 <0x00 0x30b00000 0x00 0x20000>, 1380 <0x00 0x30c00000 0x00 0x8000>, 1381 <0x00 0x30d00000 0x00 0x4000>; 1382 reg-names = "gcfg", "rchanrt", "tchanrt", 1383 "tchan", "rchan", "rflow"; 1384 msi-parent = <&main_udmass_inta>; 1385 #dma-cells = <1>; 1386 1387 ti,sci = <&sms>; 1388 ti,sci-dev-id = <319>; 1389 ti,ringacc = <&main_ringacc>; 1390 1391 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1392 <0x0f>, /* TX_HCHAN */ 1393 <0x10>; /* TX_UHCHAN */ 1394 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1395 <0x0b>, /* RX_HCHAN */ 1396 <0x0c>; /* RX_UHCHAN */ 1397 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1398 }; 1399 1400 main_bcdma_csi: dma-controller@311a0000 { 1401 compatible = "ti,j721s2-dmss-bcdma-csi"; 1402 reg = <0x00 0x311a0000 0x00 0x100>, 1403 <0x00 0x35d00000 0x00 0x20000>, 1404 <0x00 0x35c00000 0x00 0x10000>, 1405 <0x00 0x35e00000 0x00 0x80000>; 1406 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1407 msi-parent = <&main_udmass_inta>; 1408 #dma-cells = <3>; 1409 ti,sci = <&sms>; 1410 ti,sci-dev-id = <281>; 1411 ti,sci-rm-range-rchan = <0x21>; 1412 ti,sci-rm-range-tchan = <0x22>; 1413 }; 1414 1415 cpts@310d0000 { 1416 compatible = "ti,j721e-cpts"; 1417 reg = <0x00 0x310d0000 0x00 0x400>; 1418 reg-names = "cpts"; 1419 clocks = <&k3_clks 282 0>; 1420 clock-names = "cpts"; 1421 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1422 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1423 interrupts-extended = <&main_navss_intr 391>; 1424 interrupt-names = "cpts"; 1425 ti,cpts-periodic-outputs = <6>; 1426 ti,cpts-ext-ts-inputs = <8>; 1427 }; 1428 }; 1429 1430 main_mcan0: can@2701000 { 1431 compatible = "bosch,m_can"; 1432 reg = <0x00 0x02701000 0x00 0x200>, 1433 <0x00 0x02708000 0x00 0x8000>; 1434 reg-names = "m_can", "message_ram"; 1435 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1436 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1437 clock-names = "hclk", "cclk"; 1438 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1440 interrupt-names = "int0", "int1"; 1441 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1442 status = "disabled"; 1443 }; 1444 1445 main_mcan1: can@2711000 { 1446 compatible = "bosch,m_can"; 1447 reg = <0x00 0x02711000 0x00 0x200>, 1448 <0x00 0x02718000 0x00 0x8000>; 1449 reg-names = "m_can", "message_ram"; 1450 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1451 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1452 clock-names = "hclk", "cclk"; 1453 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1455 interrupt-names = "int0", "int1"; 1456 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1457 status = "disabled"; 1458 }; 1459 1460 main_mcan2: can@2721000 { 1461 compatible = "bosch,m_can"; 1462 reg = <0x00 0x02721000 0x00 0x200>, 1463 <0x00 0x02728000 0x00 0x8000>; 1464 reg-names = "m_can", "message_ram"; 1465 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1466 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1467 clock-names = "hclk", "cclk"; 1468 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1470 interrupt-names = "int0", "int1"; 1471 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1472 status = "disabled"; 1473 }; 1474 1475 main_mcan3: can@2731000 { 1476 compatible = "bosch,m_can"; 1477 reg = <0x00 0x02731000 0x00 0x200>, 1478 <0x00 0x02738000 0x00 0x8000>; 1479 reg-names = "m_can", "message_ram"; 1480 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1481 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1482 clock-names = "hclk", "cclk"; 1483 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1485 interrupt-names = "int0", "int1"; 1486 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1487 status = "disabled"; 1488 }; 1489 1490 main_mcan4: can@2741000 { 1491 compatible = "bosch,m_can"; 1492 reg = <0x00 0x02741000 0x00 0x200>, 1493 <0x00 0x02748000 0x00 0x8000>; 1494 reg-names = "m_can", "message_ram"; 1495 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1496 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1497 clock-names = "hclk", "cclk"; 1498 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1500 interrupt-names = "int0", "int1"; 1501 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1502 status = "disabled"; 1503 }; 1504 1505 main_mcan5: can@2751000 { 1506 compatible = "bosch,m_can"; 1507 reg = <0x00 0x02751000 0x00 0x200>, 1508 <0x00 0x02758000 0x00 0x8000>; 1509 reg-names = "m_can", "message_ram"; 1510 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1511 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1512 clock-names = "hclk", "cclk"; 1513 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1515 interrupt-names = "int0", "int1"; 1516 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1517 status = "disabled"; 1518 }; 1519 1520 main_mcan6: can@2761000 { 1521 compatible = "bosch,m_can"; 1522 reg = <0x00 0x02761000 0x00 0x200>, 1523 <0x00 0x02768000 0x00 0x8000>; 1524 reg-names = "m_can", "message_ram"; 1525 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1526 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1527 clock-names = "hclk", "cclk"; 1528 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1530 interrupt-names = "int0", "int1"; 1531 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1532 status = "disabled"; 1533 }; 1534 1535 main_mcan7: can@2771000 { 1536 compatible = "bosch,m_can"; 1537 reg = <0x00 0x02771000 0x00 0x200>, 1538 <0x00 0x02778000 0x00 0x8000>; 1539 reg-names = "m_can", "message_ram"; 1540 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1541 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1542 clock-names = "hclk", "cclk"; 1543 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1545 interrupt-names = "int0", "int1"; 1546 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1547 status = "disabled"; 1548 }; 1549 1550 main_mcan8: can@2781000 { 1551 compatible = "bosch,m_can"; 1552 reg = <0x00 0x02781000 0x00 0x200>, 1553 <0x00 0x02788000 0x00 0x8000>; 1554 reg-names = "m_can", "message_ram"; 1555 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1556 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1557 clock-names = "hclk", "cclk"; 1558 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupt-names = "int0", "int1"; 1561 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1562 status = "disabled"; 1563 }; 1564 1565 main_mcan9: can@2791000 { 1566 compatible = "bosch,m_can"; 1567 reg = <0x00 0x02791000 0x00 0x200>, 1568 <0x00 0x02798000 0x00 0x8000>; 1569 reg-names = "m_can", "message_ram"; 1570 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1571 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1572 clock-names = "hclk", "cclk"; 1573 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1575 interrupt-names = "int0", "int1"; 1576 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1577 status = "disabled"; 1578 }; 1579 1580 main_mcan10: can@27a1000 { 1581 compatible = "bosch,m_can"; 1582 reg = <0x00 0x027a1000 0x00 0x200>, 1583 <0x00 0x027a8000 0x00 0x8000>; 1584 reg-names = "m_can", "message_ram"; 1585 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1586 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1587 clock-names = "hclk", "cclk"; 1588 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1590 interrupt-names = "int0", "int1"; 1591 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1592 status = "disabled"; 1593 }; 1594 1595 main_mcan11: can@27b1000 { 1596 compatible = "bosch,m_can"; 1597 reg = <0x00 0x027b1000 0x00 0x200>, 1598 <0x00 0x027b8000 0x00 0x8000>; 1599 reg-names = "m_can", "message_ram"; 1600 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1601 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1602 clock-names = "hclk", "cclk"; 1603 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1605 interrupt-names = "int0", "int1"; 1606 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1607 status = "disabled"; 1608 }; 1609 1610 main_mcan12: can@27c1000 { 1611 compatible = "bosch,m_can"; 1612 reg = <0x00 0x027c1000 0x00 0x200>, 1613 <0x00 0x027c8000 0x00 0x8000>; 1614 reg-names = "m_can", "message_ram"; 1615 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1616 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1617 clock-names = "hclk", "cclk"; 1618 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1620 interrupt-names = "int0", "int1"; 1621 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1622 status = "disabled"; 1623 }; 1624 1625 main_mcan13: can@27d1000 { 1626 compatible = "bosch,m_can"; 1627 reg = <0x00 0x027d1000 0x00 0x200>, 1628 <0x00 0x027d8000 0x00 0x8000>; 1629 reg-names = "m_can", "message_ram"; 1630 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1631 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1632 clock-names = "hclk", "cclk"; 1633 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1635 interrupt-names = "int0", "int1"; 1636 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1637 status = "disabled"; 1638 }; 1639 1640 main_mcan14: can@2681000 { 1641 compatible = "bosch,m_can"; 1642 reg = <0x00 0x02681000 0x00 0x200>, 1643 <0x00 0x02688000 0x00 0x8000>; 1644 reg-names = "m_can", "message_ram"; 1645 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1646 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1647 clock-names = "hclk", "cclk"; 1648 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1650 interrupt-names = "int0", "int1"; 1651 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1652 status = "disabled"; 1653 }; 1654 1655 main_mcan15: can@2691000 { 1656 compatible = "bosch,m_can"; 1657 reg = <0x00 0x02691000 0x00 0x200>, 1658 <0x00 0x02698000 0x00 0x8000>; 1659 reg-names = "m_can", "message_ram"; 1660 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1661 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 1662 clock-names = "hclk", "cclk"; 1663 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1665 interrupt-names = "int0", "int1"; 1666 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1667 status = "disabled"; 1668 }; 1669 1670 main_mcan16: can@26a1000 { 1671 compatible = "bosch,m_can"; 1672 reg = <0x00 0x026a1000 0x00 0x200>, 1673 <0x00 0x026a8000 0x00 0x8000>; 1674 reg-names = "m_can", "message_ram"; 1675 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 1676 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 1677 clock-names = "hclk", "cclk"; 1678 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1680 interrupt-names = "int0", "int1"; 1681 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1682 status = "disabled"; 1683 }; 1684 1685 main_mcan17: can@26b1000 { 1686 compatible = "bosch,m_can"; 1687 reg = <0x00 0x026b1000 0x00 0x200>, 1688 <0x00 0x026b8000 0x00 0x8000>; 1689 reg-names = "m_can", "message_ram"; 1690 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 1691 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 1692 clock-names = "hclk", "cclk"; 1693 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1695 interrupt-names = "int0", "int1"; 1696 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1697 status = "disabled"; 1698 }; 1699 1700 main_spi0: spi@2100000 { 1701 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1702 reg = <0x00 0x02100000 0x00 0x400>; 1703 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 1707 clocks = <&k3_clks 376 1>; 1708 status = "disabled"; 1709 }; 1710 1711 main_spi1: spi@2110000 { 1712 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1713 reg = <0x00 0x02110000 0x00 0x400>; 1714 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 1718 clocks = <&k3_clks 377 1>; 1719 status = "disabled"; 1720 }; 1721 1722 main_spi2: spi@2120000 { 1723 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1724 reg = <0x00 0x02120000 0x00 0x400>; 1725 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1726 #address-cells = <1>; 1727 #size-cells = <0>; 1728 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 1729 clocks = <&k3_clks 378 1>; 1730 status = "disabled"; 1731 }; 1732 1733 main_spi3: spi@2130000 { 1734 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1735 reg = <0x00 0x02130000 0x00 0x400>; 1736 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 1740 clocks = <&k3_clks 379 1>; 1741 status = "disabled"; 1742 }; 1743 1744 main_spi4: spi@2140000 { 1745 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1746 reg = <0x00 0x02140000 0x00 0x400>; 1747 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 1751 clocks = <&k3_clks 380 1>; 1752 status = "disabled"; 1753 }; 1754 1755 main_spi5: spi@2150000 { 1756 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1757 reg = <0x00 0x02150000 0x00 0x400>; 1758 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 1762 clocks = <&k3_clks 381 1>; 1763 status = "disabled"; 1764 }; 1765 1766 main_spi6: spi@2160000 { 1767 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1768 reg = <0x00 0x02160000 0x00 0x400>; 1769 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 1773 clocks = <&k3_clks 382 1>; 1774 status = "disabled"; 1775 }; 1776 1777 main_spi7: spi@2170000 { 1778 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1779 reg = <0x00 0x02170000 0x00 0x400>; 1780 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1781 #address-cells = <1>; 1782 #size-cells = <0>; 1783 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 1784 clocks = <&k3_clks 383 1>; 1785 status = "disabled"; 1786 }; 1787 1788 ufs_wrapper: ufs-wrapper@4e80000 { 1789 compatible = "ti,j721e-ufs"; 1790 reg = <0x00 0x4e80000 0x00 0x100>; 1791 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 1792 clocks = <&k3_clks 387 3>; 1793 assigned-clocks = <&k3_clks 387 3>; 1794 assigned-clock-parents = <&k3_clks 387 6>; 1795 ranges; 1796 #address-cells = <2>; 1797 #size-cells = <2>; 1798 status = "disabled"; 1799 1800 ufs@4e84000 { 1801 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1802 reg = <0x00 0x4e84000 0x00 0x10000>; 1803 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1804 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 1805 <19200000 19200000>; 1806 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 1807 clock-names = "core_clk", "phy_clk", "ref_clk"; 1808 dma-coherent; 1809 }; 1810 }; 1811 1812 main_r5fss0: r5fss@5c00000 { 1813 compatible = "ti,j721s2-r5fss"; 1814 ti,cluster-mode = <1>; 1815 #address-cells = <1>; 1816 #size-cells = <1>; 1817 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1818 <0x5d00000 0x00 0x5d00000 0x20000>; 1819 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 1820 1821 main_r5fss0_core0: r5f@5c00000 { 1822 compatible = "ti,j721s2-r5f"; 1823 reg = <0x5c00000 0x00010000>, 1824 <0x5c10000 0x00010000>; 1825 reg-names = "atcm", "btcm"; 1826 ti,sci = <&sms>; 1827 ti,sci-dev-id = <339>; 1828 ti,sci-proc-ids = <0x06 0xff>; 1829 resets = <&k3_reset 339 1>; 1830 firmware-name = "j784s4-main-r5f0_0-fw"; 1831 ti,atcm-enable = <1>; 1832 ti,btcm-enable = <1>; 1833 ti,loczrama = <1>; 1834 }; 1835 1836 main_r5fss0_core1: r5f@5d00000 { 1837 compatible = "ti,j721s2-r5f"; 1838 reg = <0x5d00000 0x00010000>, 1839 <0x5d10000 0x00010000>; 1840 reg-names = "atcm", "btcm"; 1841 ti,sci = <&sms>; 1842 ti,sci-dev-id = <340>; 1843 ti,sci-proc-ids = <0x07 0xff>; 1844 resets = <&k3_reset 340 1>; 1845 firmware-name = "j784s4-main-r5f0_1-fw"; 1846 ti,atcm-enable = <1>; 1847 ti,btcm-enable = <1>; 1848 ti,loczrama = <1>; 1849 }; 1850 }; 1851 1852 main_r5fss1: r5fss@5e00000 { 1853 compatible = "ti,j721s2-r5fss"; 1854 ti,cluster-mode = <1>; 1855 #address-cells = <1>; 1856 #size-cells = <1>; 1857 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1858 <0x5f00000 0x00 0x5f00000 0x20000>; 1859 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 1860 1861 main_r5fss1_core0: r5f@5e00000 { 1862 compatible = "ti,j721s2-r5f"; 1863 reg = <0x5e00000 0x00010000>, 1864 <0x5e10000 0x00010000>; 1865 reg-names = "atcm", "btcm"; 1866 ti,sci = <&sms>; 1867 ti,sci-dev-id = <341>; 1868 ti,sci-proc-ids = <0x08 0xff>; 1869 resets = <&k3_reset 341 1>; 1870 firmware-name = "j784s4-main-r5f1_0-fw"; 1871 ti,atcm-enable = <1>; 1872 ti,btcm-enable = <1>; 1873 ti,loczrama = <1>; 1874 }; 1875 1876 main_r5fss1_core1: r5f@5f00000 { 1877 compatible = "ti,j721s2-r5f"; 1878 reg = <0x5f00000 0x00010000>, 1879 <0x5f10000 0x00010000>; 1880 reg-names = "atcm", "btcm"; 1881 ti,sci = <&sms>; 1882 ti,sci-dev-id = <342>; 1883 ti,sci-proc-ids = <0x09 0xff>; 1884 resets = <&k3_reset 342 1>; 1885 firmware-name = "j784s4-main-r5f1_1-fw"; 1886 ti,atcm-enable = <1>; 1887 ti,btcm-enable = <1>; 1888 ti,loczrama = <1>; 1889 }; 1890 }; 1891 1892 main_r5fss2: r5fss@5900000 { 1893 compatible = "ti,j721s2-r5fss"; 1894 ti,cluster-mode = <1>; 1895 #address-cells = <1>; 1896 #size-cells = <1>; 1897 ranges = <0x5900000 0x00 0x5900000 0x20000>, 1898 <0x5a00000 0x00 0x5a00000 0x20000>; 1899 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 1900 1901 main_r5fss2_core0: r5f@5900000 { 1902 compatible = "ti,j721s2-r5f"; 1903 reg = <0x5900000 0x00010000>, 1904 <0x5910000 0x00010000>; 1905 reg-names = "atcm", "btcm"; 1906 ti,sci = <&sms>; 1907 ti,sci-dev-id = <343>; 1908 ti,sci-proc-ids = <0x0a 0xff>; 1909 resets = <&k3_reset 343 1>; 1910 firmware-name = "j784s4-main-r5f2_0-fw"; 1911 ti,atcm-enable = <1>; 1912 ti,btcm-enable = <1>; 1913 ti,loczrama = <1>; 1914 }; 1915 1916 main_r5fss2_core1: r5f@5a00000 { 1917 compatible = "ti,j721s2-r5f"; 1918 reg = <0x5a00000 0x00010000>, 1919 <0x5a10000 0x00010000>; 1920 reg-names = "atcm", "btcm"; 1921 ti,sci = <&sms>; 1922 ti,sci-dev-id = <344>; 1923 ti,sci-proc-ids = <0x0b 0xff>; 1924 resets = <&k3_reset 344 1>; 1925 firmware-name = "j784s4-main-r5f2_1-fw"; 1926 ti,atcm-enable = <1>; 1927 ti,btcm-enable = <1>; 1928 ti,loczrama = <1>; 1929 }; 1930 }; 1931 1932 c71_0: dsp@64800000 { 1933 compatible = "ti,j721s2-c71-dsp"; 1934 reg = <0x00 0x64800000 0x00 0x00080000>, 1935 <0x00 0x64e00000 0x00 0x0000c000>; 1936 reg-names = "l2sram", "l1dram"; 1937 ti,sci = <&sms>; 1938 ti,sci-dev-id = <30>; 1939 ti,sci-proc-ids = <0x30 0xff>; 1940 resets = <&k3_reset 30 1>; 1941 firmware-name = "j784s4-c71_0-fw"; 1942 status = "disabled"; 1943 }; 1944 1945 c71_1: dsp@65800000 { 1946 compatible = "ti,j721s2-c71-dsp"; 1947 reg = <0x00 0x65800000 0x00 0x00080000>, 1948 <0x00 0x65e00000 0x00 0x0000c000>; 1949 reg-names = "l2sram", "l1dram"; 1950 ti,sci = <&sms>; 1951 ti,sci-dev-id = <33>; 1952 ti,sci-proc-ids = <0x31 0xff>; 1953 resets = <&k3_reset 33 1>; 1954 firmware-name = "j784s4-c71_1-fw"; 1955 status = "disabled"; 1956 }; 1957 1958 c71_2: dsp@66800000 { 1959 compatible = "ti,j721s2-c71-dsp"; 1960 reg = <0x00 0x66800000 0x00 0x00080000>, 1961 <0x00 0x66e00000 0x00 0x0000c000>; 1962 reg-names = "l2sram", "l1dram"; 1963 ti,sci = <&sms>; 1964 ti,sci-dev-id = <37>; 1965 ti,sci-proc-ids = <0x32 0xff>; 1966 resets = <&k3_reset 37 1>; 1967 firmware-name = "j784s4-c71_2-fw"; 1968 status = "disabled"; 1969 }; 1970 1971 c71_3: dsp@67800000 { 1972 compatible = "ti,j721s2-c71-dsp"; 1973 reg = <0x00 0x67800000 0x00 0x00080000>, 1974 <0x00 0x67e00000 0x00 0x0000c000>; 1975 reg-names = "l2sram", "l1dram"; 1976 ti,sci = <&sms>; 1977 ti,sci-dev-id = <40>; 1978 ti,sci-proc-ids = <0x33 0xff>; 1979 resets = <&k3_reset 40 1>; 1980 firmware-name = "j784s4-c71_3-fw"; 1981 status = "disabled"; 1982 }; 1983 1984 main_esm: esm@700000 { 1985 compatible = "ti,j721e-esm"; 1986 reg = <0x00 0x700000 0x00 0x1000>; 1987 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 1988 <695>; 1989 bootph-pre-ram; 1990 }; 1991 1992 watchdog0: watchdog@2200000 { 1993 compatible = "ti,j7-rti-wdt"; 1994 reg = <0x00 0x2200000 0x00 0x100>; 1995 clocks = <&k3_clks 348 1>; 1996 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 1997 assigned-clocks = <&k3_clks 348 0>; 1998 assigned-clock-parents = <&k3_clks 348 4>; 1999 }; 2000 2001 watchdog1: watchdog@2210000 { 2002 compatible = "ti,j7-rti-wdt"; 2003 reg = <0x00 0x2210000 0x00 0x100>; 2004 clocks = <&k3_clks 349 1>; 2005 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 2006 assigned-clocks = <&k3_clks 349 0>; 2007 assigned-clock-parents = <&k3_clks 349 4>; 2008 }; 2009 2010 watchdog2: watchdog@2220000 { 2011 compatible = "ti,j7-rti-wdt"; 2012 reg = <0x00 0x2220000 0x00 0x100>; 2013 clocks = <&k3_clks 350 1>; 2014 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 2015 assigned-clocks = <&k3_clks 350 0>; 2016 assigned-clock-parents = <&k3_clks 350 4>; 2017 }; 2018 2019 watchdog3: watchdog@2230000 { 2020 compatible = "ti,j7-rti-wdt"; 2021 reg = <0x00 0x2230000 0x00 0x100>; 2022 clocks = <&k3_clks 351 1>; 2023 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 2024 assigned-clocks = <&k3_clks 351 0>; 2025 assigned-clock-parents = <&k3_clks 351 4>; 2026 }; 2027 2028 watchdog4: watchdog@2240000 { 2029 compatible = "ti,j7-rti-wdt"; 2030 reg = <0x00 0x2240000 0x00 0x100>; 2031 clocks = <&k3_clks 352 1>; 2032 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 2033 assigned-clocks = <&k3_clks 352 0>; 2034 assigned-clock-parents = <&k3_clks 352 4>; 2035 }; 2036 2037 watchdog5: watchdog@2250000 { 2038 compatible = "ti,j7-rti-wdt"; 2039 reg = <0x00 0x2250000 0x00 0x100>; 2040 clocks = <&k3_clks 353 1>; 2041 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 2042 assigned-clocks = <&k3_clks 353 0>; 2043 assigned-clock-parents = <&k3_clks 353 4>; 2044 }; 2045 2046 watchdog6: watchdog@2260000 { 2047 compatible = "ti,j7-rti-wdt"; 2048 reg = <0x00 0x2260000 0x00 0x100>; 2049 clocks = <&k3_clks 354 1>; 2050 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 2051 assigned-clocks = <&k3_clks 354 0>; 2052 assigned-clock-parents = <&k3_clks 354 4>; 2053 }; 2054 2055 watchdog7: watchdog@2270000 { 2056 compatible = "ti,j7-rti-wdt"; 2057 reg = <0x00 0x2270000 0x00 0x100>; 2058 clocks = <&k3_clks 355 1>; 2059 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 2060 assigned-clocks = <&k3_clks 355 0>; 2061 assigned-clock-parents = <&k3_clks 355 4>; 2062 }; 2063 2064 /* 2065 * The following RTI instances are coupled with MCU R5Fs, c7x and 2066 * GPU so keeping them reserved as these will be used by their 2067 * respective firmware 2068 */ 2069 watchdog8: watchdog@22f0000 { 2070 compatible = "ti,j7-rti-wdt"; 2071 reg = <0x00 0x22f0000 0x00 0x100>; 2072 clocks = <&k3_clks 360 1>; 2073 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 2074 assigned-clocks = <&k3_clks 360 0>; 2075 assigned-clock-parents = <&k3_clks 360 4>; 2076 /* reserved for GPU */ 2077 status = "reserved"; 2078 }; 2079 2080 watchdog9: watchdog@2300000 { 2081 compatible = "ti,j7-rti-wdt"; 2082 reg = <0x00 0x2300000 0x00 0x100>; 2083 clocks = <&k3_clks 356 1>; 2084 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 2085 assigned-clocks = <&k3_clks 356 0>; 2086 assigned-clock-parents = <&k3_clks 356 4>; 2087 /* reserved for C7X_0 DSP */ 2088 status = "reserved"; 2089 }; 2090 2091 watchdog10: watchdog@2310000 { 2092 compatible = "ti,j7-rti-wdt"; 2093 reg = <0x00 0x2310000 0x00 0x100>; 2094 clocks = <&k3_clks 357 1>; 2095 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 2096 assigned-clocks = <&k3_clks 357 0>; 2097 assigned-clock-parents = <&k3_clks 357 4>; 2098 /* reserved for C7X_1 DSP */ 2099 status = "reserved"; 2100 }; 2101 2102 watchdog11: watchdog@2320000 { 2103 compatible = "ti,j7-rti-wdt"; 2104 reg = <0x00 0x2320000 0x00 0x100>; 2105 clocks = <&k3_clks 358 1>; 2106 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 2107 assigned-clocks = <&k3_clks 358 0>; 2108 assigned-clock-parents = <&k3_clks 358 4>; 2109 /* reserved for C7X_2 DSP */ 2110 status = "reserved"; 2111 }; 2112 2113 watchdog12: watchdog@2330000 { 2114 compatible = "ti,j7-rti-wdt"; 2115 reg = <0x00 0x2330000 0x00 0x100>; 2116 clocks = <&k3_clks 359 1>; 2117 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 2118 assigned-clocks = <&k3_clks 359 0>; 2119 assigned-clock-parents = <&k3_clks 359 4>; 2120 /* reserved for C7X_3 DSP */ 2121 status = "reserved"; 2122 }; 2123 2124 watchdog13: watchdog@23c0000 { 2125 compatible = "ti,j7-rti-wdt"; 2126 reg = <0x00 0x23c0000 0x00 0x100>; 2127 clocks = <&k3_clks 361 1>; 2128 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 2129 assigned-clocks = <&k3_clks 361 0>; 2130 assigned-clock-parents = <&k3_clks 361 4>; 2131 /* reserved for MAIN_R5F0_0 */ 2132 status = "reserved"; 2133 }; 2134 2135 watchdog14: watchdog@23d0000 { 2136 compatible = "ti,j7-rti-wdt"; 2137 reg = <0x00 0x23d0000 0x00 0x100>; 2138 clocks = <&k3_clks 362 1>; 2139 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 2140 assigned-clocks = <&k3_clks 362 0>; 2141 assigned-clock-parents = <&k3_clks 362 4>; 2142 /* reserved for MAIN_R5F0_1 */ 2143 status = "reserved"; 2144 }; 2145 2146 watchdog15: watchdog@23e0000 { 2147 compatible = "ti,j7-rti-wdt"; 2148 reg = <0x00 0x23e0000 0x00 0x100>; 2149 clocks = <&k3_clks 363 1>; 2150 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 2151 assigned-clocks = <&k3_clks 363 0>; 2152 assigned-clock-parents = <&k3_clks 363 4>; 2153 /* reserved for MAIN_R5F1_0 */ 2154 status = "reserved"; 2155 }; 2156 2157 watchdog16: watchdog@23f0000 { 2158 compatible = "ti,j7-rti-wdt"; 2159 reg = <0x00 0x23f0000 0x00 0x100>; 2160 clocks = <&k3_clks 364 1>; 2161 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 2162 assigned-clocks = <&k3_clks 364 0>; 2163 assigned-clock-parents = <&k3_clks 364 4>; 2164 /* reserved for MAIN_R5F1_1 */ 2165 status = "reserved"; 2166 }; 2167 2168 watchdog17: watchdog@2540000 { 2169 compatible = "ti,j7-rti-wdt"; 2170 reg = <0x00 0x2540000 0x00 0x100>; 2171 clocks = <&k3_clks 365 1>; 2172 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 2173 assigned-clocks = <&k3_clks 365 0>; 2174 assigned-clock-parents = <&k3_clks 366 4>; 2175 /* reserved for MAIN_R5F2_0 */ 2176 status = "reserved"; 2177 }; 2178 2179 watchdog18: watchdog@2550000 { 2180 compatible = "ti,j7-rti-wdt"; 2181 reg = <0x00 0x2550000 0x00 0x100>; 2182 clocks = <&k3_clks 366 1>; 2183 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 2184 assigned-clocks = <&k3_clks 366 0>; 2185 assigned-clock-parents = <&k3_clks 366 4>; 2186 /* reserved for MAIN_R5F2_1 */ 2187 status = "reserved"; 2188 }; 2189 2190 mhdp: bridge@a000000 { 2191 compatible = "ti,j721e-mhdp8546"; 2192 reg = <0x0 0xa000000 0x0 0x30a00>, 2193 <0x0 0x4f40000 0x0 0x20>; 2194 reg-names = "mhdptx", "j721e-intg"; 2195 clocks = <&k3_clks 217 11>; 2196 interrupt-parent = <&gic500>; 2197 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2198 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2199 status = "disabled"; 2200 2201 dp0_ports: ports { 2202 #address-cells = <1>; 2203 #size-cells = <0>; 2204 /* Remote-endpoints are on the boards so 2205 * ports are defined in the platform dt file. 2206 */ 2207 }; 2208 }; 2209 2210 dss: dss@4a00000 { 2211 compatible = "ti,j721e-dss"; 2212 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2213 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2214 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2215 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2216 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2217 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2218 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2219 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2220 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2221 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2222 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2223 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2224 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2225 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2226 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2227 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2228 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2229 reg-names = "common_m", "common_s0", 2230 "common_s1", "common_s2", 2231 "vidl1", "vidl2","vid1","vid2", 2232 "ovr1", "ovr2", "ovr3", "ovr4", 2233 "vp1", "vp2", "vp3", "vp4", 2234 "wb"; 2235 clocks = <&k3_clks 218 0>, 2236 <&k3_clks 218 2>, 2237 <&k3_clks 218 5>, 2238 <&k3_clks 218 14>, 2239 <&k3_clks 218 18>; 2240 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2241 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2242 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2246 interrupt-names = "common_m", 2247 "common_s0", 2248 "common_s1", 2249 "common_s2"; 2250 status = "disabled"; 2251 2252 dss_ports: ports { 2253 /* Ports that DSS drives are platform specific 2254 * so they are defined in platform dt file. 2255 */ 2256 }; 2257 }; 2258}; 2259