1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 /* 25 * MSMC is configured by bootloaders and a runtime fixup is done in the 26 * DT for this node 27 */ 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x00 0x70000000 0x00 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x00 0x20000>; 37 }; 38 39 tifs-sram@1f0000 { 40 reg = <0x1f0000 0x10000>; 41 }; 42 43 l3cache-sram@200000 { 44 reg = <0x200000 0x200000>; 45 }; 46 }; 47 48 scm_conf: bus@100000 { 49 compatible = "simple-bus"; 50 reg = <0x00 0x00100000 0x00 0x1c000>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 ranges = <0x00 0x00 0x00100000 0x1c000>; 54 55 cpsw1_phy_gmii_sel: phy@4034 { 56 compatible = "ti,am654-phy-gmii-sel"; 57 reg = <0x4034 0x4>; 58 #phy-cells = <1>; 59 }; 60 61 cpsw0_phy_gmii_sel: phy@4044 { 62 compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; 63 reg = <0x4044 0x20>; 64 #phy-cells = <1>; 65 ti,qsgmii-main-ports = <7>, <7>; 66 }; 67 68 pcie0_ctrl: pcie0-ctrl@4070 { 69 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 70 reg = <0x4070 0x4>; 71 }; 72 73 pcie1_ctrl: pcie1-ctrl@4074 { 74 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 75 reg = <0x4074 0x4>; 76 }; 77 78 serdes_ln_ctrl: mux-controller@4080 { 79 compatible = "reg-mux"; 80 reg = <0x00004080 0x30>; 81 #mux-control-cells = <1>; 82 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 83 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ 84 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 85 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ 86 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 87 <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ 88 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 89 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 90 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 91 <J784S4_SERDES0_LANE3_USB>, 92 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 93 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 94 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 95 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 96 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 97 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 98 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 99 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 100 <J784S4_SERDES4_LANE0_EDP_LANE0>, 101 <J784S4_SERDES4_LANE1_EDP_LANE1>, 102 <J784S4_SERDES4_LANE2_EDP_LANE2>, 103 <J784S4_SERDES4_LANE3_EDP_LANE3>; 104 }; 105 106 usb_serdes_mux: mux-controller@4000 { 107 compatible = "reg-mux"; 108 reg = <0x4000 0x4>; 109 #mux-control-cells = <1>; 110 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ 111 }; 112 113 ehrpwm_tbclk: clock-controller@4140 { 114 compatible = "ti,am654-ehrpwm-tbclk"; 115 reg = <0x4140 0x18>; 116 #clock-cells = <1>; 117 }; 118 119 audio_refclk1: clock@82e4 { 120 compatible = "ti,am62-audio-refclk"; 121 reg = <0x82e4 0x4>; 122 clocks = <&k3_clks 157 34>; 123 assigned-clocks = <&k3_clks 157 34>; 124 assigned-clock-parents = <&k3_clks 157 63>; 125 #clock-cells = <0>; 126 }; 127 }; 128 129 main_ehrpwm0: pwm@3000000 { 130 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 131 reg = <0x00 0x3000000 0x00 0x100>; 132 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; 133 clock-names = "tbclk", "fck"; 134 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 135 #pwm-cells = <3>; 136 status = "disabled"; 137 }; 138 139 main_ehrpwm1: pwm@3010000 { 140 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 141 reg = <0x00 0x3010000 0x00 0x100>; 142 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; 143 clock-names = "tbclk", "fck"; 144 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 145 #pwm-cells = <3>; 146 status = "disabled"; 147 }; 148 149 main_ehrpwm2: pwm@3020000 { 150 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 151 reg = <0x00 0x3020000 0x00 0x100>; 152 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; 153 clock-names = "tbclk", "fck"; 154 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 155 #pwm-cells = <3>; 156 status = "disabled"; 157 }; 158 159 main_ehrpwm3: pwm@3030000 { 160 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 161 reg = <0x00 0x3030000 0x00 0x100>; 162 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; 163 clock-names = "tbclk", "fck"; 164 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 165 #pwm-cells = <3>; 166 status = "disabled"; 167 }; 168 169 main_ehrpwm4: pwm@3040000 { 170 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 171 reg = <0x00 0x3040000 0x00 0x100>; 172 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; 173 clock-names = "tbclk", "fck"; 174 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 175 #pwm-cells = <3>; 176 status = "disabled"; 177 }; 178 179 main_ehrpwm5: pwm@3050000 { 180 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 181 reg = <0x00 0x3050000 0x00 0x100>; 182 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; 183 clock-names = "tbclk", "fck"; 184 power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; 185 #pwm-cells = <3>; 186 status = "disabled"; 187 }; 188 189 gic500: interrupt-controller@1800000 { 190 compatible = "arm,gic-v3"; 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges; 194 #interrupt-cells = <3>; 195 interrupt-controller; 196 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 197 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 198 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 199 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 200 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 201 202 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 203 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 204 205 gic_its: msi-controller@1820000 { 206 compatible = "arm,gic-v3-its"; 207 reg = <0x00 0x01820000 0x00 0x10000>; 208 socionext,synquacer-pre-its = <0x1000000 0x400000>; 209 msi-controller; 210 #msi-cells = <1>; 211 }; 212 }; 213 214 main_gpio_intr: interrupt-controller@a00000 { 215 compatible = "ti,sci-intr"; 216 reg = <0x00 0x00a00000 0x00 0x800>; 217 ti,intr-trigger-type = <1>; 218 interrupt-controller; 219 interrupt-parent = <&gic500>; 220 #interrupt-cells = <1>; 221 ti,sci = <&sms>; 222 ti,sci-dev-id = <10>; 223 ti,interrupt-ranges = <8 392 56>; 224 }; 225 226 main_pmx0: pinctrl@11c000 { 227 compatible = "pinctrl-single"; 228 /* Proxy 0 addressing */ 229 reg = <0x00 0x11c000 0x00 0x120>; 230 #pinctrl-cells = <1>; 231 pinctrl-single,register-width = <32>; 232 pinctrl-single,function-mask = <0xffffffff>; 233 }; 234 235 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 236 main_timerio_input: pinctrl@104200 { 237 compatible = "pinctrl-single"; 238 reg = <0x00 0x104200 0x00 0x50>; 239 #pinctrl-cells = <1>; 240 pinctrl-single,register-width = <32>; 241 pinctrl-single,function-mask = <0x00000007>; 242 }; 243 244 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 245 main_timerio_output: pinctrl@104280 { 246 compatible = "pinctrl-single"; 247 reg = <0x00 0x104280 0x00 0x20>; 248 #pinctrl-cells = <1>; 249 pinctrl-single,register-width = <32>; 250 pinctrl-single,function-mask = <0x0000001f>; 251 }; 252 253 main_crypto: crypto@4e00000 { 254 compatible = "ti,j721e-sa2ul"; 255 reg = <0x00 0x4e00000 0x00 0x1200>; 256 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 257 #address-cells = <2>; 258 #size-cells = <2>; 259 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 260 261 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 262 <&main_udmap 0x4a41>; 263 dma-names = "tx", "rx1", "rx2"; 264 265 rng: rng@4e10000 { 266 compatible = "inside-secure,safexcel-eip76"; 267 reg = <0x00 0x4e10000 0x00 0x7d>; 268 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 269 }; 270 }; 271 272 main_timer0: timer@2400000 { 273 compatible = "ti,am654-timer"; 274 reg = <0x00 0x2400000 0x00 0x400>; 275 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&k3_clks 97 2>; 277 clock-names = "fck"; 278 assigned-clocks = <&k3_clks 97 2>; 279 assigned-clock-parents = <&k3_clks 97 3>; 280 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 281 ti,timer-pwm; 282 }; 283 284 main_timer1: timer@2410000 { 285 compatible = "ti,am654-timer"; 286 reg = <0x00 0x2410000 0x00 0x400>; 287 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&k3_clks 98 2>; 289 clock-names = "fck"; 290 assigned-clocks = <&k3_clks 98 2>; 291 assigned-clock-parents = <&k3_clks 98 3>; 292 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 293 ti,timer-pwm; 294 }; 295 296 main_timer2: timer@2420000 { 297 compatible = "ti,am654-timer"; 298 reg = <0x00 0x2420000 0x00 0x400>; 299 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&k3_clks 99 2>; 301 clock-names = "fck"; 302 assigned-clocks = <&k3_clks 99 2>; 303 assigned-clock-parents = <&k3_clks 99 3>; 304 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 305 ti,timer-pwm; 306 }; 307 308 main_timer3: timer@2430000 { 309 compatible = "ti,am654-timer"; 310 reg = <0x00 0x2430000 0x00 0x400>; 311 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&k3_clks 100 2>; 313 clock-names = "fck"; 314 assigned-clocks = <&k3_clks 100 2>; 315 assigned-clock-parents = <&k3_clks 100 3>; 316 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 317 ti,timer-pwm; 318 }; 319 320 main_timer4: timer@2440000 { 321 compatible = "ti,am654-timer"; 322 reg = <0x00 0x2440000 0x00 0x400>; 323 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&k3_clks 101 2>; 325 clock-names = "fck"; 326 assigned-clocks = <&k3_clks 101 2>; 327 assigned-clock-parents = <&k3_clks 101 3>; 328 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 329 ti,timer-pwm; 330 }; 331 332 main_timer5: timer@2450000 { 333 compatible = "ti,am654-timer"; 334 reg = <0x00 0x2450000 0x00 0x400>; 335 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&k3_clks 102 2>; 337 clock-names = "fck"; 338 assigned-clocks = <&k3_clks 102 2>; 339 assigned-clock-parents = <&k3_clks 102 3>; 340 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 341 ti,timer-pwm; 342 }; 343 344 main_timer6: timer@2460000 { 345 compatible = "ti,am654-timer"; 346 reg = <0x00 0x2460000 0x00 0x400>; 347 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&k3_clks 103 2>; 349 clock-names = "fck"; 350 assigned-clocks = <&k3_clks 103 2>; 351 assigned-clock-parents = <&k3_clks 103 3>; 352 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 353 ti,timer-pwm; 354 }; 355 356 main_timer7: timer@2470000 { 357 compatible = "ti,am654-timer"; 358 reg = <0x00 0x2470000 0x00 0x400>; 359 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&k3_clks 104 2>; 361 clock-names = "fck"; 362 assigned-clocks = <&k3_clks 104 2>; 363 assigned-clock-parents = <&k3_clks 104 3>; 364 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 365 ti,timer-pwm; 366 }; 367 368 main_timer8: timer@2480000 { 369 compatible = "ti,am654-timer"; 370 reg = <0x00 0x2480000 0x00 0x400>; 371 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&k3_clks 105 2>; 373 clock-names = "fck"; 374 assigned-clocks = <&k3_clks 105 2>; 375 assigned-clock-parents = <&k3_clks 105 3>; 376 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 377 ti,timer-pwm; 378 }; 379 380 main_timer9: timer@2490000 { 381 compatible = "ti,am654-timer"; 382 reg = <0x00 0x2490000 0x00 0x400>; 383 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&k3_clks 106 2>; 385 clock-names = "fck"; 386 assigned-clocks = <&k3_clks 106 2>; 387 assigned-clock-parents = <&k3_clks 106 3>; 388 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 389 ti,timer-pwm; 390 }; 391 392 main_timer10: timer@24a0000 { 393 compatible = "ti,am654-timer"; 394 reg = <0x00 0x24a0000 0x00 0x400>; 395 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&k3_clks 107 2>; 397 clock-names = "fck"; 398 assigned-clocks = <&k3_clks 107 2>; 399 assigned-clock-parents = <&k3_clks 107 3>; 400 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 401 ti,timer-pwm; 402 }; 403 404 main_timer11: timer@24b0000 { 405 compatible = "ti,am654-timer"; 406 reg = <0x00 0x24b0000 0x00 0x400>; 407 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&k3_clks 108 2>; 409 clock-names = "fck"; 410 assigned-clocks = <&k3_clks 108 2>; 411 assigned-clock-parents = <&k3_clks 108 3>; 412 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 413 ti,timer-pwm; 414 }; 415 416 main_timer12: timer@24c0000 { 417 compatible = "ti,am654-timer"; 418 reg = <0x00 0x24c0000 0x00 0x400>; 419 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&k3_clks 109 2>; 421 clock-names = "fck"; 422 assigned-clocks = <&k3_clks 109 2>; 423 assigned-clock-parents = <&k3_clks 109 3>; 424 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 425 ti,timer-pwm; 426 }; 427 428 main_timer13: timer@24d0000 { 429 compatible = "ti,am654-timer"; 430 reg = <0x00 0x24d0000 0x00 0x400>; 431 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&k3_clks 110 2>; 433 clock-names = "fck"; 434 assigned-clocks = <&k3_clks 110 2>; 435 assigned-clock-parents = <&k3_clks 110 3>; 436 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 437 ti,timer-pwm; 438 }; 439 440 main_timer14: timer@24e0000 { 441 compatible = "ti,am654-timer"; 442 reg = <0x00 0x24e0000 0x00 0x400>; 443 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&k3_clks 111 2>; 445 clock-names = "fck"; 446 assigned-clocks = <&k3_clks 111 2>; 447 assigned-clock-parents = <&k3_clks 111 3>; 448 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 449 ti,timer-pwm; 450 }; 451 452 main_timer15: timer@24f0000 { 453 compatible = "ti,am654-timer"; 454 reg = <0x00 0x24f0000 0x00 0x400>; 455 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&k3_clks 112 2>; 457 clock-names = "fck"; 458 assigned-clocks = <&k3_clks 112 2>; 459 assigned-clock-parents = <&k3_clks 112 3>; 460 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 461 ti,timer-pwm; 462 }; 463 464 main_timer16: timer@2500000 { 465 compatible = "ti,am654-timer"; 466 reg = <0x00 0x2500000 0x00 0x400>; 467 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&k3_clks 113 2>; 469 clock-names = "fck"; 470 assigned-clocks = <&k3_clks 113 2>; 471 assigned-clock-parents = <&k3_clks 113 3>; 472 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 473 ti,timer-pwm; 474 }; 475 476 main_timer17: timer@2510000 { 477 compatible = "ti,am654-timer"; 478 reg = <0x00 0x2510000 0x00 0x400>; 479 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&k3_clks 114 2>; 481 clock-names = "fck"; 482 assigned-clocks = <&k3_clks 114 2>; 483 assigned-clock-parents = <&k3_clks 114 3>; 484 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 485 ti,timer-pwm; 486 }; 487 488 main_timer18: timer@2520000 { 489 compatible = "ti,am654-timer"; 490 reg = <0x00 0x2520000 0x00 0x400>; 491 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&k3_clks 115 2>; 493 clock-names = "fck"; 494 assigned-clocks = <&k3_clks 115 2>; 495 assigned-clock-parents = <&k3_clks 115 3>; 496 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 497 ti,timer-pwm; 498 }; 499 500 main_timer19: timer@2530000 { 501 compatible = "ti,am654-timer"; 502 reg = <0x00 0x2530000 0x00 0x400>; 503 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&k3_clks 116 2>; 505 clock-names = "fck"; 506 assigned-clocks = <&k3_clks 116 2>; 507 assigned-clock-parents = <&k3_clks 116 3>; 508 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 509 ti,timer-pwm; 510 }; 511 512 main_uart0: serial@2800000 { 513 compatible = "ti,j721e-uart", "ti,am654-uart"; 514 reg = <0x00 0x02800000 0x00 0x200>; 515 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&k3_clks 146 0>; 517 clock-names = "fclk"; 518 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 519 status = "disabled"; 520 }; 521 522 main_uart1: serial@2810000 { 523 compatible = "ti,j721e-uart", "ti,am654-uart"; 524 reg = <0x00 0x02810000 0x00 0x200>; 525 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&k3_clks 388 0>; 527 clock-names = "fclk"; 528 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 529 status = "disabled"; 530 }; 531 532 main_uart2: serial@2820000 { 533 compatible = "ti,j721e-uart", "ti,am654-uart"; 534 reg = <0x00 0x02820000 0x00 0x200>; 535 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&k3_clks 389 0>; 537 clock-names = "fclk"; 538 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 539 status = "disabled"; 540 }; 541 542 main_uart3: serial@2830000 { 543 compatible = "ti,j721e-uart", "ti,am654-uart"; 544 reg = <0x00 0x02830000 0x00 0x200>; 545 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&k3_clks 390 0>; 547 clock-names = "fclk"; 548 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 549 status = "disabled"; 550 }; 551 552 main_uart4: serial@2840000 { 553 compatible = "ti,j721e-uart", "ti,am654-uart"; 554 reg = <0x00 0x02840000 0x00 0x200>; 555 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&k3_clks 391 0>; 557 clock-names = "fclk"; 558 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 559 status = "disabled"; 560 }; 561 562 main_uart5: serial@2850000 { 563 compatible = "ti,j721e-uart", "ti,am654-uart"; 564 reg = <0x00 0x02850000 0x00 0x200>; 565 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&k3_clks 392 0>; 567 clock-names = "fclk"; 568 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 569 status = "disabled"; 570 }; 571 572 main_uart6: serial@2860000 { 573 compatible = "ti,j721e-uart", "ti,am654-uart"; 574 reg = <0x00 0x02860000 0x00 0x200>; 575 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&k3_clks 393 0>; 577 clock-names = "fclk"; 578 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 579 status = "disabled"; 580 }; 581 582 main_uart7: serial@2870000 { 583 compatible = "ti,j721e-uart", "ti,am654-uart"; 584 reg = <0x00 0x02870000 0x00 0x200>; 585 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&k3_clks 394 0>; 587 clock-names = "fclk"; 588 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 589 status = "disabled"; 590 }; 591 592 main_uart8: serial@2880000 { 593 compatible = "ti,j721e-uart", "ti,am654-uart"; 594 reg = <0x00 0x02880000 0x00 0x200>; 595 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&k3_clks 395 0>; 597 clock-names = "fclk"; 598 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 599 status = "disabled"; 600 }; 601 602 main_uart9: serial@2890000 { 603 compatible = "ti,j721e-uart", "ti,am654-uart"; 604 reg = <0x00 0x02890000 0x00 0x200>; 605 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&k3_clks 396 0>; 607 clock-names = "fclk"; 608 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 609 status = "disabled"; 610 }; 611 612 main_gpio0: gpio@600000 { 613 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 614 reg = <0x00 0x00600000 0x00 0x100>; 615 gpio-controller; 616 #gpio-cells = <2>; 617 interrupt-parent = <&main_gpio_intr>; 618 interrupts = <145>, <146>, <147>, <148>, <149>; 619 interrupt-controller; 620 #interrupt-cells = <2>; 621 ti,ngpio = <66>; 622 ti,davinci-gpio-unbanked = <0>; 623 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 624 clocks = <&k3_clks 163 0>; 625 clock-names = "gpio"; 626 status = "disabled"; 627 }; 628 629 main_gpio2: gpio@610000 { 630 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 631 reg = <0x00 0x00610000 0x00 0x100>; 632 gpio-controller; 633 #gpio-cells = <2>; 634 interrupt-parent = <&main_gpio_intr>; 635 interrupts = <154>, <155>, <156>, <157>, <158>; 636 interrupt-controller; 637 #interrupt-cells = <2>; 638 ti,ngpio = <66>; 639 ti,davinci-gpio-unbanked = <0>; 640 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 641 clocks = <&k3_clks 164 0>; 642 clock-names = "gpio"; 643 status = "disabled"; 644 }; 645 646 main_gpio4: gpio@620000 { 647 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 648 reg = <0x00 0x00620000 0x00 0x100>; 649 gpio-controller; 650 #gpio-cells = <2>; 651 interrupt-parent = <&main_gpio_intr>; 652 interrupts = <163>, <164>, <165>, <166>, <167>; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 ti,ngpio = <66>; 656 ti,davinci-gpio-unbanked = <0>; 657 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 658 clocks = <&k3_clks 165 0>; 659 clock-names = "gpio"; 660 status = "disabled"; 661 }; 662 663 main_gpio6: gpio@630000 { 664 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 665 reg = <0x00 0x00630000 0x00 0x100>; 666 gpio-controller; 667 #gpio-cells = <2>; 668 interrupt-parent = <&main_gpio_intr>; 669 interrupts = <172>, <173>, <174>, <175>, <176>; 670 interrupt-controller; 671 #interrupt-cells = <2>; 672 ti,ngpio = <66>; 673 ti,davinci-gpio-unbanked = <0>; 674 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 675 clocks = <&k3_clks 166 0>; 676 clock-names = "gpio"; 677 status = "disabled"; 678 }; 679 680 usbss0: usb@4104000 { 681 bootph-all; 682 compatible = "ti,j721e-usb"; 683 reg = <0x00 0x4104000 0x00 0x100>; 684 dma-coherent; 685 power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; 686 clocks = <&k3_clks 398 21>, <&k3_clks 398 2>; 687 clock-names = "ref", "lpm"; 688 assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */ 689 assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */ 690 #address-cells = <2>; 691 #size-cells = <2>; 692 ranges; 693 694 status = "disabled"; /* Needs lane config */ 695 696 usb0: usb@6000000 { 697 bootph-all; 698 compatible = "cdns,usb3"; 699 reg = <0x00 0x6000000 0x00 0x10000>, 700 <0x00 0x6010000 0x00 0x10000>, 701 <0x00 0x6020000 0x00 0x10000>; 702 reg-names = "otg", "xhci", "dev"; 703 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 704 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 705 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 706 interrupt-names = "host", 707 "peripheral", 708 "otg"; 709 }; 710 }; 711 712 main_i2c0: i2c@2000000 { 713 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 714 reg = <0x00 0x02000000 0x00 0x100>; 715 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 clocks = <&k3_clks 270 2>; 719 clock-names = "fck"; 720 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 721 status = "disabled"; 722 }; 723 724 main_i2c1: i2c@2010000 { 725 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 726 reg = <0x00 0x02010000 0x00 0x100>; 727 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 clocks = <&k3_clks 271 2>; 731 clock-names = "fck"; 732 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 733 status = "disabled"; 734 }; 735 736 main_i2c2: i2c@2020000 { 737 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 738 reg = <0x00 0x02020000 0x00 0x100>; 739 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 clocks = <&k3_clks 272 2>; 743 clock-names = "fck"; 744 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 745 status = "disabled"; 746 }; 747 748 main_i2c3: i2c@2030000 { 749 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 750 reg = <0x00 0x02030000 0x00 0x100>; 751 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 clocks = <&k3_clks 273 2>; 755 clock-names = "fck"; 756 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 757 status = "disabled"; 758 }; 759 760 main_i2c4: i2c@2040000 { 761 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 762 reg = <0x00 0x02040000 0x00 0x100>; 763 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 clocks = <&k3_clks 274 2>; 767 clock-names = "fck"; 768 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 769 status = "disabled"; 770 }; 771 772 main_i2c5: i2c@2050000 { 773 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 774 reg = <0x00 0x02050000 0x00 0x100>; 775 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 clocks = <&k3_clks 275 2>; 779 clock-names = "fck"; 780 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 781 status = "disabled"; 782 }; 783 784 main_i2c6: i2c@2060000 { 785 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 786 reg = <0x00 0x02060000 0x00 0x100>; 787 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 clocks = <&k3_clks 276 2>; 791 clock-names = "fck"; 792 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 793 status = "disabled"; 794 }; 795 796 ti_csi2rx0: ticsi2rx@4500000 { 797 compatible = "ti,j721e-csi2rx-shim"; 798 reg = <0x00 0x04500000 0x00 0x00001000>; 799 ranges; 800 #address-cells = <2>; 801 #size-cells = <2>; 802 dmas = <&main_bcdma_csi 0 0x4940 0>; 803 dma-names = "rx0"; 804 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 805 status = "disabled"; 806 807 cdns_csi2rx0: csi-bridge@4504000 { 808 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 809 reg = <0x00 0x04504000 0x00 0x00001000>; 810 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, 811 <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; 812 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 813 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 814 phys = <&dphy0>; 815 phy-names = "dphy"; 816 817 ports { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 821 csi0_port0: port@0 { 822 reg = <0>; 823 status = "disabled"; 824 }; 825 826 csi0_port1: port@1 { 827 reg = <1>; 828 status = "disabled"; 829 }; 830 831 csi0_port2: port@2 { 832 reg = <2>; 833 status = "disabled"; 834 }; 835 836 csi0_port3: port@3 { 837 reg = <3>; 838 status = "disabled"; 839 }; 840 841 csi0_port4: port@4 { 842 reg = <4>; 843 status = "disabled"; 844 }; 845 }; 846 }; 847 }; 848 849 ti_csi2rx1: ticsi2rx@4510000 { 850 compatible = "ti,j721e-csi2rx-shim"; 851 reg = <0x00 0x04510000 0x00 0x1000>; 852 ranges; 853 #address-cells = <2>; 854 #size-cells = <2>; 855 dmas = <&main_bcdma_csi 0 0x4960 0>; 856 dma-names = "rx0"; 857 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 858 status = "disabled"; 859 860 cdns_csi2rx1: csi-bridge@4514000 { 861 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 862 reg = <0x00 0x04514000 0x00 0x00001000>; 863 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, 864 <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; 865 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 866 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 867 phys = <&dphy1>; 868 phy-names = "dphy"; 869 ports { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 csi1_port0: port@0 { 874 reg = <0>; 875 status = "disabled"; 876 }; 877 878 csi1_port1: port@1 { 879 reg = <1>; 880 status = "disabled"; 881 }; 882 883 csi1_port2: port@2 { 884 reg = <2>; 885 status = "disabled"; 886 }; 887 888 csi1_port3: port@3 { 889 reg = <3>; 890 status = "disabled"; 891 }; 892 893 csi1_port4: port@4 { 894 reg = <4>; 895 status = "disabled"; 896 }; 897 }; 898 }; 899 }; 900 901 ti_csi2rx2: ticsi2rx@4520000 { 902 compatible = "ti,j721e-csi2rx-shim"; 903 reg = <0x00 0x04520000 0x00 0x00001000>; 904 ranges; 905 #address-cells = <2>; 906 #size-cells = <2>; 907 dmas = <&main_bcdma_csi 0 0x4980 0>; 908 dma-names = "rx0"; 909 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 910 status = "disabled"; 911 912 cdns_csi2rx2: csi-bridge@4524000 { 913 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 914 reg = <0x00 0x04524000 0x00 0x00001000>; 915 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, 916 <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; 917 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 918 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 919 phys = <&dphy2>; 920 phy-names = "dphy"; 921 922 ports { 923 #address-cells = <1>; 924 #size-cells = <0>; 925 926 csi2_port0: port@0 { 927 reg = <0>; 928 status = "disabled"; 929 }; 930 931 csi2_port1: port@1 { 932 reg = <1>; 933 status = "disabled"; 934 }; 935 936 csi2_port2: port@2 { 937 reg = <2>; 938 status = "disabled"; 939 }; 940 941 csi2_port3: port@3 { 942 reg = <3>; 943 status = "disabled"; 944 }; 945 946 csi2_port4: port@4 { 947 reg = <4>; 948 status = "disabled"; 949 }; 950 }; 951 }; 952 }; 953 954 dphy0: phy@4580000 { 955 compatible = "cdns,dphy-rx"; 956 reg = <0x00 0x04580000 0x00 0x00001100>; 957 #phy-cells = <0>; 958 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; 959 status = "disabled"; 960 }; 961 962 dphy1: phy@4590000 { 963 compatible = "cdns,dphy-rx"; 964 reg = <0x00 0x04590000 0x00 0x00001100>; 965 #phy-cells = <0>; 966 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; 967 status = "disabled"; 968 }; 969 970 dphy2: phy@45a0000 { 971 compatible = "cdns,dphy-rx"; 972 reg = <0x00 0x045a0000 0x00 0x00001100>; 973 #phy-cells = <0>; 974 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 975 status = "disabled"; 976 }; 977 978 vpu0: video-codec@4210000 { 979 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 980 reg = <0x00 0x4210000 0x00 0x10000>; 981 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&k3_clks 241 2>; 983 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 984 }; 985 986 vpu1: video-codec@4220000 { 987 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 988 reg = <0x00 0x4220000 0x00 0x10000>; 989 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&k3_clks 242 2>; 991 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 992 }; 993 994 main_sdhci0: mmc@4f80000 { 995 compatible = "ti,j721e-sdhci-8bit"; 996 reg = <0x00 0x04f80000 0x00 0x1000>, 997 <0x00 0x04f88000 0x00 0x400>; 998 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 999 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 1000 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 1001 clock-names = "clk_ahb", "clk_xin"; 1002 assigned-clocks = <&k3_clks 140 2>; 1003 assigned-clock-parents = <&k3_clks 140 3>; 1004 bus-width = <8>; 1005 ti,otap-del-sel-legacy = <0x0>; 1006 ti,otap-del-sel-mmc-hs = <0x0>; 1007 ti,otap-del-sel-ddr52 = <0x6>; 1008 ti,otap-del-sel-hs200 = <0x8>; 1009 ti,otap-del-sel-hs400 = <0x5>; 1010 ti,itap-del-sel-legacy = <0x10>; 1011 ti,itap-del-sel-mmc-hs = <0xa>; 1012 ti,strobe-sel = <0x77>; 1013 ti,clkbuf-sel = <0x7>; 1014 ti,trm-icp = <0x8>; 1015 mmc-ddr-1_8v; 1016 mmc-hs200-1_8v; 1017 mmc-hs400-1_8v; 1018 dma-coherent; 1019 status = "disabled"; 1020 }; 1021 1022 main_sdhci1: mmc@4fb0000 { 1023 compatible = "ti,j721e-sdhci-4bit"; 1024 reg = <0x00 0x04fb0000 0x00 0x1000>, 1025 <0x00 0x04fb8000 0x00 0x400>; 1026 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 1028 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 1029 clock-names = "clk_ahb", "clk_xin"; 1030 assigned-clocks = <&k3_clks 141 4>; 1031 assigned-clock-parents = <&k3_clks 141 5>; 1032 bus-width = <4>; 1033 ti,otap-del-sel-legacy = <0x0>; 1034 ti,otap-del-sel-sd-hs = <0x0>; 1035 ti,otap-del-sel-sdr12 = <0xf>; 1036 ti,otap-del-sel-sdr25 = <0xf>; 1037 ti,otap-del-sel-sdr50 = <0xc>; 1038 ti,otap-del-sel-sdr104 = <0x5>; 1039 ti,otap-del-sel-ddr50 = <0xc>; 1040 ti,itap-del-sel-legacy = <0x0>; 1041 ti,itap-del-sel-sd-hs = <0x0>; 1042 ti,itap-del-sel-sdr12 = <0x0>; 1043 ti,itap-del-sel-sdr25 = <0x0>; 1044 ti,itap-del-sel-ddr50 = <0x2>; 1045 ti,clkbuf-sel = <0x7>; 1046 ti,trm-icp = <0x8>; 1047 dma-coherent; 1048 status = "disabled"; 1049 }; 1050 1051 pcie0_rc: pcie@2900000 { 1052 compatible = "ti,j784s4-pcie-host"; 1053 reg = <0x00 0x02900000 0x00 0x1000>, 1054 <0x00 0x02907000 0x00 0x400>, 1055 <0x00 0x0d000000 0x00 0x00800000>, 1056 <0x00 0x10000000 0x00 0x00001000>; 1057 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1058 interrupt-names = "link_state"; 1059 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 1060 device_type = "pci"; 1061 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 1062 max-link-speed = <3>; 1063 num-lanes = <4>; 1064 power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; 1065 clocks = <&k3_clks 332 0>; 1066 clock-names = "fck"; 1067 #address-cells = <3>; 1068 #size-cells = <2>; 1069 bus-range = <0x0 0xff>; 1070 vendor-id = <0x104c>; 1071 device-id = <0xb012>; 1072 msi-map = <0x0 &gic_its 0x0 0x10000>; 1073 dma-coherent; 1074 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 1075 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 1076 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1077 status = "disabled"; 1078 }; 1079 1080 pcie1_rc: pcie@2910000 { 1081 compatible = "ti,j784s4-pcie-host"; 1082 reg = <0x00 0x02910000 0x00 0x1000>, 1083 <0x00 0x02917000 0x00 0x400>, 1084 <0x00 0x0d800000 0x00 0x00800000>, 1085 <0x00 0x18000000 0x00 0x00001000>; 1086 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1087 interrupt-names = "link_state"; 1088 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1089 device_type = "pci"; 1090 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 1091 max-link-speed = <3>; 1092 num-lanes = <4>; 1093 power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; 1094 clocks = <&k3_clks 333 0>; 1095 clock-names = "fck"; 1096 #address-cells = <3>; 1097 #size-cells = <2>; 1098 bus-range = <0x0 0xff>; 1099 vendor-id = <0x104c>; 1100 device-id = <0xb012>; 1101 msi-map = <0x0 &gic_its 0x10000 0x10000>; 1102 dma-coherent; 1103 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1104 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1106 status = "disabled"; 1107 }; 1108 1109 serdes_wiz0: wiz@5060000 { 1110 compatible = "ti,j784s4-wiz-10g"; 1111 #address-cells = <1>; 1112 #size-cells = <1>; 1113 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 1114 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 1115 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1116 assigned-clocks = <&k3_clks 404 6>; 1117 assigned-clock-parents = <&k3_clks 404 10>; 1118 num-lanes = <4>; 1119 #reset-cells = <1>; 1120 #clock-cells = <1>; 1121 ranges = <0x5060000 0x00 0x5060000 0x10000>; 1122 status = "disabled"; 1123 1124 serdes0: serdes@5060000 { 1125 compatible = "ti,j721e-serdes-10g"; 1126 reg = <0x05060000 0x010000>; 1127 reg-names = "torrent_phy"; 1128 resets = <&serdes_wiz0 0>; 1129 reset-names = "torrent_reset"; 1130 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1131 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1132 clock-names = "refclk", "phy_en_refclk"; 1133 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1134 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1135 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1136 assigned-clock-parents = <&k3_clks 404 6>, 1137 <&k3_clks 404 6>, 1138 <&k3_clks 404 6>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 #clock-cells = <1>; 1142 status = "disabled"; 1143 }; 1144 }; 1145 1146 serdes_wiz1: wiz@5070000 { 1147 compatible = "ti,j784s4-wiz-10g"; 1148 #address-cells = <1>; 1149 #size-cells = <1>; 1150 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 1151 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 1152 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1153 assigned-clocks = <&k3_clks 405 6>; 1154 assigned-clock-parents = <&k3_clks 405 10>; 1155 num-lanes = <4>; 1156 #reset-cells = <1>; 1157 #clock-cells = <1>; 1158 ranges = <0x05070000 0x00 0x05070000 0x10000>; 1159 status = "disabled"; 1160 1161 serdes1: serdes@5070000 { 1162 compatible = "ti,j721e-serdes-10g"; 1163 reg = <0x05070000 0x010000>; 1164 reg-names = "torrent_phy"; 1165 resets = <&serdes_wiz1 0>; 1166 reset-names = "torrent_reset"; 1167 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1168 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 1169 clock-names = "refclk", "phy_en_refclk"; 1170 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1171 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 1172 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 1173 assigned-clock-parents = <&k3_clks 405 6>, 1174 <&k3_clks 405 6>, 1175 <&k3_clks 405 6>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 #clock-cells = <1>; 1179 status = "disabled"; 1180 }; 1181 }; 1182 1183 serdes_wiz4: wiz@5050000 { 1184 compatible = "ti,j784s4-wiz-10g"; 1185 #address-cells = <1>; 1186 #size-cells = <1>; 1187 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 1188 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 1189 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1190 assigned-clocks = <&k3_clks 407 6>; 1191 assigned-clock-parents = <&k3_clks 407 10>; 1192 num-lanes = <4>; 1193 #reset-cells = <1>; 1194 #clock-cells = <1>; 1195 ranges = <0x05050000 0x00 0x05050000 0x10000>, 1196 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 1197 status = "disabled"; 1198 1199 serdes4: serdes@5050000 { 1200 /* 1201 * Note: we also map DPTX PHY registers as the Torrent 1202 * needs to manage those. 1203 */ 1204 compatible = "ti,j721e-serdes-10g"; 1205 reg = <0x05050000 0x010000>, 1206 <0x0a030a00 0x40>; /* DPTX PHY */ 1207 reg-names = "torrent_phy"; 1208 resets = <&serdes_wiz4 0>; 1209 reset-names = "torrent_reset"; 1210 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1211 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 1212 clock-names = "refclk", "phy_en_refclk"; 1213 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1214 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1215 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1216 assigned-clock-parents = <&k3_clks 407 6>, 1217 <&k3_clks 407 6>, 1218 <&k3_clks 407 6>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 #clock-cells = <1>; 1222 status = "disabled"; 1223 }; 1224 }; 1225 1226 main_navss: bus@30000000 { 1227 bootph-all; 1228 compatible = "simple-bus"; 1229 #address-cells = <2>; 1230 #size-cells = <2>; 1231 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 1232 ti,sci-dev-id = <280>; 1233 dma-coherent; 1234 dma-ranges; 1235 1236 main_navss_intr: interrupt-controller@310e0000 { 1237 compatible = "ti,sci-intr"; 1238 reg = <0x00 0x310e0000 0x00 0x4000>; 1239 ti,intr-trigger-type = <4>; 1240 interrupt-controller; 1241 interrupt-parent = <&gic500>; 1242 #interrupt-cells = <1>; 1243 ti,sci = <&sms>; 1244 ti,sci-dev-id = <283>; 1245 ti,interrupt-ranges = <0 64 64>, 1246 <64 448 64>, 1247 <128 672 64>; 1248 }; 1249 1250 main_udmass_inta: msi-controller@33d00000 { 1251 compatible = "ti,sci-inta"; 1252 reg = <0x00 0x33d00000 0x00 0x100000>; 1253 interrupt-controller; 1254 #interrupt-cells = <0>; 1255 interrupt-parent = <&main_navss_intr>; 1256 msi-controller; 1257 ti,sci = <&sms>; 1258 ti,sci-dev-id = <321>; 1259 ti,interrupt-ranges = <0 0 256>; 1260 ti,unmapped-event-sources = <&main_bcdma_csi>; 1261 }; 1262 1263 secure_proxy_main: mailbox@32c00000 { 1264 bootph-all; 1265 compatible = "ti,am654-secure-proxy"; 1266 #mbox-cells = <1>; 1267 reg-names = "target_data", "rt", "scfg"; 1268 reg = <0x00 0x32c00000 0x00 0x100000>, 1269 <0x00 0x32400000 0x00 0x100000>, 1270 <0x00 0x32800000 0x00 0x100000>; 1271 interrupt-names = "rx_011"; 1272 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1273 }; 1274 1275 hwspinlock: hwlock@30e00000 { 1276 compatible = "ti,am654-hwspinlock"; 1277 reg = <0x00 0x30e00000 0x00 0x1000>; 1278 #hwlock-cells = <1>; 1279 }; 1280 1281 mailbox0_cluster0: mailbox@31f80000 { 1282 compatible = "ti,am654-mailbox"; 1283 reg = <0x00 0x31f80000 0x00 0x200>; 1284 #mbox-cells = <1>; 1285 ti,mbox-num-users = <4>; 1286 ti,mbox-num-fifos = <16>; 1287 interrupt-parent = <&main_navss_intr>; 1288 status = "disabled"; 1289 }; 1290 1291 mailbox0_cluster1: mailbox@31f81000 { 1292 compatible = "ti,am654-mailbox"; 1293 reg = <0x00 0x31f81000 0x00 0x200>; 1294 #mbox-cells = <1>; 1295 ti,mbox-num-users = <4>; 1296 ti,mbox-num-fifos = <16>; 1297 interrupt-parent = <&main_navss_intr>; 1298 status = "disabled"; 1299 }; 1300 1301 mailbox0_cluster2: mailbox@31f82000 { 1302 compatible = "ti,am654-mailbox"; 1303 reg = <0x00 0x31f82000 0x00 0x200>; 1304 #mbox-cells = <1>; 1305 ti,mbox-num-users = <4>; 1306 ti,mbox-num-fifos = <16>; 1307 interrupt-parent = <&main_navss_intr>; 1308 status = "disabled"; 1309 }; 1310 1311 mailbox0_cluster3: mailbox@31f83000 { 1312 compatible = "ti,am654-mailbox"; 1313 reg = <0x00 0x31f83000 0x00 0x200>; 1314 #mbox-cells = <1>; 1315 ti,mbox-num-users = <4>; 1316 ti,mbox-num-fifos = <16>; 1317 interrupt-parent = <&main_navss_intr>; 1318 status = "disabled"; 1319 }; 1320 1321 mailbox0_cluster4: mailbox@31f84000 { 1322 compatible = "ti,am654-mailbox"; 1323 reg = <0x00 0x31f84000 0x00 0x200>; 1324 #mbox-cells = <1>; 1325 ti,mbox-num-users = <4>; 1326 ti,mbox-num-fifos = <16>; 1327 interrupt-parent = <&main_navss_intr>; 1328 status = "disabled"; 1329 }; 1330 1331 mailbox0_cluster5: mailbox@31f85000 { 1332 compatible = "ti,am654-mailbox"; 1333 reg = <0x00 0x31f85000 0x00 0x200>; 1334 #mbox-cells = <1>; 1335 ti,mbox-num-users = <4>; 1336 ti,mbox-num-fifos = <16>; 1337 interrupt-parent = <&main_navss_intr>; 1338 status = "disabled"; 1339 }; 1340 1341 mailbox0_cluster6: mailbox@31f86000 { 1342 compatible = "ti,am654-mailbox"; 1343 reg = <0x00 0x31f86000 0x00 0x200>; 1344 #mbox-cells = <1>; 1345 ti,mbox-num-users = <4>; 1346 ti,mbox-num-fifos = <16>; 1347 interrupt-parent = <&main_navss_intr>; 1348 status = "disabled"; 1349 }; 1350 1351 mailbox0_cluster7: mailbox@31f87000 { 1352 compatible = "ti,am654-mailbox"; 1353 reg = <0x00 0x31f87000 0x00 0x200>; 1354 #mbox-cells = <1>; 1355 ti,mbox-num-users = <4>; 1356 ti,mbox-num-fifos = <16>; 1357 interrupt-parent = <&main_navss_intr>; 1358 status = "disabled"; 1359 }; 1360 1361 mailbox0_cluster8: mailbox@31f88000 { 1362 compatible = "ti,am654-mailbox"; 1363 reg = <0x00 0x31f88000 0x00 0x200>; 1364 #mbox-cells = <1>; 1365 ti,mbox-num-users = <4>; 1366 ti,mbox-num-fifos = <16>; 1367 interrupt-parent = <&main_navss_intr>; 1368 status = "disabled"; 1369 }; 1370 1371 mailbox0_cluster9: mailbox@31f89000 { 1372 compatible = "ti,am654-mailbox"; 1373 reg = <0x00 0x31f89000 0x00 0x200>; 1374 #mbox-cells = <1>; 1375 ti,mbox-num-users = <4>; 1376 ti,mbox-num-fifos = <16>; 1377 interrupt-parent = <&main_navss_intr>; 1378 status = "disabled"; 1379 }; 1380 1381 mailbox0_cluster10: mailbox@31f8a000 { 1382 compatible = "ti,am654-mailbox"; 1383 reg = <0x00 0x31f8a000 0x00 0x200>; 1384 #mbox-cells = <1>; 1385 ti,mbox-num-users = <4>; 1386 ti,mbox-num-fifos = <16>; 1387 interrupt-parent = <&main_navss_intr>; 1388 status = "disabled"; 1389 }; 1390 1391 mailbox0_cluster11: mailbox@31f8b000 { 1392 compatible = "ti,am654-mailbox"; 1393 reg = <0x00 0x31f8b000 0x00 0x200>; 1394 #mbox-cells = <1>; 1395 ti,mbox-num-users = <4>; 1396 ti,mbox-num-fifos = <16>; 1397 interrupt-parent = <&main_navss_intr>; 1398 status = "disabled"; 1399 }; 1400 1401 mailbox1_cluster0: mailbox@31f90000 { 1402 compatible = "ti,am654-mailbox"; 1403 reg = <0x00 0x31f90000 0x00 0x200>; 1404 #mbox-cells = <1>; 1405 ti,mbox-num-users = <4>; 1406 ti,mbox-num-fifos = <16>; 1407 interrupt-parent = <&main_navss_intr>; 1408 status = "disabled"; 1409 }; 1410 1411 mailbox1_cluster1: mailbox@31f91000 { 1412 compatible = "ti,am654-mailbox"; 1413 reg = <0x00 0x31f91000 0x00 0x200>; 1414 #mbox-cells = <1>; 1415 ti,mbox-num-users = <4>; 1416 ti,mbox-num-fifos = <16>; 1417 interrupt-parent = <&main_navss_intr>; 1418 status = "disabled"; 1419 }; 1420 1421 mailbox1_cluster2: mailbox@31f92000 { 1422 compatible = "ti,am654-mailbox"; 1423 reg = <0x00 0x31f92000 0x00 0x200>; 1424 #mbox-cells = <1>; 1425 ti,mbox-num-users = <4>; 1426 ti,mbox-num-fifos = <16>; 1427 interrupt-parent = <&main_navss_intr>; 1428 status = "disabled"; 1429 }; 1430 1431 mailbox1_cluster3: mailbox@31f93000 { 1432 compatible = "ti,am654-mailbox"; 1433 reg = <0x00 0x31f93000 0x00 0x200>; 1434 #mbox-cells = <1>; 1435 ti,mbox-num-users = <4>; 1436 ti,mbox-num-fifos = <16>; 1437 interrupt-parent = <&main_navss_intr>; 1438 status = "disabled"; 1439 }; 1440 1441 mailbox1_cluster4: mailbox@31f94000 { 1442 compatible = "ti,am654-mailbox"; 1443 reg = <0x00 0x31f94000 0x00 0x200>; 1444 #mbox-cells = <1>; 1445 ti,mbox-num-users = <4>; 1446 ti,mbox-num-fifos = <16>; 1447 interrupt-parent = <&main_navss_intr>; 1448 status = "disabled"; 1449 }; 1450 1451 mailbox1_cluster5: mailbox@31f95000 { 1452 compatible = "ti,am654-mailbox"; 1453 reg = <0x00 0x31f95000 0x00 0x200>; 1454 #mbox-cells = <1>; 1455 ti,mbox-num-users = <4>; 1456 ti,mbox-num-fifos = <16>; 1457 interrupt-parent = <&main_navss_intr>; 1458 status = "disabled"; 1459 }; 1460 1461 mailbox1_cluster6: mailbox@31f96000 { 1462 compatible = "ti,am654-mailbox"; 1463 reg = <0x00 0x31f96000 0x00 0x200>; 1464 #mbox-cells = <1>; 1465 ti,mbox-num-users = <4>; 1466 ti,mbox-num-fifos = <16>; 1467 interrupt-parent = <&main_navss_intr>; 1468 status = "disabled"; 1469 }; 1470 1471 mailbox1_cluster7: mailbox@31f97000 { 1472 compatible = "ti,am654-mailbox"; 1473 reg = <0x00 0x31f97000 0x00 0x200>; 1474 #mbox-cells = <1>; 1475 ti,mbox-num-users = <4>; 1476 ti,mbox-num-fifos = <16>; 1477 interrupt-parent = <&main_navss_intr>; 1478 status = "disabled"; 1479 }; 1480 1481 mailbox1_cluster8: mailbox@31f98000 { 1482 compatible = "ti,am654-mailbox"; 1483 reg = <0x00 0x31f98000 0x00 0x200>; 1484 #mbox-cells = <1>; 1485 ti,mbox-num-users = <4>; 1486 ti,mbox-num-fifos = <16>; 1487 interrupt-parent = <&main_navss_intr>; 1488 status = "disabled"; 1489 }; 1490 1491 mailbox1_cluster9: mailbox@31f99000 { 1492 compatible = "ti,am654-mailbox"; 1493 reg = <0x00 0x31f99000 0x00 0x200>; 1494 #mbox-cells = <1>; 1495 ti,mbox-num-users = <4>; 1496 ti,mbox-num-fifos = <16>; 1497 interrupt-parent = <&main_navss_intr>; 1498 status = "disabled"; 1499 }; 1500 1501 mailbox1_cluster10: mailbox@31f9a000 { 1502 compatible = "ti,am654-mailbox"; 1503 reg = <0x00 0x31f9a000 0x00 0x200>; 1504 #mbox-cells = <1>; 1505 ti,mbox-num-users = <4>; 1506 ti,mbox-num-fifos = <16>; 1507 interrupt-parent = <&main_navss_intr>; 1508 status = "disabled"; 1509 }; 1510 1511 mailbox1_cluster11: mailbox@31f9b000 { 1512 compatible = "ti,am654-mailbox"; 1513 reg = <0x00 0x31f9b000 0x00 0x200>; 1514 #mbox-cells = <1>; 1515 ti,mbox-num-users = <4>; 1516 ti,mbox-num-fifos = <16>; 1517 interrupt-parent = <&main_navss_intr>; 1518 status = "disabled"; 1519 }; 1520 1521 main_ringacc: ringacc@3c000000 { 1522 compatible = "ti,am654-navss-ringacc"; 1523 reg = <0x00 0x3c000000 0x00 0x400000>, 1524 <0x00 0x38000000 0x00 0x400000>, 1525 <0x00 0x31120000 0x00 0x100>, 1526 <0x00 0x33000000 0x00 0x40000>, 1527 <0x00 0x31080000 0x00 0x40000>; 1528 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1529 ti,num-rings = <1024>; 1530 ti,sci-rm-range-gp-rings = <0x1>; 1531 ti,sci = <&sms>; 1532 ti,sci-dev-id = <315>; 1533 msi-parent = <&main_udmass_inta>; 1534 }; 1535 1536 main_udmap: dma-controller@31150000 { 1537 compatible = "ti,j721e-navss-main-udmap"; 1538 reg = <0x00 0x31150000 0x00 0x100>, 1539 <0x00 0x34000000 0x00 0x80000>, 1540 <0x00 0x35000000 0x00 0x200000>, 1541 <0x00 0x30b00000 0x00 0x20000>, 1542 <0x00 0x30c00000 0x00 0x8000>, 1543 <0x00 0x30d00000 0x00 0x4000>; 1544 reg-names = "gcfg", "rchanrt", "tchanrt", 1545 "tchan", "rchan", "rflow"; 1546 msi-parent = <&main_udmass_inta>; 1547 #dma-cells = <1>; 1548 1549 ti,sci = <&sms>; 1550 ti,sci-dev-id = <319>; 1551 ti,ringacc = <&main_ringacc>; 1552 1553 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1554 <0x0f>, /* TX_HCHAN */ 1555 <0x10>; /* TX_UHCHAN */ 1556 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1557 <0x0b>, /* RX_HCHAN */ 1558 <0x0c>; /* RX_UHCHAN */ 1559 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1560 }; 1561 1562 main_bcdma_csi: dma-controller@311a0000 { 1563 compatible = "ti,j721s2-dmss-bcdma-csi"; 1564 reg = <0x00 0x311a0000 0x00 0x100>, 1565 <0x00 0x35d00000 0x00 0x20000>, 1566 <0x00 0x35c00000 0x00 0x10000>, 1567 <0x00 0x35e00000 0x00 0x80000>; 1568 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1569 msi-parent = <&main_udmass_inta>; 1570 #dma-cells = <3>; 1571 ti,sci = <&sms>; 1572 ti,sci-dev-id = <281>; 1573 ti,sci-rm-range-rchan = <0x21>; 1574 ti,sci-rm-range-tchan = <0x22>; 1575 }; 1576 1577 cpts@310d0000 { 1578 compatible = "ti,j721e-cpts"; 1579 reg = <0x00 0x310d0000 0x00 0x400>; 1580 reg-names = "cpts"; 1581 clocks = <&k3_clks 282 0>; 1582 clock-names = "cpts"; 1583 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1584 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1585 interrupts-extended = <&main_navss_intr 391>; 1586 interrupt-names = "cpts"; 1587 ti,cpts-periodic-outputs = <6>; 1588 ti,cpts-ext-ts-inputs = <8>; 1589 }; 1590 }; 1591 1592 main_cpsw0: ethernet@c000000 { 1593 compatible = "ti,j784s4-cpswxg-nuss"; 1594 reg = <0x00 0xc000000 0x00 0x200000>; 1595 reg-names = "cpsw_nuss"; 1596 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 1597 #address-cells = <2>; 1598 #size-cells = <2>; 1599 dma-coherent; 1600 clocks = <&k3_clks 64 0>; 1601 clock-names = "fck"; 1602 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1603 1604 dmas = <&main_udmap 0xca00>, 1605 <&main_udmap 0xca01>, 1606 <&main_udmap 0xca02>, 1607 <&main_udmap 0xca03>, 1608 <&main_udmap 0xca04>, 1609 <&main_udmap 0xca05>, 1610 <&main_udmap 0xca06>, 1611 <&main_udmap 0xca07>, 1612 <&main_udmap 0x4a00>; 1613 dma-names = "tx0", "tx1", "tx2", "tx3", 1614 "tx4", "tx5", "tx6", "tx7", 1615 "rx"; 1616 1617 status = "disabled"; 1618 1619 ethernet-ports { 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 1623 main_cpsw0_port1: port@1 { 1624 reg = <1>; 1625 label = "port1"; 1626 ti,mac-only; 1627 status = "disabled"; 1628 }; 1629 1630 main_cpsw0_port2: port@2 { 1631 reg = <2>; 1632 label = "port2"; 1633 ti,mac-only; 1634 status = "disabled"; 1635 }; 1636 1637 main_cpsw0_port3: port@3 { 1638 reg = <3>; 1639 label = "port3"; 1640 ti,mac-only; 1641 status = "disabled"; 1642 }; 1643 1644 main_cpsw0_port4: port@4 { 1645 reg = <4>; 1646 label = "port4"; 1647 ti,mac-only; 1648 status = "disabled"; 1649 }; 1650 1651 main_cpsw0_port5: port@5 { 1652 reg = <5>; 1653 label = "port5"; 1654 ti,mac-only; 1655 status = "disabled"; 1656 }; 1657 1658 main_cpsw0_port6: port@6 { 1659 reg = <6>; 1660 label = "port6"; 1661 ti,mac-only; 1662 status = "disabled"; 1663 }; 1664 1665 main_cpsw0_port7: port@7 { 1666 reg = <7>; 1667 label = "port7"; 1668 ti,mac-only; 1669 status = "disabled"; 1670 }; 1671 1672 main_cpsw0_port8: port@8 { 1673 reg = <8>; 1674 label = "port8"; 1675 ti,mac-only; 1676 status = "disabled"; 1677 }; 1678 }; 1679 1680 main_cpsw0_mdio: mdio@f00 { 1681 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1682 reg = <0x00 0xf00 0x00 0x100>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 clocks = <&k3_clks 64 0>; 1686 clock-names = "fck"; 1687 bus_freq = <1000000>; 1688 status = "disabled"; 1689 }; 1690 1691 cpts@3d000 { 1692 compatible = "ti,am65-cpts"; 1693 reg = <0x00 0x3d000 0x00 0x400>; 1694 clocks = <&k3_clks 64 3>; 1695 clock-names = "cpts"; 1696 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1697 interrupt-names = "cpts"; 1698 ti,cpts-ext-ts-inputs = <4>; 1699 ti,cpts-periodic-outputs = <2>; 1700 }; 1701 }; 1702 1703 main_cpsw1: ethernet@c200000 { 1704 compatible = "ti,j721e-cpsw-nuss"; 1705 reg = <0x00 0xc200000 0x00 0x200000>; 1706 reg-names = "cpsw_nuss"; 1707 ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; 1708 #address-cells = <2>; 1709 #size-cells = <2>; 1710 dma-coherent; 1711 clocks = <&k3_clks 62 0>; 1712 clock-names = "fck"; 1713 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1714 1715 dmas = <&main_udmap 0xc640>, 1716 <&main_udmap 0xc641>, 1717 <&main_udmap 0xc642>, 1718 <&main_udmap 0xc643>, 1719 <&main_udmap 0xc644>, 1720 <&main_udmap 0xc645>, 1721 <&main_udmap 0xc646>, 1722 <&main_udmap 0xc647>, 1723 <&main_udmap 0x4640>; 1724 dma-names = "tx0", "tx1", "tx2", "tx3", 1725 "tx4", "tx5", "tx6", "tx7", 1726 "rx"; 1727 1728 status = "disabled"; 1729 1730 ethernet-ports { 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 1734 main_cpsw1_port1: port@1 { 1735 reg = <1>; 1736 label = "port1"; 1737 phys = <&cpsw1_phy_gmii_sel 1>; 1738 ti,mac-only; 1739 status = "disabled"; 1740 }; 1741 }; 1742 1743 main_cpsw1_mdio: mdio@f00 { 1744 compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; 1745 reg = <0x00 0xf00 0x00 0x100>; 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 clocks = <&k3_clks 62 0>; 1749 clock-names = "fck"; 1750 bus_freq = <1000000>; 1751 status = "disabled"; 1752 }; 1753 1754 cpts@3d000 { 1755 compatible = "ti,am65-cpts"; 1756 reg = <0x00 0x3d000 0x00 0x400>; 1757 clocks = <&k3_clks 62 3>; 1758 clock-names = "cpts"; 1759 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1760 interrupt-names = "cpts"; 1761 ti,cpts-ext-ts-inputs = <4>; 1762 ti,cpts-periodic-outputs = <2>; 1763 }; 1764 }; 1765 1766 main_mcan0: can@2701000 { 1767 compatible = "bosch,m_can"; 1768 reg = <0x00 0x02701000 0x00 0x200>, 1769 <0x00 0x02708000 0x00 0x8000>; 1770 reg-names = "m_can", "message_ram"; 1771 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1772 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1773 clock-names = "hclk", "cclk"; 1774 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1776 interrupt-names = "int0", "int1"; 1777 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1778 status = "disabled"; 1779 }; 1780 1781 main_mcan1: can@2711000 { 1782 compatible = "bosch,m_can"; 1783 reg = <0x00 0x02711000 0x00 0x200>, 1784 <0x00 0x02718000 0x00 0x8000>; 1785 reg-names = "m_can", "message_ram"; 1786 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1787 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1788 clock-names = "hclk", "cclk"; 1789 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1791 interrupt-names = "int0", "int1"; 1792 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1793 status = "disabled"; 1794 }; 1795 1796 main_mcan2: can@2721000 { 1797 compatible = "bosch,m_can"; 1798 reg = <0x00 0x02721000 0x00 0x200>, 1799 <0x00 0x02728000 0x00 0x8000>; 1800 reg-names = "m_can", "message_ram"; 1801 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1802 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1803 clock-names = "hclk", "cclk"; 1804 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1806 interrupt-names = "int0", "int1"; 1807 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1808 status = "disabled"; 1809 }; 1810 1811 main_mcan3: can@2731000 { 1812 compatible = "bosch,m_can"; 1813 reg = <0x00 0x02731000 0x00 0x200>, 1814 <0x00 0x02738000 0x00 0x8000>; 1815 reg-names = "m_can", "message_ram"; 1816 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1817 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1818 clock-names = "hclk", "cclk"; 1819 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1821 interrupt-names = "int0", "int1"; 1822 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1823 status = "disabled"; 1824 }; 1825 1826 main_mcan4: can@2741000 { 1827 compatible = "bosch,m_can"; 1828 reg = <0x00 0x02741000 0x00 0x200>, 1829 <0x00 0x02748000 0x00 0x8000>; 1830 reg-names = "m_can", "message_ram"; 1831 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1832 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1833 clock-names = "hclk", "cclk"; 1834 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1836 interrupt-names = "int0", "int1"; 1837 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1838 status = "disabled"; 1839 }; 1840 1841 main_mcan5: can@2751000 { 1842 compatible = "bosch,m_can"; 1843 reg = <0x00 0x02751000 0x00 0x200>, 1844 <0x00 0x02758000 0x00 0x8000>; 1845 reg-names = "m_can", "message_ram"; 1846 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1847 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1848 clock-names = "hclk", "cclk"; 1849 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1851 interrupt-names = "int0", "int1"; 1852 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1853 status = "disabled"; 1854 }; 1855 1856 main_mcan6: can@2761000 { 1857 compatible = "bosch,m_can"; 1858 reg = <0x00 0x02761000 0x00 0x200>, 1859 <0x00 0x02768000 0x00 0x8000>; 1860 reg-names = "m_can", "message_ram"; 1861 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1862 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1863 clock-names = "hclk", "cclk"; 1864 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1866 interrupt-names = "int0", "int1"; 1867 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1868 status = "disabled"; 1869 }; 1870 1871 main_mcan7: can@2771000 { 1872 compatible = "bosch,m_can"; 1873 reg = <0x00 0x02771000 0x00 0x200>, 1874 <0x00 0x02778000 0x00 0x8000>; 1875 reg-names = "m_can", "message_ram"; 1876 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1877 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1878 clock-names = "hclk", "cclk"; 1879 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1881 interrupt-names = "int0", "int1"; 1882 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1883 status = "disabled"; 1884 }; 1885 1886 main_mcan8: can@2781000 { 1887 compatible = "bosch,m_can"; 1888 reg = <0x00 0x02781000 0x00 0x200>, 1889 <0x00 0x02788000 0x00 0x8000>; 1890 reg-names = "m_can", "message_ram"; 1891 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1892 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1893 clock-names = "hclk", "cclk"; 1894 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1896 interrupt-names = "int0", "int1"; 1897 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1898 status = "disabled"; 1899 }; 1900 1901 main_mcan9: can@2791000 { 1902 compatible = "bosch,m_can"; 1903 reg = <0x00 0x02791000 0x00 0x200>, 1904 <0x00 0x02798000 0x00 0x8000>; 1905 reg-names = "m_can", "message_ram"; 1906 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1907 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1908 clock-names = "hclk", "cclk"; 1909 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1911 interrupt-names = "int0", "int1"; 1912 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1913 status = "disabled"; 1914 }; 1915 1916 main_mcan10: can@27a1000 { 1917 compatible = "bosch,m_can"; 1918 reg = <0x00 0x027a1000 0x00 0x200>, 1919 <0x00 0x027a8000 0x00 0x8000>; 1920 reg-names = "m_can", "message_ram"; 1921 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1922 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1923 clock-names = "hclk", "cclk"; 1924 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1926 interrupt-names = "int0", "int1"; 1927 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1928 status = "disabled"; 1929 }; 1930 1931 main_mcan11: can@27b1000 { 1932 compatible = "bosch,m_can"; 1933 reg = <0x00 0x027b1000 0x00 0x200>, 1934 <0x00 0x027b8000 0x00 0x8000>; 1935 reg-names = "m_can", "message_ram"; 1936 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1937 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1938 clock-names = "hclk", "cclk"; 1939 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1941 interrupt-names = "int0", "int1"; 1942 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1943 status = "disabled"; 1944 }; 1945 1946 main_mcan12: can@27c1000 { 1947 compatible = "bosch,m_can"; 1948 reg = <0x00 0x027c1000 0x00 0x200>, 1949 <0x00 0x027c8000 0x00 0x8000>; 1950 reg-names = "m_can", "message_ram"; 1951 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1952 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1953 clock-names = "hclk", "cclk"; 1954 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1956 interrupt-names = "int0", "int1"; 1957 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1958 status = "disabled"; 1959 }; 1960 1961 main_mcan13: can@27d1000 { 1962 compatible = "bosch,m_can"; 1963 reg = <0x00 0x027d1000 0x00 0x200>, 1964 <0x00 0x027d8000 0x00 0x8000>; 1965 reg-names = "m_can", "message_ram"; 1966 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1967 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1968 clock-names = "hclk", "cclk"; 1969 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1971 interrupt-names = "int0", "int1"; 1972 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1973 status = "disabled"; 1974 }; 1975 1976 main_mcan14: can@2681000 { 1977 compatible = "bosch,m_can"; 1978 reg = <0x00 0x02681000 0x00 0x200>, 1979 <0x00 0x02688000 0x00 0x8000>; 1980 reg-names = "m_can", "message_ram"; 1981 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1982 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1983 clock-names = "hclk", "cclk"; 1984 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1986 interrupt-names = "int0", "int1"; 1987 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1988 status = "disabled"; 1989 }; 1990 1991 main_mcan15: can@2691000 { 1992 compatible = "bosch,m_can"; 1993 reg = <0x00 0x02691000 0x00 0x200>, 1994 <0x00 0x02698000 0x00 0x8000>; 1995 reg-names = "m_can", "message_ram"; 1996 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1997 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 1998 clock-names = "hclk", "cclk"; 1999 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 2001 interrupt-names = "int0", "int1"; 2002 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2003 status = "disabled"; 2004 }; 2005 2006 main_mcan16: can@26a1000 { 2007 compatible = "bosch,m_can"; 2008 reg = <0x00 0x026a1000 0x00 0x200>, 2009 <0x00 0x026a8000 0x00 0x8000>; 2010 reg-names = "m_can", "message_ram"; 2011 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 2012 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 2013 clock-names = "hclk", "cclk"; 2014 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2016 interrupt-names = "int0", "int1"; 2017 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2018 status = "disabled"; 2019 }; 2020 2021 main_mcan17: can@26b1000 { 2022 compatible = "bosch,m_can"; 2023 reg = <0x00 0x026b1000 0x00 0x200>, 2024 <0x00 0x026b8000 0x00 0x8000>; 2025 reg-names = "m_can", "message_ram"; 2026 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 2027 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 2028 clock-names = "hclk", "cclk"; 2029 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 2031 interrupt-names = "int0", "int1"; 2032 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2033 status = "disabled"; 2034 }; 2035 2036 main_spi0: spi@2100000 { 2037 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2038 reg = <0x00 0x02100000 0x00 0x400>; 2039 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 2043 clocks = <&k3_clks 376 1>; 2044 status = "disabled"; 2045 }; 2046 2047 main_spi1: spi@2110000 { 2048 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2049 reg = <0x00 0x02110000 0x00 0x400>; 2050 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 2054 clocks = <&k3_clks 377 1>; 2055 status = "disabled"; 2056 }; 2057 2058 main_spi2: spi@2120000 { 2059 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2060 reg = <0x00 0x02120000 0x00 0x400>; 2061 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2062 #address-cells = <1>; 2063 #size-cells = <0>; 2064 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 2065 clocks = <&k3_clks 378 1>; 2066 status = "disabled"; 2067 }; 2068 2069 main_spi3: spi@2130000 { 2070 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2071 reg = <0x00 0x02130000 0x00 0x400>; 2072 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 2076 clocks = <&k3_clks 379 1>; 2077 status = "disabled"; 2078 }; 2079 2080 main_spi4: spi@2140000 { 2081 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2082 reg = <0x00 0x02140000 0x00 0x400>; 2083 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 2087 clocks = <&k3_clks 380 1>; 2088 status = "disabled"; 2089 }; 2090 2091 main_spi5: spi@2150000 { 2092 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2093 reg = <0x00 0x02150000 0x00 0x400>; 2094 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 2098 clocks = <&k3_clks 381 1>; 2099 status = "disabled"; 2100 }; 2101 2102 main_spi6: spi@2160000 { 2103 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2104 reg = <0x00 0x02160000 0x00 0x400>; 2105 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 2109 clocks = <&k3_clks 382 1>; 2110 status = "disabled"; 2111 }; 2112 2113 main_spi7: spi@2170000 { 2114 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2115 reg = <0x00 0x02170000 0x00 0x400>; 2116 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2117 #address-cells = <1>; 2118 #size-cells = <0>; 2119 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 2120 clocks = <&k3_clks 383 1>; 2121 status = "disabled"; 2122 }; 2123 2124 ufs_wrapper: ufs-wrapper@4e80000 { 2125 compatible = "ti,j721e-ufs"; 2126 reg = <0x00 0x4e80000 0x00 0x100>; 2127 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 2128 clocks = <&k3_clks 387 3>; 2129 assigned-clocks = <&k3_clks 387 3>; 2130 assigned-clock-parents = <&k3_clks 387 6>; 2131 ranges; 2132 #address-cells = <2>; 2133 #size-cells = <2>; 2134 status = "disabled"; 2135 2136 ufs@4e84000 { 2137 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 2138 reg = <0x00 0x4e84000 0x00 0x10000>; 2139 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2140 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 2141 <19200000 19200000>; 2142 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 2143 clock-names = "core_clk", "phy_clk", "ref_clk"; 2144 dma-coherent; 2145 }; 2146 }; 2147 2148 main_r5fss0: r5fss@5c00000 { 2149 compatible = "ti,j721s2-r5fss"; 2150 ti,cluster-mode = <1>; 2151 #address-cells = <1>; 2152 #size-cells = <1>; 2153 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2154 <0x5d00000 0x00 0x5d00000 0x20000>; 2155 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 2156 2157 main_r5fss0_core0: r5f@5c00000 { 2158 compatible = "ti,j721s2-r5f"; 2159 reg = <0x5c00000 0x00010000>, 2160 <0x5c10000 0x00010000>; 2161 reg-names = "atcm", "btcm"; 2162 ti,sci = <&sms>; 2163 ti,sci-dev-id = <339>; 2164 ti,sci-proc-ids = <0x06 0xff>; 2165 resets = <&k3_reset 339 1>; 2166 firmware-name = "j784s4-main-r5f0_0-fw"; 2167 ti,atcm-enable = <1>; 2168 ti,btcm-enable = <1>; 2169 ti,loczrama = <1>; 2170 }; 2171 2172 main_r5fss0_core1: r5f@5d00000 { 2173 compatible = "ti,j721s2-r5f"; 2174 reg = <0x5d00000 0x00010000>, 2175 <0x5d10000 0x00010000>; 2176 reg-names = "atcm", "btcm"; 2177 ti,sci = <&sms>; 2178 ti,sci-dev-id = <340>; 2179 ti,sci-proc-ids = <0x07 0xff>; 2180 resets = <&k3_reset 340 1>; 2181 firmware-name = "j784s4-main-r5f0_1-fw"; 2182 ti,atcm-enable = <1>; 2183 ti,btcm-enable = <1>; 2184 ti,loczrama = <1>; 2185 }; 2186 }; 2187 2188 main_r5fss1: r5fss@5e00000 { 2189 compatible = "ti,j721s2-r5fss"; 2190 ti,cluster-mode = <1>; 2191 #address-cells = <1>; 2192 #size-cells = <1>; 2193 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2194 <0x5f00000 0x00 0x5f00000 0x20000>; 2195 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 2196 2197 main_r5fss1_core0: r5f@5e00000 { 2198 compatible = "ti,j721s2-r5f"; 2199 reg = <0x5e00000 0x00010000>, 2200 <0x5e10000 0x00010000>; 2201 reg-names = "atcm", "btcm"; 2202 ti,sci = <&sms>; 2203 ti,sci-dev-id = <341>; 2204 ti,sci-proc-ids = <0x08 0xff>; 2205 resets = <&k3_reset 341 1>; 2206 firmware-name = "j784s4-main-r5f1_0-fw"; 2207 ti,atcm-enable = <1>; 2208 ti,btcm-enable = <1>; 2209 ti,loczrama = <1>; 2210 }; 2211 2212 main_r5fss1_core1: r5f@5f00000 { 2213 compatible = "ti,j721s2-r5f"; 2214 reg = <0x5f00000 0x00010000>, 2215 <0x5f10000 0x00010000>; 2216 reg-names = "atcm", "btcm"; 2217 ti,sci = <&sms>; 2218 ti,sci-dev-id = <342>; 2219 ti,sci-proc-ids = <0x09 0xff>; 2220 resets = <&k3_reset 342 1>; 2221 firmware-name = "j784s4-main-r5f1_1-fw"; 2222 ti,atcm-enable = <1>; 2223 ti,btcm-enable = <1>; 2224 ti,loczrama = <1>; 2225 }; 2226 }; 2227 2228 main_r5fss2: r5fss@5900000 { 2229 compatible = "ti,j721s2-r5fss"; 2230 ti,cluster-mode = <1>; 2231 #address-cells = <1>; 2232 #size-cells = <1>; 2233 ranges = <0x5900000 0x00 0x5900000 0x20000>, 2234 <0x5a00000 0x00 0x5a00000 0x20000>; 2235 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 2236 2237 main_r5fss2_core0: r5f@5900000 { 2238 compatible = "ti,j721s2-r5f"; 2239 reg = <0x5900000 0x00010000>, 2240 <0x5910000 0x00010000>; 2241 reg-names = "atcm", "btcm"; 2242 ti,sci = <&sms>; 2243 ti,sci-dev-id = <343>; 2244 ti,sci-proc-ids = <0x0a 0xff>; 2245 resets = <&k3_reset 343 1>; 2246 firmware-name = "j784s4-main-r5f2_0-fw"; 2247 ti,atcm-enable = <1>; 2248 ti,btcm-enable = <1>; 2249 ti,loczrama = <1>; 2250 }; 2251 2252 main_r5fss2_core1: r5f@5a00000 { 2253 compatible = "ti,j721s2-r5f"; 2254 reg = <0x5a00000 0x00010000>, 2255 <0x5a10000 0x00010000>; 2256 reg-names = "atcm", "btcm"; 2257 ti,sci = <&sms>; 2258 ti,sci-dev-id = <344>; 2259 ti,sci-proc-ids = <0x0b 0xff>; 2260 resets = <&k3_reset 344 1>; 2261 firmware-name = "j784s4-main-r5f2_1-fw"; 2262 ti,atcm-enable = <1>; 2263 ti,btcm-enable = <1>; 2264 ti,loczrama = <1>; 2265 }; 2266 }; 2267 2268 c71_0: dsp@64800000 { 2269 compatible = "ti,j721s2-c71-dsp"; 2270 reg = <0x00 0x64800000 0x00 0x00080000>, 2271 <0x00 0x64e00000 0x00 0x0000c000>; 2272 reg-names = "l2sram", "l1dram"; 2273 ti,sci = <&sms>; 2274 ti,sci-dev-id = <30>; 2275 ti,sci-proc-ids = <0x30 0xff>; 2276 resets = <&k3_reset 30 1>; 2277 firmware-name = "j784s4-c71_0-fw"; 2278 status = "disabled"; 2279 }; 2280 2281 c71_1: dsp@65800000 { 2282 compatible = "ti,j721s2-c71-dsp"; 2283 reg = <0x00 0x65800000 0x00 0x00080000>, 2284 <0x00 0x65e00000 0x00 0x0000c000>; 2285 reg-names = "l2sram", "l1dram"; 2286 ti,sci = <&sms>; 2287 ti,sci-dev-id = <33>; 2288 ti,sci-proc-ids = <0x31 0xff>; 2289 resets = <&k3_reset 33 1>; 2290 firmware-name = "j784s4-c71_1-fw"; 2291 status = "disabled"; 2292 }; 2293 2294 c71_2: dsp@66800000 { 2295 compatible = "ti,j721s2-c71-dsp"; 2296 reg = <0x00 0x66800000 0x00 0x00080000>, 2297 <0x00 0x66e00000 0x00 0x0000c000>; 2298 reg-names = "l2sram", "l1dram"; 2299 ti,sci = <&sms>; 2300 ti,sci-dev-id = <37>; 2301 ti,sci-proc-ids = <0x32 0xff>; 2302 resets = <&k3_reset 37 1>; 2303 firmware-name = "j784s4-c71_2-fw"; 2304 status = "disabled"; 2305 }; 2306 2307 main_esm: esm@700000 { 2308 compatible = "ti,j721e-esm"; 2309 reg = <0x00 0x700000 0x00 0x1000>; 2310 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 2311 <695>; 2312 bootph-pre-ram; 2313 }; 2314 2315 watchdog0: watchdog@2200000 { 2316 compatible = "ti,j7-rti-wdt"; 2317 reg = <0x00 0x2200000 0x00 0x100>; 2318 clocks = <&k3_clks 348 0>; 2319 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 2320 assigned-clocks = <&k3_clks 348 0>; 2321 assigned-clock-parents = <&k3_clks 348 4>; 2322 }; 2323 2324 watchdog1: watchdog@2210000 { 2325 compatible = "ti,j7-rti-wdt"; 2326 reg = <0x00 0x2210000 0x00 0x100>; 2327 clocks = <&k3_clks 349 0>; 2328 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 2329 assigned-clocks = <&k3_clks 349 0>; 2330 assigned-clock-parents = <&k3_clks 349 4>; 2331 }; 2332 2333 watchdog2: watchdog@2220000 { 2334 compatible = "ti,j7-rti-wdt"; 2335 reg = <0x00 0x2220000 0x00 0x100>; 2336 clocks = <&k3_clks 350 0>; 2337 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 2338 assigned-clocks = <&k3_clks 350 0>; 2339 assigned-clock-parents = <&k3_clks 350 4>; 2340 }; 2341 2342 watchdog3: watchdog@2230000 { 2343 compatible = "ti,j7-rti-wdt"; 2344 reg = <0x00 0x2230000 0x00 0x100>; 2345 clocks = <&k3_clks 351 0>; 2346 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 2347 assigned-clocks = <&k3_clks 351 0>; 2348 assigned-clock-parents = <&k3_clks 351 4>; 2349 }; 2350 2351 watchdog4: watchdog@2240000 { 2352 compatible = "ti,j7-rti-wdt"; 2353 reg = <0x00 0x2240000 0x00 0x100>; 2354 clocks = <&k3_clks 352 0>; 2355 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 2356 assigned-clocks = <&k3_clks 352 0>; 2357 assigned-clock-parents = <&k3_clks 352 4>; 2358 }; 2359 2360 watchdog5: watchdog@2250000 { 2361 compatible = "ti,j7-rti-wdt"; 2362 reg = <0x00 0x2250000 0x00 0x100>; 2363 clocks = <&k3_clks 353 0>; 2364 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 2365 assigned-clocks = <&k3_clks 353 0>; 2366 assigned-clock-parents = <&k3_clks 353 4>; 2367 }; 2368 2369 watchdog6: watchdog@2260000 { 2370 compatible = "ti,j7-rti-wdt"; 2371 reg = <0x00 0x2260000 0x00 0x100>; 2372 clocks = <&k3_clks 354 0>; 2373 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 2374 assigned-clocks = <&k3_clks 354 0>; 2375 assigned-clock-parents = <&k3_clks 354 4>; 2376 }; 2377 2378 watchdog7: watchdog@2270000 { 2379 compatible = "ti,j7-rti-wdt"; 2380 reg = <0x00 0x2270000 0x00 0x100>; 2381 clocks = <&k3_clks 355 0>; 2382 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 2383 assigned-clocks = <&k3_clks 355 0>; 2384 assigned-clock-parents = <&k3_clks 355 4>; 2385 }; 2386 2387 /* 2388 * The following RTI instances are coupled with MCU R5Fs, c7x and 2389 * GPU so keeping them reserved as these will be used by their 2390 * respective firmware 2391 */ 2392 watchdog8: watchdog@22f0000 { 2393 compatible = "ti,j7-rti-wdt"; 2394 reg = <0x00 0x22f0000 0x00 0x100>; 2395 clocks = <&k3_clks 360 0>; 2396 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 2397 assigned-clocks = <&k3_clks 360 0>; 2398 assigned-clock-parents = <&k3_clks 360 4>; 2399 /* reserved for GPU */ 2400 status = "reserved"; 2401 }; 2402 2403 watchdog9: watchdog@2300000 { 2404 compatible = "ti,j7-rti-wdt"; 2405 reg = <0x00 0x2300000 0x00 0x100>; 2406 clocks = <&k3_clks 356 0>; 2407 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 2408 assigned-clocks = <&k3_clks 356 0>; 2409 assigned-clock-parents = <&k3_clks 356 4>; 2410 /* reserved for C7X_0 DSP */ 2411 status = "reserved"; 2412 }; 2413 2414 watchdog10: watchdog@2310000 { 2415 compatible = "ti,j7-rti-wdt"; 2416 reg = <0x00 0x2310000 0x00 0x100>; 2417 clocks = <&k3_clks 357 0>; 2418 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 2419 assigned-clocks = <&k3_clks 357 0>; 2420 assigned-clock-parents = <&k3_clks 357 4>; 2421 /* reserved for C7X_1 DSP */ 2422 status = "reserved"; 2423 }; 2424 2425 watchdog11: watchdog@2320000 { 2426 compatible = "ti,j7-rti-wdt"; 2427 reg = <0x00 0x2320000 0x00 0x100>; 2428 clocks = <&k3_clks 358 0>; 2429 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 2430 assigned-clocks = <&k3_clks 358 0>; 2431 assigned-clock-parents = <&k3_clks 358 4>; 2432 /* reserved for C7X_2 DSP */ 2433 status = "reserved"; 2434 }; 2435 2436 watchdog12: watchdog@2330000 { 2437 compatible = "ti,j7-rti-wdt"; 2438 reg = <0x00 0x2330000 0x00 0x100>; 2439 clocks = <&k3_clks 359 0>; 2440 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 2441 assigned-clocks = <&k3_clks 359 0>; 2442 assigned-clock-parents = <&k3_clks 359 4>; 2443 /* reserved for C7X_3 DSP */ 2444 status = "reserved"; 2445 }; 2446 2447 watchdog13: watchdog@23c0000 { 2448 compatible = "ti,j7-rti-wdt"; 2449 reg = <0x00 0x23c0000 0x00 0x100>; 2450 clocks = <&k3_clks 361 0>; 2451 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 2452 assigned-clocks = <&k3_clks 361 0>; 2453 assigned-clock-parents = <&k3_clks 361 4>; 2454 /* reserved for MAIN_R5F0_0 */ 2455 status = "reserved"; 2456 }; 2457 2458 watchdog14: watchdog@23d0000 { 2459 compatible = "ti,j7-rti-wdt"; 2460 reg = <0x00 0x23d0000 0x00 0x100>; 2461 clocks = <&k3_clks 362 0>; 2462 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 2463 assigned-clocks = <&k3_clks 362 0>; 2464 assigned-clock-parents = <&k3_clks 362 4>; 2465 /* reserved for MAIN_R5F0_1 */ 2466 status = "reserved"; 2467 }; 2468 2469 watchdog15: watchdog@23e0000 { 2470 compatible = "ti,j7-rti-wdt"; 2471 reg = <0x00 0x23e0000 0x00 0x100>; 2472 clocks = <&k3_clks 363 0>; 2473 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 2474 assigned-clocks = <&k3_clks 363 0>; 2475 assigned-clock-parents = <&k3_clks 363 4>; 2476 /* reserved for MAIN_R5F1_0 */ 2477 status = "reserved"; 2478 }; 2479 2480 watchdog16: watchdog@23f0000 { 2481 compatible = "ti,j7-rti-wdt"; 2482 reg = <0x00 0x23f0000 0x00 0x100>; 2483 clocks = <&k3_clks 364 0>; 2484 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 2485 assigned-clocks = <&k3_clks 364 0>; 2486 assigned-clock-parents = <&k3_clks 364 4>; 2487 /* reserved for MAIN_R5F1_1 */ 2488 status = "reserved"; 2489 }; 2490 2491 watchdog17: watchdog@2540000 { 2492 compatible = "ti,j7-rti-wdt"; 2493 reg = <0x00 0x2540000 0x00 0x100>; 2494 clocks = <&k3_clks 365 0>; 2495 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 2496 assigned-clocks = <&k3_clks 365 0>; 2497 assigned-clock-parents = <&k3_clks 366 4>; 2498 /* reserved for MAIN_R5F2_0 */ 2499 status = "reserved"; 2500 }; 2501 2502 watchdog18: watchdog@2550000 { 2503 compatible = "ti,j7-rti-wdt"; 2504 reg = <0x00 0x2550000 0x00 0x100>; 2505 clocks = <&k3_clks 366 0>; 2506 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 2507 assigned-clocks = <&k3_clks 366 0>; 2508 assigned-clock-parents = <&k3_clks 366 4>; 2509 /* reserved for MAIN_R5F2_1 */ 2510 status = "reserved"; 2511 }; 2512 2513 mhdp: bridge@a000000 { 2514 compatible = "ti,j721e-mhdp8546"; 2515 reg = <0x0 0xa000000 0x0 0x30a00>, 2516 <0x0 0x4f40000 0x0 0x20>; 2517 reg-names = "mhdptx", "j721e-intg"; 2518 clocks = <&k3_clks 217 11>; 2519 interrupt-parent = <&gic500>; 2520 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2521 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2522 status = "disabled"; 2523 2524 dp0_ports: ports { 2525 #address-cells = <1>; 2526 #size-cells = <0>; 2527 /* Remote-endpoints are on the boards so 2528 * ports are defined in the platform dt file. 2529 */ 2530 }; 2531 }; 2532 2533 dss: dss@4a00000 { 2534 compatible = "ti,j721e-dss"; 2535 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2536 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2537 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2538 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2539 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2540 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2541 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2542 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2543 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2544 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2545 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2546 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2547 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2548 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2549 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2550 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2551 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2552 reg-names = "common_m", "common_s0", 2553 "common_s1", "common_s2", 2554 "vidl1", "vidl2","vid1","vid2", 2555 "ovr1", "ovr2", "ovr3", "ovr4", 2556 "vp1", "vp2", "vp3", "vp4", 2557 "wb"; 2558 clocks = <&k3_clks 218 0>, 2559 <&k3_clks 218 2>, 2560 <&k3_clks 218 5>, 2561 <&k3_clks 218 14>, 2562 <&k3_clks 218 18>; 2563 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2564 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2565 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2569 interrupt-names = "common_m", 2570 "common_s0", 2571 "common_s1", 2572 "common_s2"; 2573 status = "disabled"; 2574 2575 dss_ports: ports { 2576 /* Ports that DSS drives are platform specific 2577 * so they are defined in platform dt file. 2578 */ 2579 }; 2580 }; 2581 2582 mcasp0: mcasp@2b00000 { 2583 compatible = "ti,am33xx-mcasp-audio"; 2584 reg = <0x00 0x02b00000 0x00 0x2000>, 2585 <0x00 0x02b08000 0x00 0x1000>; 2586 reg-names = "mpu","dat"; 2587 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 2589 interrupt-names = "tx", "rx"; 2590 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 2591 dma-names = "tx", "rx"; 2592 clocks = <&k3_clks 265 0>; 2593 clock-names = "fck"; 2594 assigned-clocks = <&k3_clks 265 0>; 2595 assigned-clock-parents = <&k3_clks 265 1>; 2596 power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>; 2597 status = "disabled"; 2598 }; 2599 2600 mcasp1: mcasp@2b10000 { 2601 compatible = "ti,am33xx-mcasp-audio"; 2602 reg = <0x00 0x02b10000 0x00 0x2000>, 2603 <0x00 0x02b18000 0x00 0x1000>; 2604 reg-names = "mpu","dat"; 2605 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 2607 interrupt-names = "tx", "rx"; 2608 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 2609 dma-names = "tx", "rx"; 2610 clocks = <&k3_clks 266 0>; 2611 clock-names = "fck"; 2612 assigned-clocks = <&k3_clks 266 0>; 2613 assigned-clock-parents = <&k3_clks 266 1>; 2614 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2615 status = "disabled"; 2616 }; 2617 2618 mcasp2: mcasp@2b20000 { 2619 compatible = "ti,am33xx-mcasp-audio"; 2620 reg = <0x00 0x02b20000 0x00 0x2000>, 2621 <0x00 0x02b28000 0x00 0x1000>; 2622 reg-names = "mpu","dat"; 2623 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 2625 interrupt-names = "tx", "rx"; 2626 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 2627 dma-names = "tx", "rx"; 2628 clocks = <&k3_clks 267 0>; 2629 clock-names = "fck"; 2630 assigned-clocks = <&k3_clks 267 0>; 2631 assigned-clock-parents = <&k3_clks 267 1>; 2632 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2633 status = "disabled"; 2634 }; 2635 2636 mcasp3: mcasp@2b30000 { 2637 compatible = "ti,am33xx-mcasp-audio"; 2638 reg = <0x00 0x02b30000 0x00 0x2000>, 2639 <0x00 0x02b38000 0x00 0x1000>; 2640 reg-names = "mpu","dat"; 2641 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 2642 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 2643 interrupt-names = "tx", "rx"; 2644 dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>; 2645 dma-names = "tx", "rx"; 2646 clocks = <&k3_clks 268 0>; 2647 clock-names = "fck"; 2648 assigned-clocks = <&k3_clks 268 0>; 2649 assigned-clock-parents = <&k3_clks 268 1>; 2650 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2651 status = "disabled"; 2652 }; 2653 2654 mcasp4: mcasp@2b40000 { 2655 compatible = "ti,am33xx-mcasp-audio"; 2656 reg = <0x00 0x02b40000 0x00 0x2000>, 2657 <0x00 0x02b48000 0x00 0x1000>; 2658 reg-names = "mpu","dat"; 2659 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 2660 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 2661 interrupt-names = "tx", "rx"; 2662 dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>; 2663 dma-names = "tx", "rx"; 2664 clocks = <&k3_clks 269 0>; 2665 clock-names = "fck"; 2666 assigned-clocks = <&k3_clks 269 0>; 2667 assigned-clock-parents = <&k3_clks 269 1>; 2668 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2669 status = "disabled"; 2670 }; 2671}; 2672