1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 6 * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 7 */ 8/ { 9 chosen { 10 stdout-path = "serial2:115200n8"; 11 }; 12 13 aliases { 14 serial0 = &wkup_uart0; 15 serial1 = &mcu_uart0; 16 serial2 = &main_uart8; 17 mmc0 = &main_sdhci0; 18 mmc1 = &main_sdhci1; 19 i2c0 = &wkup_i2c0; 20 i2c3 = &main_i2c0; 21 ethernet0 = &mcu_cpsw_port1; 22 ethernet1 = &main_cpsw1_port1; 23 }; 24 25 reserved_memory: reserved-memory { 26 #address-cells = <2>; 27 #size-cells = <2>; 28 ranges; 29 30 secure_ddr: optee@9e800000 { 31 reg = <0x00 0x9e800000 0x00 0x01800000>; 32 no-map; 33 }; 34 35 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 36 compatible = "shared-dma-pool"; 37 reg = <0x00 0xa0000000 0x00 0x100000>; 38 no-map; 39 }; 40 41 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 42 compatible = "shared-dma-pool"; 43 reg = <0x00 0xa0100000 0x00 0xf00000>; 44 no-map; 45 }; 46 47 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 48 compatible = "shared-dma-pool"; 49 reg = <0x00 0xa1000000 0x00 0x100000>; 50 no-map; 51 }; 52 53 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa1100000 0x00 0xf00000>; 56 no-map; 57 }; 58 59 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa2000000 0x00 0x100000>; 62 no-map; 63 }; 64 65 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa2100000 0x00 0xf00000>; 68 no-map; 69 }; 70 71 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa3000000 0x00 0x100000>; 74 no-map; 75 }; 76 77 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 78 compatible = "shared-dma-pool"; 79 reg = <0x00 0xa3100000 0x00 0xf00000>; 80 no-map; 81 }; 82 83 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa4000000 0x00 0x100000>; 86 no-map; 87 }; 88 89 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x00 0xa4100000 0x00 0xf00000>; 92 no-map; 93 }; 94 95 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 96 compatible = "shared-dma-pool"; 97 reg = <0x00 0xa5000000 0x00 0x100000>; 98 no-map; 99 }; 100 101 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 102 compatible = "shared-dma-pool"; 103 reg = <0x00 0xa5100000 0x00 0xf00000>; 104 no-map; 105 }; 106 107 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 108 compatible = "shared-dma-pool"; 109 reg = <0x00 0xa6000000 0x00 0x100000>; 110 no-map; 111 }; 112 113 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 114 compatible = "shared-dma-pool"; 115 reg = <0x00 0xa6100000 0x00 0xf00000>; 116 no-map; 117 }; 118 119 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 120 compatible = "shared-dma-pool"; 121 reg = <0x00 0xa7000000 0x00 0x100000>; 122 no-map; 123 }; 124 125 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 126 compatible = "shared-dma-pool"; 127 reg = <0x00 0xa7100000 0x00 0xf00000>; 128 no-map; 129 }; 130 131 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 132 compatible = "shared-dma-pool"; 133 reg = <0x00 0xa8000000 0x00 0x100000>; 134 no-map; 135 }; 136 137 c71_0_memory_region: c71-memory@a8100000 { 138 compatible = "shared-dma-pool"; 139 reg = <0x00 0xa8100000 0x00 0xf00000>; 140 no-map; 141 }; 142 143 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 144 compatible = "shared-dma-pool"; 145 reg = <0x00 0xa9000000 0x00 0x100000>; 146 no-map; 147 }; 148 149 c71_1_memory_region: c71-memory@a9100000 { 150 compatible = "shared-dma-pool"; 151 reg = <0x00 0xa9100000 0x00 0xf00000>; 152 no-map; 153 }; 154 155 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 156 compatible = "shared-dma-pool"; 157 reg = <0x00 0xaa000000 0x00 0x100000>; 158 no-map; 159 }; 160 161 c71_2_memory_region: c71-memory@aa100000 { 162 compatible = "shared-dma-pool"; 163 reg = <0x00 0xaa100000 0x00 0xf00000>; 164 no-map; 165 }; 166 }; 167 168 evm_12v0: regulator-evm12v0 { 169 /* main supply */ 170 compatible = "regulator-fixed"; 171 regulator-name = "evm_12v0"; 172 regulator-min-microvolt = <12000000>; 173 regulator-max-microvolt = <12000000>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 vsys_3v3: regulator-vsys3v3 { 179 /* Output of LM5140 */ 180 compatible = "regulator-fixed"; 181 regulator-name = "vsys_3v3"; 182 regulator-min-microvolt = <3300000>; 183 regulator-max-microvolt = <3300000>; 184 vin-supply = <&evm_12v0>; 185 regulator-always-on; 186 regulator-boot-on; 187 }; 188 189 vsys_5v0: regulator-vsys5v0 { 190 /* Output of LM5140 */ 191 compatible = "regulator-fixed"; 192 regulator-name = "vsys_5v0"; 193 regulator-min-microvolt = <5000000>; 194 regulator-max-microvolt = <5000000>; 195 vin-supply = <&evm_12v0>; 196 regulator-always-on; 197 regulator-boot-on; 198 }; 199 200 vdd_mmc1: regulator-sd { 201 /* Output of TPS22918 */ 202 compatible = "regulator-fixed"; 203 regulator-name = "vdd_mmc1"; 204 regulator-min-microvolt = <3300000>; 205 regulator-max-microvolt = <3300000>; 206 regulator-boot-on; 207 enable-active-high; 208 vin-supply = <&vsys_3v3>; 209 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 210 }; 211 212 vdd_sd_dv: regulator-TLV71033 { 213 /* Output of TLV71033 */ 214 compatible = "regulator-gpio"; 215 regulator-name = "tlv71033"; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&vdd_sd_dv_pins_default>; 218 regulator-min-microvolt = <1800000>; 219 regulator-max-microvolt = <3300000>; 220 regulator-boot-on; 221 vin-supply = <&vsys_5v0>; 222 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 223 states = <1800000 0x0>, 224 <3300000 0x1>; 225 }; 226 227 dp0_pwr_3v3: regulator-dp0-prw { 228 compatible = "regulator-fixed"; 229 regulator-name = "dp0-pwr"; 230 regulator-min-microvolt = <3300000>; 231 regulator-max-microvolt = <3300000>; 232 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; 233 enable-active-high; 234 }; 235 236 dp0: connector-dp0 { 237 compatible = "dp-connector"; 238 label = "DP0"; 239 type = "full-size"; 240 dp-pwr-supply = <&dp0_pwr_3v3>; 241 242 port { 243 dp0_connector_in: endpoint { 244 remote-endpoint = <&dp0_out>; 245 }; 246 }; 247 }; 248 249 transceiver0: can-phy0 { 250 compatible = "ti,tcan1042"; 251 #phy-cells = <0>; 252 max-bitrate = <5000000>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 255 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; 256 }; 257 258 transceiver1: can-phy1 { 259 compatible = "ti,tcan1042"; 260 #phy-cells = <0>; 261 max-bitrate = <5000000>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 264 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 265 }; 266 267 transceiver2: can-phy2 { 268 /* standby pin has been grounded by default */ 269 compatible = "ti,tcan1042"; 270 #phy-cells = <0>; 271 max-bitrate = <5000000>; 272 }; 273 274 transceiver3: can-phy3 { 275 compatible = "ti,tcan1042"; 276 #phy-cells = <0>; 277 max-bitrate = <5000000>; 278 standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 279 mux-states = <&mux1 1>; 280 }; 281 282 mux1: mux-controller { 283 compatible = "gpio-mux"; 284 #mux-state-cells = <1>; 285 mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; 286 idle-state = <1>; 287 }; 288 289 codec_audio: sound { 290 compatible = "ti,j7200-cpb-audio"; 291 model = "j784s4-cpb"; 292 293 ti,cpb-mcasp = <&mcasp0>; 294 ti,cpb-codec = <&pcm3168a_1>; 295 296 clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, 297 <&k3_clks 157 34>, <&k3_clks 157 63>; 298 clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", 299 "cpb-codec-scki", "cpb-codec-scki-48000"; 300 }; 301}; 302 303&wkup_gpio0 { 304 status = "okay"; 305}; 306 307&main_pmx0 { 308 main_cpsw2g_default_pins: main-cpsw2g-default-pins { 309 pinctrl-single,pins = < 310 J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ 311 J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ 312 J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ 313 J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ 314 J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ 315 J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ 316 J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ 317 J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ 318 J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ 319 J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ 320 J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ 321 J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ 322 >; 323 }; 324 325 main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { 326 pinctrl-single,pins = < 327 J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ 328 J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ 329 >; 330 }; 331 332 main_uart8_pins_default: main-uart8-default-pins { 333 bootph-all; 334 pinctrl-single,pins = < 335 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 336 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 337 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 338 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 339 >; 340 }; 341 342 main_i2c0_pins_default: main-i2c0-default-pins { 343 pinctrl-single,pins = < 344 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 345 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 346 >; 347 }; 348 349 main_i2c5_pins_default: main-i2c5-default-pins { 350 pinctrl-single,pins = < 351 J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ 352 J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ 353 >; 354 }; 355 356 main_mmc1_pins_default: main-mmc1-default-pins { 357 bootph-all; 358 pinctrl-single,pins = < 359 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 360 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 361 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 362 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 363 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 364 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 365 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 366 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 367 >; 368 }; 369 370 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 371 pinctrl-single,pins = < 372 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 373 >; 374 }; 375 376 dp0_pins_default: dp0-default-pins { 377 pinctrl-single,pins = < 378 J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ 379 >; 380 }; 381 382 main_i2c4_pins_default: main-i2c4-default-pins { 383 pinctrl-single,pins = < 384 J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ 385 J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ 386 >; 387 }; 388 389 main_mcan4_pins_default: main-mcan4-default-pins { 390 pinctrl-single,pins = < 391 J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ 392 J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ 393 >; 394 }; 395 396 main_mcan16_pins_default: main-mcan16-default-pins { 397 pinctrl-single,pins = < 398 J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ 399 J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ 400 >; 401 }; 402 403 main_usbss0_pins_default: main-usbss0-default-pins { 404 bootph-all; 405 pinctrl-single,pins = < 406 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 407 >; 408 }; 409 410 main_i2c3_pins_default: main-i2c3-default-pins { 411 pinctrl-single,pins = < 412 J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ 413 J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ 414 >; 415 }; 416 417 main_mcasp0_pins_default: main-mcasp0-default-pins { 418 pinctrl-single,pins = < 419 J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ 420 J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ 421 J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ 422 J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ 423 >; 424 }; 425 426 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 427 pinctrl-single,pins = < 428 J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ 429 >; 430 }; 431}; 432 433&wkup_pmx2 { 434 wkup_uart0_pins_default: wkup-uart0-default-pins { 435 bootph-all; 436 pinctrl-single,pins = < 437 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 438 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 439 >; 440 }; 441 442 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 443 bootph-all; 444 pinctrl-single,pins = < 445 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 446 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 447 >; 448 }; 449 450 mcu_uart0_pins_default: mcu-uart0-default-pins { 451 bootph-all; 452 pinctrl-single,pins = < 453 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 454 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 455 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 456 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 457 >; 458 }; 459 460 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 461 pinctrl-single,pins = < 462 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 463 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 464 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 465 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 466 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 467 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 468 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 469 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 470 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 471 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 472 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 473 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 474 >; 475 }; 476 477 mcu_mdio_pins_default: mcu-mdio-default-pins { 478 pinctrl-single,pins = < 479 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 480 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 481 >; 482 }; 483 484 mcu_adc0_pins_default: mcu-adc0-default-pins { 485 pinctrl-single,pins = < 486 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 487 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 488 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 489 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 490 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 491 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 492 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 493 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 494 >; 495 }; 496 497 mcu_adc1_pins_default: mcu-adc1-default-pins { 498 pinctrl-single,pins = < 499 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 500 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 501 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 502 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 503 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 504 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 505 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 506 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 507 >; 508 }; 509 510 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 511 pinctrl-single,pins = < 512 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 513 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 514 >; 515 }; 516 517 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 518 pinctrl-single,pins = < 519 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 520 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 521 >; 522 }; 523 524 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 525 pinctrl-single,pins = < 526 J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ 527 >; 528 }; 529 530 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 531 pinctrl-single,pins = < 532 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 533 >; 534 }; 535}; 536 537&wkup_pmx1 { 538 status = "okay"; 539 540 pmic_irq_pins_default: pmic-irq-default-pins { 541 pinctrl-single,pins = < 542 /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 543 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) 544 >; 545 }; 546}; 547 548&wkup_pmx0 { 549 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 550 bootph-all; 551 pinctrl-single,pins = < 552 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 553 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 554 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 555 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 556 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 557 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 558 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 559 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 560 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 561 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 562 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 563 >; 564 }; 565}; 566 567&wkup_pmx1 { 568 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 569 bootph-all; 570 pinctrl-single,pins = < 571 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 572 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 573 >; 574 }; 575 576 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 577 bootph-all; 578 pinctrl-single,pins = < 579 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 580 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 581 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 582 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 583 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 584 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 585 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 586 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 587 >; 588 }; 589}; 590 591&wkup_uart0 { 592 /* Firmware usage */ 593 status = "reserved"; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&wkup_uart0_pins_default>; 596}; 597 598&wkup_i2c0 { 599 bootph-all; 600 status = "okay"; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&wkup_i2c0_pins_default>; 603 clock-frequency = <400000>; 604 605 eeprom@50 { 606 /* CAV24C256WE-GT3 */ 607 compatible = "atmel,24c256"; 608 reg = <0x50>; 609 }; 610 611 tps659413: pmic@48 { 612 compatible = "ti,tps6594-q1"; 613 reg = <0x48>; 614 system-power-controller; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pmic_irq_pins_default>; 617 interrupt-parent = <&wkup_gpio0>; 618 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 619 gpio-controller; 620 #gpio-cells = <2>; 621 ti,primary-pmic; 622 buck12-supply = <&vsys_3v3>; 623 buck3-supply = <&vsys_3v3>; 624 buck4-supply = <&vsys_3v3>; 625 buck5-supply = <&vsys_3v3>; 626 ldo1-supply = <&vsys_3v3>; 627 ldo2-supply = <&vsys_3v3>; 628 ldo3-supply = <&vsys_3v3>; 629 ldo4-supply = <&vsys_3v3>; 630 631 regulators { 632 bucka12: buck12 { 633 regulator-name = "vdd_ddr_1v1"; 634 regulator-min-microvolt = <1100000>; 635 regulator-max-microvolt = <1100000>; 636 regulator-boot-on; 637 regulator-always-on; 638 }; 639 640 bucka3: buck3 { 641 regulator-name = "vdd_ram_0v85"; 642 regulator-min-microvolt = <850000>; 643 regulator-max-microvolt = <850000>; 644 regulator-boot-on; 645 regulator-always-on; 646 }; 647 648 bucka4: buck4 { 649 regulator-name = "vdd_io_1v8"; 650 regulator-min-microvolt = <1800000>; 651 regulator-max-microvolt = <1800000>; 652 regulator-boot-on; 653 regulator-always-on; 654 }; 655 656 bucka5: buck5 { 657 regulator-name = "vdd_mcu_0v85"; 658 regulator-min-microvolt = <850000>; 659 regulator-max-microvolt = <850000>; 660 regulator-boot-on; 661 regulator-always-on; 662 }; 663 664 ldoa1: ldo1 { 665 regulator-name = "vdd_mcuio_1v8"; 666 regulator-min-microvolt = <1800000>; 667 regulator-max-microvolt = <1800000>; 668 regulator-boot-on; 669 regulator-always-on; 670 }; 671 672 ldoa2: ldo2 { 673 regulator-name = "vdd_mcuio_3v3"; 674 regulator-min-microvolt = <3300000>; 675 regulator-max-microvolt = <3300000>; 676 regulator-boot-on; 677 regulator-always-on; 678 }; 679 680 ldoa3: ldo3 { 681 regulator-name = "vds_dll_0v8"; 682 regulator-min-microvolt = <800000>; 683 regulator-max-microvolt = <800000>; 684 regulator-boot-on; 685 regulator-always-on; 686 }; 687 688 ldoa4: ldo4 { 689 regulator-name = "vda_mcu_1v8"; 690 regulator-min-microvolt = <1800000>; 691 regulator-max-microvolt = <1800000>; 692 regulator-boot-on; 693 regulator-always-on; 694 }; 695 }; 696 }; 697 698 tps62873a: regulator@40 { 699 compatible = "ti,tps62873"; 700 reg = <0x40>; 701 bootph-pre-ram; 702 regulator-name = "VDD_CPU_AVS"; 703 regulator-min-microvolt = <750000>; 704 regulator-max-microvolt = <1330000>; 705 regulator-boot-on; 706 regulator-always-on; 707 }; 708 709 tps62873b: regulator@43 { 710 compatible = "ti,tps62873"; 711 reg = <0x43>; 712 regulator-name = "VDD_CORE_0V8"; 713 regulator-min-microvolt = <760000>; 714 regulator-max-microvolt = <840000>; 715 regulator-boot-on; 716 regulator-always-on; 717 }; 718}; 719 720&mcu_uart0 { 721 bootph-all; 722 status = "okay"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&mcu_uart0_pins_default>; 725}; 726 727&main_uart8 { 728 bootph-all; 729 status = "okay"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&main_uart8_pins_default>; 732}; 733 734&ufs_wrapper { 735 status = "okay"; 736}; 737 738&fss { 739 status = "okay"; 740}; 741 742&ospi0 { 743 status = "okay"; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 746 747 flash@0 { 748 compatible = "jedec,spi-nor"; 749 reg = <0x0>; 750 spi-tx-bus-width = <8>; 751 spi-rx-bus-width = <8>; 752 spi-max-frequency = <25000000>; 753 cdns,tshsl-ns = <60>; 754 cdns,tsd2d-ns = <60>; 755 cdns,tchsh-ns = <60>; 756 cdns,tslch-ns = <60>; 757 cdns,read-delay = <4>; 758 759 partitions { 760 compatible = "fixed-partitions"; 761 #address-cells = <1>; 762 #size-cells = <1>; 763 764 partition@0 { 765 label = "ospi.tiboot3"; 766 reg = <0x0 0x80000>; 767 }; 768 769 partition@80000 { 770 label = "ospi.tispl"; 771 reg = <0x80000 0x200000>; 772 }; 773 774 partition@280000 { 775 label = "ospi.u-boot"; 776 reg = <0x280000 0x400000>; 777 }; 778 779 partition@680000 { 780 label = "ospi.env"; 781 reg = <0x680000 0x40000>; 782 }; 783 784 partition@6c0000 { 785 label = "ospi.env.backup"; 786 reg = <0x6c0000 0x40000>; 787 }; 788 789 partition@800000 { 790 label = "ospi.rootfs"; 791 reg = <0x800000 0x37c0000>; 792 }; 793 794 partition@3fc0000 { 795 bootph-all; 796 label = "ospi.phypattern"; 797 reg = <0x3fc0000 0x40000>; 798 }; 799 }; 800 }; 801}; 802 803&ospi1 { 804 status = "okay"; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 807 808 flash@0 { 809 compatible = "jedec,spi-nor"; 810 reg = <0x0>; 811 spi-tx-bus-width = <1>; 812 spi-rx-bus-width = <4>; 813 spi-max-frequency = <40000000>; 814 cdns,tshsl-ns = <60>; 815 cdns,tsd2d-ns = <60>; 816 cdns,tchsh-ns = <60>; 817 cdns,tslch-ns = <60>; 818 cdns,read-delay = <2>; 819 820 partitions { 821 compatible = "fixed-partitions"; 822 #address-cells = <1>; 823 #size-cells = <1>; 824 825 partition@0 { 826 label = "qspi.tiboot3"; 827 reg = <0x0 0x80000>; 828 }; 829 830 partition@80000 { 831 label = "qspi.tispl"; 832 reg = <0x80000 0x200000>; 833 }; 834 835 partition@280000 { 836 label = "qspi.u-boot"; 837 reg = <0x280000 0x400000>; 838 }; 839 840 partition@680000 { 841 label = "qspi.env"; 842 reg = <0x680000 0x40000>; 843 }; 844 845 partition@6c0000 { 846 label = "qspi.env.backup"; 847 reg = <0x6c0000 0x40000>; 848 }; 849 850 partition@800000 { 851 label = "qspi.rootfs"; 852 reg = <0x800000 0x37c0000>; 853 }; 854 855 partition@3fc0000 { 856 bootph-all; 857 label = "qspi.phypattern"; 858 reg = <0x3fc0000 0x40000>; 859 }; 860 }; 861 862 }; 863}; 864 865&main_i2c0 { 866 status = "okay"; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&main_i2c0_pins_default>; 869 870 clock-frequency = <400000>; 871 872 exp1: gpio@20 { 873 compatible = "ti,tca6416"; 874 reg = <0x20>; 875 gpio-controller; 876 #gpio-cells = <2>; 877 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 878 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 879 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 880 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 881 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 882 883 p12-hog { 884 /* P12 - AUDIO_MUX_SEL */ 885 gpio-hog; 886 gpios = <12 GPIO_ACTIVE_HIGH>; 887 output-low; 888 line-name = "AUDIO_MUX_SEL"; 889 }; 890 }; 891 892 exp2: gpio@22 { 893 compatible = "ti,tca6424"; 894 reg = <0x22>; 895 gpio-controller; 896 #gpio-cells = <2>; 897 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 898 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 899 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 900 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 901 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 902 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 903 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 904 "USER_INPUT1", "USER_LED1", "USER_LED2"; 905 906 p13-hog { 907 /* P13 - CANUART_MUX_SEL0 */ 908 gpio-hog; 909 gpios = <13 GPIO_ACTIVE_HIGH>; 910 output-high; 911 line-name = "CANUART_MUX_SEL0"; 912 }; 913 914 p15-hog { 915 /* P15 - CANUART_MUX1_SEL1 */ 916 gpio-hog; 917 gpios = <15 GPIO_ACTIVE_HIGH>; 918 output-high; 919 line-name = "CANUART_MUX1_SEL1"; 920 }; 921 }; 922}; 923 924&main_i2c5 { 925 pinctrl-names = "default"; 926 pinctrl-0 = <&main_i2c5_pins_default>; 927 clock-frequency = <400000>; 928 status = "okay"; 929 930 exp5: gpio@20 { 931 compatible = "ti,tca6408"; 932 reg = <0x20>; 933 gpio-controller; 934 #gpio-cells = <2>; 935 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", 936 "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", 937 "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", 938 "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; 939 }; 940}; 941 942&main_sdhci0 { 943 bootph-all; 944 /* eMMC */ 945 status = "okay"; 946 non-removable; 947 ti,driver-strength-ohm = <50>; 948 disable-wp; 949}; 950 951&main_sdhci1 { 952 bootph-all; 953 /* SD card */ 954 status = "okay"; 955 pinctrl-0 = <&main_mmc1_pins_default>; 956 pinctrl-names = "default"; 957 disable-wp; 958 vmmc-supply = <&vdd_mmc1>; 959 vqmmc-supply = <&vdd_sd_dv>; 960}; 961 962&main_gpio0 { 963 status = "okay"; 964}; 965 966&mcu_cpsw { 967 status = "okay"; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&mcu_cpsw_pins_default>; 970}; 971 972&davinci_mdio { 973 pinctrl-names = "default"; 974 pinctrl-0 = <&mcu_mdio_pins_default>; 975 976 mcu_phy0: ethernet-phy@0 { 977 reg = <0>; 978 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 979 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 980 ti,min-output-impedance; 981 }; 982}; 983 984&mcu_cpsw_port1 { 985 status = "okay"; 986 phy-mode = "rgmii-rxid"; 987 phy-handle = <&mcu_phy0>; 988}; 989 990&main_cpsw1 { 991 pinctrl-names = "default"; 992 pinctrl-0 = <&main_cpsw2g_default_pins>; 993 status = "okay"; 994}; 995 996&main_cpsw1_mdio { 997 pinctrl-names = "default"; 998 pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; 999 status = "okay"; 1000 1001 main_cpsw1_phy0: ethernet-phy@0 { 1002 reg = <0>; 1003 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1004 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1005 ti,min-output-impedance; 1006 }; 1007}; 1008 1009&main_cpsw1_port1 { 1010 phy-mode = "rgmii-rxid"; 1011 phy-handle = <&main_cpsw1_phy0>; 1012 status = "okay"; 1013}; 1014 1015&mailbox0_cluster0 { 1016 status = "okay"; 1017 interrupts = <436>; 1018 1019 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1020 ti,mbox-rx = <0 0 0>; 1021 ti,mbox-tx = <1 0 0>; 1022 }; 1023 1024 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1025 ti,mbox-rx = <2 0 0>; 1026 ti,mbox-tx = <3 0 0>; 1027 }; 1028}; 1029 1030&mailbox0_cluster1 { 1031 status = "okay"; 1032 interrupts = <432>; 1033 1034 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1035 ti,mbox-rx = <0 0 0>; 1036 ti,mbox-tx = <1 0 0>; 1037 }; 1038 1039 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1040 ti,mbox-rx = <2 0 0>; 1041 ti,mbox-tx = <3 0 0>; 1042 }; 1043}; 1044 1045&mailbox0_cluster2 { 1046 status = "okay"; 1047 interrupts = <428>; 1048 1049 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1050 ti,mbox-rx = <0 0 0>; 1051 ti,mbox-tx = <1 0 0>; 1052 }; 1053 1054 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1055 ti,mbox-rx = <2 0 0>; 1056 ti,mbox-tx = <3 0 0>; 1057 }; 1058}; 1059 1060&mailbox0_cluster3 { 1061 status = "okay"; 1062 interrupts = <424>; 1063 1064 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 1065 ti,mbox-rx = <0 0 0>; 1066 ti,mbox-tx = <1 0 0>; 1067 }; 1068 1069 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 1070 ti,mbox-rx = <2 0 0>; 1071 ti,mbox-tx = <3 0 0>; 1072 }; 1073}; 1074 1075&mailbox0_cluster4 { 1076 status = "okay"; 1077 interrupts = <420>; 1078 1079 mbox_c71_0: mbox-c71-0 { 1080 ti,mbox-rx = <0 0 0>; 1081 ti,mbox-tx = <1 0 0>; 1082 }; 1083 1084 mbox_c71_1: mbox-c71-1 { 1085 ti,mbox-rx = <2 0 0>; 1086 ti,mbox-tx = <3 0 0>; 1087 }; 1088}; 1089 1090&mailbox0_cluster5 { 1091 status = "okay"; 1092 interrupts = <416>; 1093 1094 mbox_c71_2: mbox-c71-2 { 1095 ti,mbox-rx = <0 0 0>; 1096 ti,mbox-tx = <1 0 0>; 1097 }; 1098}; 1099 1100&mcu_r5fss0_core0 { 1101 status = "okay"; 1102 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1103 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1104 <&mcu_r5fss0_core0_memory_region>; 1105}; 1106 1107&mcu_r5fss0_core1 { 1108 status = "okay"; 1109 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1110 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1111 <&mcu_r5fss0_core1_memory_region>; 1112}; 1113 1114&main_r5fss0 { 1115 ti,cluster-mode = <0>; 1116}; 1117 1118&main_r5fss1 { 1119 ti,cluster-mode = <0>; 1120}; 1121 1122&main_r5fss2 { 1123 ti,cluster-mode = <0>; 1124}; 1125 1126/* Timers are used by Remoteproc firmware */ 1127&main_timer0 { 1128 status = "reserved"; 1129}; 1130 1131&main_timer1 { 1132 status = "reserved"; 1133}; 1134 1135&main_timer2 { 1136 status = "reserved"; 1137}; 1138 1139&main_timer3 { 1140 status = "reserved"; 1141}; 1142 1143&main_timer4 { 1144 status = "reserved"; 1145}; 1146 1147&main_timer5 { 1148 status = "reserved"; 1149}; 1150 1151&main_timer6 { 1152 status = "reserved"; 1153}; 1154 1155&main_timer7 { 1156 status = "reserved"; 1157}; 1158 1159&main_timer8 { 1160 status = "reserved"; 1161}; 1162 1163&main_timer9 { 1164 status = "reserved"; 1165}; 1166 1167&main_r5fss0_core0 { 1168 status = "okay"; 1169 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1170 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1171 <&main_r5fss0_core0_memory_region>; 1172}; 1173 1174&main_r5fss0_core1 { 1175 status = "okay"; 1176 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1177 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1178 <&main_r5fss0_core1_memory_region>; 1179}; 1180 1181&main_r5fss1_core0 { 1182 status = "okay"; 1183 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1184 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1185 <&main_r5fss1_core0_memory_region>; 1186}; 1187 1188&main_r5fss1_core1 { 1189 status = "okay"; 1190 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1191 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1192 <&main_r5fss1_core1_memory_region>; 1193}; 1194 1195&main_r5fss2_core0 { 1196 status = "okay"; 1197 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 1198 memory-region = <&main_r5fss2_core0_dma_memory_region>, 1199 <&main_r5fss2_core0_memory_region>; 1200}; 1201 1202&main_r5fss2_core1 { 1203 status = "okay"; 1204 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 1205 memory-region = <&main_r5fss2_core1_dma_memory_region>, 1206 <&main_r5fss2_core1_memory_region>; 1207}; 1208 1209&c71_0 { 1210 status = "okay"; 1211 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1212 memory-region = <&c71_0_dma_memory_region>, 1213 <&c71_0_memory_region>; 1214}; 1215 1216&c71_1 { 1217 status = "okay"; 1218 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 1219 memory-region = <&c71_1_dma_memory_region>, 1220 <&c71_1_memory_region>; 1221}; 1222 1223&c71_2 { 1224 status = "okay"; 1225 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 1226 memory-region = <&c71_2_dma_memory_region>, 1227 <&c71_2_memory_region>; 1228}; 1229 1230&tscadc0 { 1231 pinctrl-0 = <&mcu_adc0_pins_default>; 1232 pinctrl-names = "default"; 1233 status = "okay"; 1234 adc { 1235 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1236 }; 1237}; 1238 1239&tscadc1 { 1240 pinctrl-0 = <&mcu_adc1_pins_default>; 1241 pinctrl-names = "default"; 1242 status = "okay"; 1243 adc { 1244 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1245 }; 1246}; 1247 1248&serdes_refclk { 1249 status = "okay"; 1250 clock-frequency = <100000000>; 1251}; 1252 1253&dss { 1254 status = "okay"; 1255 assigned-clocks = <&k3_clks 218 2>, 1256 <&k3_clks 218 5>, 1257 <&k3_clks 218 14>, 1258 <&k3_clks 218 18>; 1259 assigned-clock-parents = <&k3_clks 218 3>, 1260 <&k3_clks 218 7>, 1261 <&k3_clks 218 16>, 1262 <&k3_clks 218 22>; 1263}; 1264 1265&serdes0 { 1266 status = "okay"; 1267 1268 serdes0_pcie1_link: phy@0 { 1269 reg = <0>; 1270 cdns,num-lanes = <2>; 1271 #phy-cells = <0>; 1272 cdns,phy-type = <PHY_TYPE_PCIE>; 1273 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 1274 }; 1275 1276 serdes0_usb_link: phy@3 { 1277 reg = <3>; 1278 cdns,num-lanes = <1>; 1279 #phy-cells = <0>; 1280 cdns,phy-type = <PHY_TYPE_USB3>; 1281 resets = <&serdes_wiz0 4>; 1282 }; 1283}; 1284 1285&serdes_wiz0 { 1286 status = "okay"; 1287}; 1288 1289&usb_serdes_mux { 1290 idle-states = <0>; /* USB0 to SERDES lane 3 */ 1291}; 1292 1293&usbss0 { 1294 status = "okay"; 1295 pinctrl-0 = <&main_usbss0_pins_default>; 1296 pinctrl-names = "default"; 1297 ti,vbus-divider; 1298}; 1299 1300&usb0 { 1301 dr_mode = "otg"; 1302 maximum-speed = "super-speed"; 1303 phys = <&serdes0_usb_link>; 1304 phy-names = "cdns3,usb3-phy"; 1305}; 1306 1307&serdes_wiz4 { 1308 status = "okay"; 1309}; 1310 1311&serdes4 { 1312 status = "okay"; 1313 serdes4_dp_link: phy@0 { 1314 reg = <0>; 1315 cdns,num-lanes = <4>; 1316 #phy-cells = <0>; 1317 cdns,phy-type = <PHY_TYPE_DP>; 1318 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1319 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1320 }; 1321}; 1322 1323&mhdp { 1324 status = "okay"; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&dp0_pins_default>; 1327 phys = <&serdes4_dp_link>; 1328 phy-names = "dpphy"; 1329}; 1330 1331&dss_ports { 1332 /* DP */ 1333 port { 1334 dpi0_out: endpoint { 1335 remote-endpoint = <&dp0_in>; 1336 }; 1337 }; 1338}; 1339 1340&main_i2c4 { 1341 status = "okay"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&main_i2c4_pins_default>; 1344 clock-frequency = <400000>; 1345 1346 exp4: gpio@20 { 1347 compatible = "ti,tca6408"; 1348 reg = <0x20>; 1349 gpio-controller; 1350 #gpio-cells = <2>; 1351 }; 1352}; 1353 1354&dp0_ports { 1355 port@0 { 1356 reg = <0>; 1357 1358 dp0_in: endpoint { 1359 remote-endpoint = <&dpi0_out>; 1360 }; 1361 }; 1362 1363 port@4 { 1364 reg = <4>; 1365 1366 dp0_out: endpoint { 1367 remote-endpoint = <&dp0_connector_in>; 1368 }; 1369 }; 1370}; 1371 1372&mcu_mcan0 { 1373 status = "okay"; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&mcu_mcan0_pins_default>; 1376 phys = <&transceiver0>; 1377}; 1378 1379&mcu_mcan1 { 1380 status = "okay"; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&mcu_mcan1_pins_default>; 1383 phys = <&transceiver1>; 1384}; 1385 1386&main_mcan16 { 1387 status = "okay"; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&main_mcan16_pins_default>; 1390 phys = <&transceiver2>; 1391}; 1392 1393&main_mcan4 { 1394 status = "okay"; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&main_mcan4_pins_default>; 1397 phys = <&transceiver3>; 1398}; 1399 1400&pcie1_rc { 1401 status = "okay"; 1402 num-lanes = <2>; 1403 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 1404 phys = <&serdes0_pcie1_link>; 1405 phy-names = "pcie-phy"; 1406}; 1407 1408&serdes1 { 1409 status = "okay"; 1410 1411 serdes1_pcie0_link: phy@0 { 1412 reg = <0>; 1413 cdns,num-lanes = <4>; 1414 #phy-cells = <0>; 1415 cdns,phy-type = <PHY_TYPE_PCIE>; 1416 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, 1417 <&serdes_wiz1 3>, <&serdes_wiz1 4>; 1418 }; 1419}; 1420 1421&serdes_wiz1 { 1422 status = "okay"; 1423}; 1424 1425&pcie0_rc { 1426 status = "okay"; 1427 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1428 phys = <&serdes1_pcie0_link>; 1429 phy-names = "pcie-phy"; 1430}; 1431 1432&k3_clks { 1433 /* Confiure AUDIO_EXT_REFCLK1 pin as output */ 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 1436}; 1437 1438&main_i2c3 { 1439 status = "okay"; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&main_i2c3_pins_default>; 1442 clock-frequency = <400000>; 1443 1444 exp3: gpio@20 { 1445 compatible = "ti,tca6408"; 1446 reg = <0x20>; 1447 gpio-controller; 1448 #gpio-cells = <2>; 1449 }; 1450 1451 pcm3168a_1: audio-codec@44 { 1452 compatible = "ti,pcm3168a"; 1453 reg = <0x44>; 1454 #sound-dai-cells = <1>; 1455 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 1456 clocks = <&audio_refclk1>; 1457 clock-names = "scki"; 1458 VDD1-supply = <&vsys_3v3>; 1459 VDD2-supply = <&vsys_3v3>; 1460 VCCAD1-supply = <&vsys_5v0>; 1461 VCCAD2-supply = <&vsys_5v0>; 1462 VCCDA1-supply = <&vsys_5v0>; 1463 VCCDA2-supply = <&vsys_5v0>; 1464 }; 1465}; 1466 1467&mcasp0 { 1468 status = "okay"; 1469 #sound-dai-cells = <0>; 1470 pinctrl-names = "default"; 1471 pinctrl-0 = <&main_mcasp0_pins_default>; 1472 op-mode = <0>; /* MCASP_IIS_MODE */ 1473 tdm-slots = <2>; 1474 auxclk-fs-ratio = <256>; 1475 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1476 0 0 0 1 1477 2 0 0 0 1478 0 0 0 0 1479 0 0 0 0 1480 >; 1481}; 1482