1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 and J742S2 SoC Family 4 * 5 * TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 6 * TRM (j742s2): https://www.ti.com/lit/pdf/spruje3 7 * 8 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 * 10 */ 11 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/soc/ti,sci_pm_domain.h> 15 16#include "k3-pinctrl.h" 17 18/ { 19 interrupt-parent = <&gic500>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 L2_0: l2-cache0 { 24 compatible = "cache"; 25 cache-level = <2>; 26 cache-unified; 27 cache-size = <0x200000>; 28 cache-line-size = <64>; 29 cache-sets = <1024>; 30 next-level-cache = <&msmc_l3>; 31 }; 32 33 L2_1: l2-cache1 { 34 compatible = "cache"; 35 cache-level = <2>; 36 cache-unified; 37 cache-size = <0x200000>; 38 cache-line-size = <64>; 39 cache-sets = <1024>; 40 next-level-cache = <&msmc_l3>; 41 }; 42 43 msmc_l3: l3-cache0 { 44 compatible = "cache"; 45 cache-level = <3>; 46 cache-unified; 47 }; 48 49 firmware { 50 optee { 51 compatible = "linaro,optee-tz"; 52 method = "smc"; 53 }; 54 55 psci: psci { 56 compatible = "arm,psci-1.0"; 57 method = "smc"; 58 }; 59 }; 60 61 a72_timer0: timer-cl0-cpu0 { 62 compatible = "arm,armv8-timer"; 63 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 64 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 65 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 66 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 67 }; 68 69 pmu: pmu { 70 compatible = "arm,cortex-a72-pmu"; 71 /* Recommendation from GIC500 TRM Table A.3 */ 72 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 73 }; 74 75 cbass_main: bus@100000 { 76 bootph-all; 77 compatible = "simple-bus"; 78 #address-cells = <2>; 79 #size-cells = <2>; 80 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 81 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 82 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ 83 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ 84 <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ 85 <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ 86 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/ 87 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/ 88 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/ 89 <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/ 90 <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ 91 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ 92 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ 93 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ 94 <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */ 95 <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */ 96 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ 97 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ 98 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 99 <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ 100 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ 101 <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */ 102 <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */ 103 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */ 104 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */ 105 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 106 107 /* MCUSS_WKUP Range */ 108 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 109 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 110 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 111 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 112 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 113 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 114 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 115 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 116 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 117 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 118 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 119 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; 120 121 cbass_mcu_wakeup: bus@28380000 { 122 bootph-all; 123 compatible = "simple-bus"; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 127 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 128 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 129 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 130 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 131 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 132 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 133 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 134 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 135 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 136 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */ 137 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */ 138 }; 139 }; 140 141 thermal_zones: thermal-zones { 142 #include "k3-j784s4-j742s2-thermal-common.dtsi" 143 }; 144}; 145 146/* Now include peripherals from each bus segment */ 147#include "k3-j784s4-j742s2-main-common.dtsi" 148#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi" 149