1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2/** 3 * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 4 * and ENET-2 Expansion slots of J784S4 EVM. 5 * 6 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9/dts-v1/; 10/plugin/; 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/phy/phy-cadence.h> 14#include <dt-bindings/phy/phy.h> 15 16#include "k3-serdes.h" 17 18&{/} { 19 aliases { 20 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 21 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 22 ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; 23 }; 24}; 25 26&main_cpsw0 { 27 pinctrl-names = "default"; 28 status = "okay"; 29}; 30 31&main_cpsw0_port1 { 32 phy-mode = "usxgmii"; 33 mac-address = [00 00 00 00 00 00]; 34 phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; 35 phy-names = "mac", "serdes"; 36 status = "okay"; 37 fixed-link { 38 speed = <5000>; 39 full-duplex; 40 }; 41}; 42 43&main_cpsw0_port2 { 44 phy-mode = "usxgmii"; 45 mac-address = [00 00 00 00 00 00]; 46 phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; 47 phy-names = "mac", "serdes"; 48 status = "okay"; 49 fixed-link { 50 speed = <5000>; 51 full-duplex; 52 }; 53}; 54 55&serdes_wiz2 { 56 assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */ 57 status = "okay"; 58}; 59 60&serdes2 { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 status = "okay"; 64 65 serdes2_usxgmii_link: phy@2 { 66 reg = <2>; 67 cdns,num-lanes = <2>; 68 #phy-cells = <0>; 69 cdns,phy-type = <PHY_TYPE_USXGMII>; 70 resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>; 71 }; 72}; 73 74&serdes_ln_ctrl { 75 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 76 <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>, 77 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 78 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 79 <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>, 80 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>; 81}; 82