1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J742S2 SoC Family 4 * 5 * TRM: https://www.ti.com/lit/pdf/spruje3 6 * 7 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 8 * 9 */ 10#include "k3-j784s4-j742s2-common.dtsi" 11 12/ { 13 model = "Texas Instruments K3 J742S2 SoC"; 14 compatible = "ti,j742s2"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu-map { 21 cluster0: cluster0 { 22 core0 { 23 cpu = <&cpu0>; 24 }; 25 26 core1 { 27 cpu = <&cpu1>; 28 }; 29 30 core2 { 31 cpu = <&cpu2>; 32 }; 33 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 compatible = "arm,cortex-a72"; 42 reg = <0x000>; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 i-cache-size = <0xc000>; 46 i-cache-line-size = <64>; 47 i-cache-sets = <256>; 48 d-cache-size = <0x8000>; 49 d-cache-line-size = <64>; 50 d-cache-sets = <256>; 51 next-level-cache = <&L2_0>; 52 }; 53 54 cpu1: cpu@1 { 55 compatible = "arm,cortex-a72"; 56 reg = <0x001>; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 i-cache-size = <0xc000>; 60 i-cache-line-size = <64>; 61 i-cache-sets = <256>; 62 d-cache-size = <0x8000>; 63 d-cache-line-size = <64>; 64 d-cache-sets = <256>; 65 next-level-cache = <&L2_0>; 66 }; 67 68 cpu2: cpu@2 { 69 compatible = "arm,cortex-a72"; 70 reg = <0x002>; 71 device_type = "cpu"; 72 enable-method = "psci"; 73 i-cache-size = <0xc000>; 74 i-cache-line-size = <64>; 75 i-cache-sets = <256>; 76 d-cache-size = <0x8000>; 77 d-cache-line-size = <64>; 78 d-cache-sets = <256>; 79 next-level-cache = <&L2_0>; 80 }; 81 82 cpu3: cpu@3 { 83 compatible = "arm,cortex-a72"; 84 reg = <0x003>; 85 device_type = "cpu"; 86 enable-method = "psci"; 87 i-cache-size = <0xc000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <256>; 90 d-cache-size = <0x8000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <256>; 93 next-level-cache = <&L2_0>; 94 }; 95 }; 96}; 97 98#include "k3-j742s2-main.dtsi" 99