1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the J722S EVM 4 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Schematics: https://www.ti.com/lit/zip/sprr495 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy.h> 13#include "k3-j722s.dtsi" 14#include "k3-serdes.h" 15 16/ { 17 compatible = "ti,j722s-evm", "ti,j722s"; 18 model = "Texas Instruments J722S EVM"; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial2 = &main_uart0; 23 mmc0 = &sdhci0; 24 mmc1 = &sdhci1; 25 }; 26 27 chosen { 28 stdout-path = &main_uart0; 29 }; 30 31 memory@80000000 { 32 /* 8G RAM */ 33 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 34 <0x00000008 0x80000000 0x00000001 0x80000000>; 35 device_type = "memory"; 36 bootph-pre-ram; 37 }; 38 39 reserved_memory: reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 secure_tfa_ddr: tfa@9e780000 { 45 reg = <0x00 0x9e780000 0x00 0x80000>; 46 no-map; 47 }; 48 49 secure_ddr: optee@9e800000 { 50 reg = <0x00 0x9e800000 0x00 0x01800000>; 51 no-map; 52 }; 53 54 wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa0100000 0x00 0xf00000>; 57 no-map; 58 }; 59 60 }; 61 62 vmain_pd: regulator-0 { 63 /* TPS65988 PD CONTROLLER OUTPUT */ 64 compatible = "regulator-fixed"; 65 regulator-name = "vmain_pd"; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 regulator-always-on; 69 regulator-boot-on; 70 bootph-all; 71 }; 72 73 vsys_5v0: regulator-vsys5v0 { 74 /* Output of LM5140 */ 75 compatible = "regulator-fixed"; 76 regulator-name = "vsys_5v0"; 77 regulator-min-microvolt = <5000000>; 78 regulator-max-microvolt = <5000000>; 79 vin-supply = <&vmain_pd>; 80 regulator-always-on; 81 regulator-boot-on; 82 }; 83 84 vdd_mmc1: regulator-mmc1 { 85 /* TPS22918DBVR */ 86 compatible = "regulator-fixed"; 87 regulator-name = "vdd_mmc1"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 regulator-boot-on; 91 enable-active-high; 92 gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; 93 bootph-all; 94 }; 95 96 vdd_sd_dv: regulator-TLV71033 { 97 compatible = "regulator-gpio"; 98 regulator-name = "tlv71033"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&vdd_sd_dv_pins_default>; 101 regulator-min-microvolt = <1800000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-boot-on; 104 vin-supply = <&vsys_5v0>; 105 gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; 106 states = <1800000 0x0>, 107 <3300000 0x1>; 108 }; 109 110 vsys_io_3v3: regulator-vsys-io-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "vsys_io_3v3"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 regulator-always-on; 116 regulator-boot-on; 117 }; 118 119 vsys_io_1v8: regulator-vsys-io-1v8 { 120 compatible = "regulator-fixed"; 121 regulator-name = "vsys_io_1v8"; 122 regulator-min-microvolt = <1800000>; 123 regulator-max-microvolt = <1800000>; 124 regulator-always-on; 125 regulator-boot-on; 126 }; 127 128 vsys_io_1v2: regulator-vsys-io-1v2 { 129 compatible = "regulator-fixed"; 130 regulator-name = "vsys_io_1v2"; 131 regulator-min-microvolt = <1200000>; 132 regulator-max-microvolt = <1200000>; 133 regulator-always-on; 134 regulator-boot-on; 135 }; 136 137 codec_audio: sound { 138 compatible = "simple-audio-card"; 139 simple-audio-card,name = "J722S-EVM"; 140 simple-audio-card,widgets = 141 "Headphone", "Headphone Jack", 142 "Line", "Line In", 143 "Microphone", "Microphone Jack"; 144 simple-audio-card,routing = 145 "Headphone Jack", "HPLOUT", 146 "Headphone Jack", "HPROUT", 147 "LINE1L", "Line In", 148 "LINE1R", "Line In", 149 "MIC3R", "Microphone Jack", 150 "Microphone Jack", "Mic Bias"; 151 simple-audio-card,format = "dsp_b"; 152 simple-audio-card,bitclock-master = <&sound_master>; 153 simple-audio-card,frame-master = <&sound_master>; 154 simple-audio-card,bitclock-inversion; 155 156 simple-audio-card,cpu { 157 sound-dai = <&mcasp1>; 158 }; 159 160 sound_master: simple-audio-card,codec { 161 sound-dai = <&tlv320aic3106>; 162 clocks = <&audio_refclk1>; 163 }; 164 }; 165}; 166 167&main_pmx0 { 168 169 main_i2c0_pins_default: main-i2c0-default-pins { 170 pinctrl-single,pins = < 171 J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ 172 J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ 173 >; 174 bootph-all; 175 }; 176 177 main_uart0_pins_default: main-uart0-default-pins { 178 pinctrl-single,pins = < 179 J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ 180 J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ 181 >; 182 bootph-all; 183 }; 184 185 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 186 pinctrl-single,pins = < 187 J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ 188 >; 189 bootph-all; 190 }; 191 192 main_mmc1_pins_default: main-mmc1-default-pins { 193 pinctrl-single,pins = < 194 J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ 195 J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ 196 J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ 197 J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ 198 J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ 199 J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ 200 J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ 201 >; 202 bootph-all; 203 }; 204 205 mdio_pins_default: mdio-default-pins { 206 pinctrl-single,pins = < 207 J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ 208 J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ 209 >; 210 }; 211 212 ospi0_pins_default: ospi0-default-pins { 213 pinctrl-single,pins = < 214 J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ 215 J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ 216 J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ 217 J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ 218 J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ 219 J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ 220 J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ 221 J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ 222 J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ 223 J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ 224 J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ 225 >; 226 bootph-all; 227 }; 228 229 rgmii1_pins_default: rgmii1-default-pins { 230 pinctrl-single,pins = < 231 J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ 232 J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ 233 J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ 234 J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ 235 J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ 236 J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ 237 J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ 238 J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ 239 J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ 240 J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ 241 J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ 242 J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ 243 >; 244 }; 245 246 main_usb1_pins_default: main-usb1-default-pins { 247 pinctrl-single,pins = < 248 J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ 249 >; 250 }; 251 252 main_mcasp1_pins_default: main-mcasp1-default-pins { 253 pinctrl-single,pins = < 254 J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */ 255 J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */ 256 J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */ 257 J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */ 258 >; 259 }; 260 261 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 262 pinctrl-single,pins = < 263 J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ 264 >; 265 }; 266}; 267 268&cpsw3g { 269 status = "okay"; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&rgmii1_pins_default>; 272}; 273 274&cpsw3g_mdio { 275 status = "okay"; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&mdio_pins_default>; 278 279 cpsw3g_phy0: ethernet-phy@0 { 280 reg = <0>; 281 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 282 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 283 ti,min-output-impedance; 284 }; 285}; 286 287&cpsw_port1 { 288 phy-mode = "rgmii-rxid"; 289 phy-handle = <&cpsw3g_phy0>; 290 status = "okay"; 291}; 292 293&main_gpio1 { 294 status = "okay"; 295}; 296 297&main_uart0 { 298 pinctrl-names = "default"; 299 pinctrl-0 = <&main_uart0_pins_default>; 300 status = "okay"; 301 bootph-all; 302}; 303 304&mcu_pmx0 { 305 306 wkup_uart0_pins_default: wkup-uart0-default-pins { 307 pinctrl-single,pins = < 308 J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ 309 J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ 310 J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ 311 J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ 312 >; 313 bootph-all; 314 }; 315 316 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 317 pinctrl-single,pins = < 318 J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ 319 J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ 320 >; 321 bootph-all; 322 }; 323}; 324 325&wkup_uart0 { 326 /* WKUP UART0 is used by Device Manager firmware */ 327 pinctrl-names = "default"; 328 pinctrl-0 = <&wkup_uart0_pins_default>; 329 status = "reserved"; 330 bootph-all; 331}; 332 333&wkup_i2c0 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&wkup_i2c0_pins_default>; 336 clock-frequency = <400000>; 337 status = "okay"; 338 bootph-all; 339}; 340 341&k3_clks { 342 /* Configure AUDIO_EXT_REFCLK1 pin as output */ 343 pinctrl-names = "default"; 344 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 345}; 346 347&main_i2c0 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&main_i2c0_pins_default>; 350 clock-frequency = <400000>; 351 status = "okay"; 352 bootph-all; 353 354 exp1: gpio@23 { 355 compatible = "ti,tca6424"; 356 reg = <0x23>; 357 gpio-controller; 358 #gpio-cells = <2>; 359 gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", 360 "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", 361 "CSI_VIO_SEL", "USB2.0_MUX_SEL", 362 "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", 363 "LMK1_OE1", "LMK1_OE0", 364 "LMK2_OE0", "LMK2_OE1", 365 "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", 366 "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", 367 "USER_LED2", "MCAN0_STB", 368 "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", 369 "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", 370 "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; 371 372 p05-hog { 373 /* P05 - USB2.0_MUX_SEL */ 374 gpio-hog; 375 gpios = <5 GPIO_ACTIVE_HIGH>; 376 output-high; 377 }; 378 379 p01_hog: p01-hog { 380 /* P01 - TRC_MUX_SEL */ 381 gpio-hog; 382 gpios = <0 GPIO_ACTIVE_HIGH>; 383 output-low; 384 line-name = "TRC_MUX_SEL"; 385 }; 386 387 p02_hog: p02-hog { 388 /* P02 - MCASP1_FET_SEL */ 389 gpio-hog; 390 gpios = <2 GPIO_ACTIVE_HIGH>; 391 output-high; 392 line-name = "MCASP1_FET_SEL"; 393 }; 394 395 p13_hog: p13-hog { 396 /* P13 - GPIO_AUD_RSTn */ 397 gpio-hog; 398 gpios = <13 GPIO_ACTIVE_HIGH>; 399 output-high; 400 line-name = "GPIO_AUD_RSTn"; 401 }; 402 }; 403 404 tlv320aic3106: audio-codec@1b { 405 #sound-dai-cells = <0>; 406 compatible = "ti,tlv320aic3106"; 407 reg = <0x1b>; 408 ai3x-micbias-vg = <1>; /* 2.0V */ 409 AVDD-supply = <&vsys_io_3v3>; 410 IOVDD-supply = <&vsys_io_3v3>; 411 DRVDD-supply = <&vsys_io_3v3>; 412 DVDD-supply = <&vsys_io_1v8>; 413 }; 414}; 415 416&ospi0 { 417 pinctrl-names = "default"; 418 pinctrl-0 = <&ospi0_pins_default>; 419 status = "okay"; 420 421 flash@0 { 422 compatible = "jedec,spi-nor"; 423 reg = <0x0>; 424 spi-tx-bus-width = <8>; 425 spi-rx-bus-width = <8>; 426 spi-max-frequency = <25000000>; 427 cdns,tshsl-ns = <60>; 428 cdns,tsd2d-ns = <60>; 429 cdns,tchsh-ns = <60>; 430 cdns,tslch-ns = <60>; 431 cdns,read-delay = <4>; 432 bootph-all; 433 434 partitions { 435 compatible = "fixed-partitions"; 436 #address-cells = <1>; 437 #size-cells = <1>; 438 439 partition@0 { 440 label = "ospi.tiboot3"; 441 reg = <0x00 0x80000>; 442 }; 443 444 partition@80000 { 445 label = "ospi.tispl"; 446 reg = <0x80000 0x200000>; 447 }; 448 449 partition@280000 { 450 label = "ospi.u-boot"; 451 reg = <0x280000 0x400000>; 452 }; 453 454 partition@680000 { 455 label = "ospi.env"; 456 reg = <0x680000 0x40000>; 457 }; 458 459 partition@6c0000 { 460 label = "ospi.env.backup"; 461 reg = <0x6c0000 0x40000>; 462 }; 463 464 partition@800000 { 465 label = "ospi.rootfs"; 466 reg = <0x800000 0x37c0000>; 467 }; 468 469 partition@3fc0000 { 470 label = "ospi.phypattern"; 471 reg = <0x3fc0000 0x40000>; 472 }; 473 }; 474 }; 475 476}; 477 478&sdhci0 { 479 disable-wp; 480 bootph-all; 481 ti,driver-strength-ohm = <50>; 482 status = "okay"; 483}; 484 485&sdhci1 { 486 /* SD/MMC */ 487 vmmc-supply = <&vdd_mmc1>; 488 vqmmc-supply = <&vdd_sd_dv>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&main_mmc1_pins_default>; 491 ti,driver-strength-ohm = <50>; 492 disable-wp; 493 status = "okay"; 494 bootph-all; 495}; 496 497&serdes_ln_ctrl { 498 idle-states = <J722S_SERDES0_LANE0_USB>, 499 <J722S_SERDES1_LANE0_PCIE0_LANE0>; 500}; 501 502&serdes0 { 503 status = "okay"; 504 serdes0_usb_link: phy@0 { 505 reg = <0>; 506 cdns,num-lanes = <1>; 507 #phy-cells = <0>; 508 cdns,phy-type = <PHY_TYPE_USB3>; 509 resets = <&serdes_wiz0 1>; 510 }; 511}; 512 513&serdes1 { 514 status = "okay"; 515 serdes1_pcie_link: phy@0 { 516 reg = <0>; 517 cdns,num-lanes = <1>; 518 #phy-cells = <0>; 519 cdns,phy-type = <PHY_TYPE_PCIE>; 520 resets = <&serdes_wiz1 1>; 521 }; 522}; 523 524&pcie0_rc { 525 reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; 526 phys = <&serdes1_pcie_link>; 527 phy-names = "pcie-phy"; 528 status = "okay"; 529}; 530 531&usbss0 { 532 ti,vbus-divider; 533 status = "okay"; 534}; 535 536&usb0 { 537 dr_mode = "otg"; 538 usb-role-switch; 539}; 540 541&usbss1 { 542 pinctrl-names = "default"; 543 pinctrl-0 = <&main_usb1_pins_default>; 544 ti,vbus-divider; 545 status = "okay"; 546}; 547 548&usb1 { 549 dr_mode = "host"; 550 maximum-speed = "super-speed"; 551 phys = <&serdes0_usb_link>; 552 phy-names = "cdns3,usb3-phy"; 553}; 554 555&mcasp1 { 556 status = "okay"; 557 #sound-dai-cells = <0>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&main_mcasp1_pins_default>; 560 op-mode = <0>; /* MCASP_IIS_MODE */ 561 tdm-slots = <2>; 562 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 563 1 0 2 0 564 0 0 0 0 565 0 0 0 0 566 0 0 0 0 567 >; 568}; 569