xref: /linux/arch/arm64/boot/dts/ti/k3-j722s-evm.dts (revision 4b660dbd9ee2059850fd30e0df420ca7a38a1856)
1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Device Tree file for the J722S EVM
4 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Schematics: https://www.ti.com/lit/zip/sprr495
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/net/ti-dp83867.h>
12#include "k3-j722s.dtsi"
13
14/ {
15	compatible = "ti,j722s-evm", "ti,j722s";
16	model = "Texas Instruments J722S EVM";
17
18	aliases {
19		serial0 = &wkup_uart0;
20		serial2 = &main_uart0;
21		mmc0 = &sdhci0;
22		mmc1 = &sdhci1;
23	};
24
25	chosen {
26		stdout-path = &main_uart0;
27	};
28
29	memory@80000000 {
30		/* 8G RAM */
31		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
32		      <0x00000008 0x80000000 0x00000001 0x80000000>;
33		device_type = "memory";
34		bootph-pre-ram;
35	};
36
37	reserved_memory: reserved-memory {
38		#address-cells = <2>;
39		#size-cells = <2>;
40		ranges;
41
42		secure_tfa_ddr: tfa@9e780000 {
43			reg = <0x00 0x9e780000 0x00 0x80000>;
44			no-map;
45		};
46
47		secure_ddr: optee@9e800000 {
48			reg = <0x00 0x9e800000 0x00 0x01800000>;
49			no-map;
50		};
51
52		wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
53			compatible = "shared-dma-pool";
54			reg = <0x00 0xa0100000 0x00 0xf00000>;
55			no-map;
56		};
57
58	};
59
60	vmain_pd: regulator-0 {
61		/* TPS65988 PD CONTROLLER OUTPUT */
62		compatible = "regulator-fixed";
63		regulator-name = "vmain_pd";
64		regulator-min-microvolt = <5000000>;
65		regulator-max-microvolt = <5000000>;
66		regulator-always-on;
67		regulator-boot-on;
68		bootph-all;
69	};
70
71	vsys_5v0: regulator-vsys5v0 {
72		/* Output of LM5140 */
73		compatible = "regulator-fixed";
74		regulator-name = "vsys_5v0";
75		regulator-min-microvolt = <5000000>;
76		regulator-max-microvolt = <5000000>;
77		vin-supply = <&vmain_pd>;
78		regulator-always-on;
79		regulator-boot-on;
80	};
81
82	vdd_mmc1: regulator-mmc1 {
83		/* TPS22918DBVR */
84		compatible = "regulator-fixed";
85		regulator-name = "vdd_mmc1";
86		regulator-min-microvolt = <3300000>;
87		regulator-max-microvolt = <3300000>;
88		regulator-boot-on;
89		enable-active-high;
90		gpio = <&exp1 15 GPIO_ACTIVE_HIGH>;
91		bootph-all;
92	};
93
94	vdd_sd_dv: regulator-TLV71033 {
95		compatible = "regulator-gpio";
96		regulator-name = "tlv71033";
97		pinctrl-names = "default";
98		pinctrl-0 = <&vdd_sd_dv_pins_default>;
99		regulator-min-microvolt = <1800000>;
100		regulator-max-microvolt = <3300000>;
101		regulator-boot-on;
102		vin-supply = <&vsys_5v0>;
103		gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
104		states = <1800000 0x0>,
105			 <3300000 0x1>;
106	};
107
108	vsys_io_1v8: regulator-vsys-io-1v8 {
109		compatible = "regulator-fixed";
110		regulator-name = "vsys_io_1v8";
111		regulator-min-microvolt = <1800000>;
112		regulator-max-microvolt = <1800000>;
113		regulator-always-on;
114		regulator-boot-on;
115	};
116
117	vsys_io_1v2: regulator-vsys-io-1v2 {
118		compatible = "regulator-fixed";
119		regulator-name = "vsys_io_1v2";
120		regulator-min-microvolt = <1200000>;
121		regulator-max-microvolt = <1200000>;
122		regulator-always-on;
123		regulator-boot-on;
124	};
125};
126
127&main_pmx0 {
128
129	main_i2c0_pins_default: main-i2c0-default-pins {
130		pinctrl-single,pins = <
131			J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
132			J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
133		>;
134		bootph-all;
135	};
136
137	main_uart0_pins_default: main-uart0-default-pins {
138		pinctrl-single,pins = <
139			J722S_IOPAD(0x01c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
140			J722S_IOPAD(0x01cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
141		>;
142		bootph-all;
143	};
144
145	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
146		pinctrl-single,pins = <
147			J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */
148		>;
149		bootph-all;
150	};
151
152	main_mmc1_pins_default: main-mmc1-default-pins {
153		pinctrl-single,pins = <
154			J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */
155			J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */
156			J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */
157			J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */
158			J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */
159			J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
160			J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */
161		>;
162		bootph-all;
163	};
164
165	mdio_pins_default: mdio-default-pins {
166		pinctrl-single,pins = <
167			J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */
168			J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */
169		>;
170	};
171
172	ospi0_pins_default: ospi0-default-pins {
173		pinctrl-single,pins = <
174			J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */
175			J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */
176			J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */
177			J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */
178			J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */
179			J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */
180			J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */
181			J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */
182			J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */
183			J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */
184			J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */
185		>;
186		bootph-all;
187	};
188
189	rgmii1_pins_default: rgmii1-default-pins {
190		pinctrl-single,pins = <
191			J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */
192			J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */
193			J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */
194			J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */
195			J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */
196			J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */
197			J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */
198			J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */
199			J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */
200			J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */
201			J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
202			J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
203		>;
204	};
205};
206
207&cpsw3g {
208	status = "okay";
209	pinctrl-names = "default";
210	pinctrl-0 = <&rgmii1_pins_default>;
211};
212
213&cpsw3g_mdio {
214	status = "okay";
215	pinctrl-names = "default";
216	pinctrl-0 = <&mdio_pins_default>;
217
218	cpsw3g_phy0: ethernet-phy@0 {
219		reg = <0>;
220		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
221		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
222		ti,min-output-impedance;
223	};
224};
225
226&cpsw_port1 {
227	phy-mode = "rgmii-rxid";
228	phy-handle = <&cpsw3g_phy0>;
229};
230
231&cpsw_port2 {
232	status = "disabled";
233};
234
235&main_gpio1 {
236	status = "okay";
237};
238
239&main_uart0 {
240	pinctrl-names = "default";
241	pinctrl-0 = <&main_uart0_pins_default>;
242	status = "okay";
243	bootph-all;
244};
245
246&mcu_pmx0 {
247
248	wkup_uart0_pins_default: wkup-uart0-default-pins {
249		pinctrl-single,pins = <
250			J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C7) WKUP_UART0_CTSn */
251			J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (C6) WKUP_UART0_RTSn */
252			J722S_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
253			J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
254		>;
255		bootph-all;
256	};
257
258	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
259		pinctrl-single,pins = <
260			J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0)	/* (C7) WKUP_I2C0_SCL */
261			J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0)	/* (C6) WKUP_I2C1_SDA */
262		>;
263		bootph-all;
264	};
265};
266
267&wkup_uart0 {
268	/* WKUP UART0 is used by Device Manager firmware */
269	pinctrl-names = "default";
270	pinctrl-0 = <&wkup_uart0_pins_default>;
271	status = "reserved";
272	bootph-all;
273};
274
275&wkup_i2c0 {
276	pinctrl-names = "default";
277	pinctrl-0 = <&wkup_i2c0_pins_default>;
278	clock-frequency = <400000>;
279	status = "okay";
280	bootph-all;
281};
282
283&main_i2c0 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&main_i2c0_pins_default>;
286	clock-frequency = <400000>;
287	status = "okay";
288	bootph-all;
289
290	exp1: gpio@23 {
291		compatible = "ti,tca6424";
292		reg = <0x23>;
293		gpio-controller;
294		#gpio-cells = <2>;
295		gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL",
296				  "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#",
297				  "CSI_VIO_SEL", "USB2.0_MUX_SEL",
298				  "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2",
299				  "LMK1_OE1", "LMK1_OE0",
300				  "LMK2_OE0", "LMK2_OE1",
301				  "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn",
302				  "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN",
303				  "USER_LED2", "MCAN0_STB",
304				  "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
305				  "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
306				  "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
307	};
308};
309
310&ospi0 {
311	pinctrl-names = "default";
312	pinctrl-0 = <&ospi0_pins_default>;
313	status = "okay";
314
315	flash@0 {
316		compatible = "jedec,spi-nor";
317		reg = <0x0>;
318		spi-tx-bus-width = <8>;
319		spi-rx-bus-width = <8>;
320		spi-max-frequency = <25000000>;
321		cdns,tshsl-ns = <60>;
322		cdns,tsd2d-ns = <60>;
323		cdns,tchsh-ns = <60>;
324		cdns,tslch-ns = <60>;
325		cdns,read-delay = <4>;
326		bootph-all;
327
328		partitions {
329			compatible = "fixed-partitions";
330			#address-cells = <1>;
331			#size-cells = <1>;
332
333			partition@0 {
334				label = "ospi.tiboot3";
335				reg = <0x00 0x80000>;
336			};
337
338			partition@80000 {
339				label = "ospi.tispl";
340				reg = <0x80000 0x200000>;
341			};
342
343			partition@280000 {
344				label = "ospi.u-boot";
345				reg = <0x280000 0x400000>;
346			};
347
348			partition@680000 {
349				label = "ospi.env";
350				reg = <0x680000 0x40000>;
351			};
352
353			partition@6c0000 {
354				label = "ospi.env.backup";
355				reg = <0x6c0000 0x40000>;
356			};
357
358			partition@800000 {
359				label = "ospi.rootfs";
360				reg = <0x800000 0x37c0000>;
361			};
362
363			partition@3fc0000 {
364				label = "ospi.phypattern";
365				reg = <0x3fc0000 0x40000>;
366			};
367		};
368	};
369
370};
371
372&sdhci1 {
373	/* SD/MMC */
374	vmmc-supply = <&vdd_mmc1>;
375	vqmmc-supply = <&vdd_sd_dv>;
376	pinctrl-names = "default";
377	pinctrl-0 = <&main_mmc1_pins_default>;
378	ti,driver-strength-ohm = <50>;
379	disable-wp;
380	no-1-8-v;
381	status = "okay";
382	bootph-all;
383};
384