1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * SoM: https://www.ti.com/lit/zip/sprr439 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9 10#include "k3-j721s2.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 memory@80000000 { 15 device_type = "memory"; 16 bootph-all; 17 /* 16 GB RAM */ 18 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 19 <0x00000008 0x80000000 0x00000003 0x80000000>; 20 }; 21 22 /* Reserving memory regions still pending */ 23 reserved_memory: reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 secure_ddr: optee@9e800000 { 29 reg = <0x00 0x9e800000 0x00 0x01800000>; 30 alignment = <0x1000>; 31 no-map; 32 }; 33 34 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 35 compatible = "shared-dma-pool"; 36 reg = <0x00 0xa0000000 0x00 0x100000>; 37 no-map; 38 }; 39 40 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 41 compatible = "shared-dma-pool"; 42 reg = <0x00 0xa0100000 0x00 0xf00000>; 43 no-map; 44 }; 45 46 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 47 compatible = "shared-dma-pool"; 48 reg = <0x00 0xa1000000 0x00 0x100000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa1100000 0x00 0xf00000>; 55 no-map; 56 }; 57 58 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa2000000 0x00 0x100000>; 61 no-map; 62 }; 63 64 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa2100000 0x00 0xf00000>; 67 no-map; 68 }; 69 70 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa3000000 0x00 0x100000>; 73 no-map; 74 }; 75 76 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa3100000 0x00 0xf00000>; 79 no-map; 80 }; 81 82 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa4000000 0x00 0x100000>; 85 no-map; 86 }; 87 88 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa4100000 0x00 0xf00000>; 91 no-map; 92 }; 93 94 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa5000000 0x00 0x100000>; 97 no-map; 98 }; 99 100 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 101 compatible = "shared-dma-pool"; 102 reg = <0x00 0xa5100000 0x00 0xf00000>; 103 no-map; 104 }; 105 106 c71_0_dma_memory_region: c71-dma-memory@a6000000 { 107 compatible = "shared-dma-pool"; 108 reg = <0x00 0xa6000000 0x00 0x100000>; 109 no-map; 110 }; 111 112 c71_0_memory_region: c71-memory@a6100000 { 113 compatible = "shared-dma-pool"; 114 reg = <0x00 0xa6100000 0x00 0xf00000>; 115 no-map; 116 }; 117 118 c71_1_dma_memory_region: c71-dma-memory@a7000000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa7000000 0x00 0x100000>; 121 no-map; 122 }; 123 124 c71_1_memory_region: c71-memory@a7100000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa7100000 0x00 0xf00000>; 127 no-map; 128 }; 129 130 rtos_ipc_memory_region: ipc-memories@a8000000 { 131 reg = <0x00 0xa8000000 0x00 0x01c00000>; 132 alignment = <0x1000>; 133 no-map; 134 }; 135 }; 136 137 mux0: mux-controller-0 { 138 compatible = "gpio-mux"; 139 #mux-state-cells = <1>; 140 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; 141 }; 142 143 mux1: mux-controller-1 { 144 compatible = "gpio-mux"; 145 #mux-state-cells = <1>; 146 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; 147 }; 148 149 transceiver0: can-phy0 { 150 /* standby pin has been grounded by default */ 151 compatible = "ti,tcan1042"; 152 #phy-cells = <0>; 153 max-bitrate = <5000000>; 154 }; 155}; 156 157&wkup_pmx0 { 158 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 159 pinctrl-single,pins = < 160 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ 161 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ 162 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ 163 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ 164 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ 165 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ 166 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ 167 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ 168 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ 169 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ 170 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ 171 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ 172 >; 173 bootph-all; 174 }; 175}; 176 177&wkup_pmx1 { 178 pmic_irq_pins_default: pmic-irq-default-pins { 179 pinctrl-single,pins = < 180 /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 181 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) 182 >; 183 }; 184}; 185 186&wkup_pmx2 { 187 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 188 pinctrl-single,pins = < 189 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ 190 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ 191 >; 192 bootph-pre-ram; 193 }; 194}; 195 196&main_pmx0 { 197 main_i2c0_pins_default: main-i2c0-default-pins { 198 pinctrl-single,pins = < 199 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ 200 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ 201 >; 202 }; 203 204 main_mcan16_pins_default: main-mcan16-default-pins { 205 pinctrl-single,pins = < 206 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ 207 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ 208 >; 209 }; 210}; 211 212&wkup_i2c0 { 213 status = "okay"; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&wkup_i2c0_pins_default>; 216 clock-frequency = <400000>; 217 218 eeprom@50 { 219 /* CAV24C256WE-GT3 */ 220 compatible = "atmel,24c256"; 221 reg = <0x50>; 222 }; 223 224 tps659411: pmic@48 { 225 compatible = "ti,tps6594-q1"; 226 reg = <0x48>; 227 system-power-controller; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pmic_irq_pins_default>; 230 interrupt-parent = <&wkup_gpio0>; 231 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 ti,primary-pmic; 235 buck1234-supply = <&vsys_3v3>; 236 buck5-supply = <&vsys_3v3>; 237 ldo1-supply = <&vsys_3v3>; 238 ldo2-supply = <&vsys_3v3>; 239 ldo3-supply = <&vsys_3v3>; 240 ldo4-supply = <&vsys_3v3>; 241 242 regulators { 243 bucka1234: buck1234 { 244 regulator-name = "vdd_cpu_avs"; 245 regulator-min-microvolt = <600000>; 246 regulator-max-microvolt = <900000>; 247 regulator-boot-on; 248 regulator-always-on; 249 bootph-pre-ram; 250 }; 251 252 bucka5: buck5 { 253 regulator-name = "vdd_mcu_0v85"; 254 regulator-min-microvolt = <850000>; 255 regulator-max-microvolt = <850000>; 256 regulator-boot-on; 257 regulator-always-on; 258 }; 259 260 ldoa1: ldo1 { 261 regulator-name = "vdd_mcuwk_0v8"; 262 regulator-min-microvolt = <800000>; 263 regulator-max-microvolt = <800000>; 264 regulator-boot-on; 265 regulator-always-on; 266 }; 267 268 ldoa2: ldo2 { 269 regulator-name = "vdd_mcu_gpioret_3v3"; 270 regulator-min-microvolt = <3300000>; 271 regulator-max-microvolt = <3300000>; 272 regulator-boot-on; 273 regulator-always-on; 274 }; 275 276 ldoa3: ldo3 { 277 regulator-name = "vdd_mcuio_1v8"; 278 regulator-min-microvolt = <1800000>; 279 regulator-max-microvolt = <1800000>; 280 regulator-boot-on; 281 regulator-always-on; 282 }; 283 284 ldoa4: ldo4 { 285 regulator-name = "vda_mcu_1v8"; 286 regulator-min-microvolt = <1800000>; 287 regulator-max-microvolt = <1800000>; 288 regulator-boot-on; 289 regulator-always-on; 290 }; 291 }; 292 }; 293 294 tps659414: pmic@4c { 295 compatible = "ti,tps6594-q1"; 296 reg = <0x4c>; 297 system-power-controller; 298 interrupt-parent = <&wkup_gpio0>; 299 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 300 gpio-controller; 301 #gpio-cells = <2>; 302 buck1-supply = <&vsys_3v3>; 303 buck2-supply = <&vsys_3v3>; 304 buck3-supply = <&vsys_3v3>; 305 buck4-supply = <&vsys_3v3>; 306 buck5-supply = <&vsys_3v3>; 307 ldo1-supply = <&vsys_3v3>; 308 ldo2-supply = <&vsys_3v3>; 309 ldo3-supply = <&vsys_3v3>; 310 ldo4-supply = <&vsys_3v3>; 311 312 regulators { 313 buckb1: buck1 { 314 regulator-name = "vdd_io_1v8_reg"; 315 regulator-min-microvolt = <1800000>; 316 regulator-max-microvolt = <1800000>; 317 regulator-always-on; 318 regulator-boot-on; 319 }; 320 321 buckb2: buck2 { 322 regulator-name = "vdd_fpd_1v1"; 323 regulator-min-microvolt = <1100000>; 324 regulator-max-microvolt = <1100000>; 325 regulator-boot-on; 326 regulator-always-on; 327 }; 328 329 buckb3: buck3 { 330 regulator-name = "vdd_phy_1v8"; 331 regulator-min-microvolt = <1800000>; 332 regulator-max-microvolt = <1800000>; 333 regulator-boot-on; 334 regulator-always-on; 335 }; 336 337 buckb4: buck4 { 338 regulator-name = "vdd_ddr_1v1"; 339 regulator-min-microvolt = <1100000>; 340 regulator-max-microvolt = <1100000>; 341 regulator-boot-on; 342 regulator-always-on; 343 }; 344 345 buckb5: buck5 { 346 regulator-name = "vdd_ram_0v85"; 347 regulator-min-microvolt = <850000>; 348 regulator-max-microvolt = <850000>; 349 regulator-boot-on; 350 regulator-always-on; 351 }; 352 353 ldob1: ldo1 { 354 regulator-name = "vdd_wk_0v8"; 355 regulator-min-microvolt = <800000>; 356 regulator-max-microvolt = <800000>; 357 regulator-boot-on; 358 regulator-always-on; 359 }; 360 361 ldob2: ldo2 { 362 regulator-name = "vdd_gpioret_3v3"; 363 regulator-min-microvolt = <3300000>; 364 regulator-max-microvolt = <3300000>; 365 regulator-boot-on; 366 regulator-always-on; 367 }; 368 369 ldob3: ldo3 { 370 regulator-name = "vda_dll_0v8"; 371 regulator-min-microvolt = <800000>; 372 regulator-max-microvolt = <800000>; 373 regulator-boot-on; 374 regulator-always-on; 375 }; 376 377 ldob4: ldo4 { 378 regulator-name = "vda_pll_1v8"; 379 regulator-min-microvolt = <1800000>; 380 regulator-max-microvolt = <1800000>; 381 regulator-boot-on; 382 regulator-always-on; 383 }; 384 }; 385 }; 386 387 lp876411: pmic@58 { 388 compatible = "ti,lp8764-q1"; 389 reg = <0x58>; 390 system-power-controller; 391 interrupt-parent = <&wkup_gpio0>; 392 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 393 gpio-controller; 394 #gpio-cells = <2>; 395 buck1234-supply = <&vsys_3v3>; 396 397 regulators { 398 buckc1234: buck1234 { 399 regulator-name = "vdd_core_0v8"; 400 regulator-min-microvolt = <800000>; 401 regulator-max-microvolt = <800000>; 402 regulator-boot-on; 403 regulator-always-on; 404 }; 405 }; 406 }; 407}; 408 409&main_i2c0 { 410 status = "okay"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&main_i2c0_pins_default>; 413 clock-frequency = <400000>; 414 415 exp_som: gpio@21 { 416 compatible = "ti,tca6408"; 417 reg = <0x21>; 418 gpio-controller; 419 #gpio-cells = <2>; 420 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 421 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 422 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", 423 "GPIO_LIN_EN", "CAN_STB"; 424 }; 425}; 426 427&main_mcan16 { 428 status = "okay"; 429 pinctrl-0 = <&main_mcan16_pins_default>; 430 pinctrl-names = "default"; 431 phys = <&transceiver0>; 432}; 433 434&ospi0 { 435 status = "okay"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 438 439 flash@0 { 440 compatible = "jedec,spi-nor"; 441 reg = <0x0>; 442 spi-tx-bus-width = <8>; 443 spi-rx-bus-width = <8>; 444 spi-max-frequency = <25000000>; 445 bootph-all; 446 cdns,tshsl-ns = <60>; 447 cdns,tsd2d-ns = <60>; 448 cdns,tchsh-ns = <60>; 449 cdns,tslch-ns = <60>; 450 cdns,read-delay = <4>; 451 }; 452}; 453 454&mailbox0_cluster0 { 455 status = "okay"; 456 interrupts = <436>; 457 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 458 ti,mbox-rx = <0 0 0>; 459 ti,mbox-tx = <1 0 0>; 460 }; 461 462 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 463 ti,mbox-rx = <2 0 0>; 464 ti,mbox-tx = <3 0 0>; 465 }; 466}; 467 468&mailbox0_cluster1 { 469 status = "okay"; 470 interrupts = <432>; 471 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 472 ti,mbox-rx = <0 0 0>; 473 ti,mbox-tx = <1 0 0>; 474 }; 475 476 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 477 ti,mbox-rx = <2 0 0>; 478 ti,mbox-tx = <3 0 0>; 479 }; 480}; 481 482&mailbox0_cluster2 { 483 status = "okay"; 484 interrupts = <428>; 485 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 486 ti,mbox-rx = <0 0 0>; 487 ti,mbox-tx = <1 0 0>; 488 }; 489 490 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 491 ti,mbox-rx = <2 0 0>; 492 ti,mbox-tx = <3 0 0>; 493 }; 494}; 495 496&mailbox0_cluster4 { 497 status = "okay"; 498 interrupts = <420>; 499 mbox_c71_0: mbox-c71-0 { 500 ti,mbox-rx = <0 0 0>; 501 ti,mbox-tx = <1 0 0>; 502 }; 503 504 mbox_c71_1: mbox-c71-1 { 505 ti,mbox-rx = <2 0 0>; 506 ti,mbox-tx = <3 0 0>; 507 }; 508}; 509 510&mcu_r5fss0_core0 { 511 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 512 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 513 <&mcu_r5fss0_core0_memory_region>; 514}; 515 516&mcu_r5fss0_core1 { 517 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 518 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 519 <&mcu_r5fss0_core1_memory_region>; 520}; 521 522&main_r5fss0 { 523 ti,cluster-mode = <0>; 524}; 525 526&main_r5fss1 { 527 ti,cluster-mode = <0>; 528}; 529 530/* Timers are used by Remoteproc firmware */ 531&main_timer0 { 532 status = "reserved"; 533}; 534 535&main_timer1 { 536 status = "reserved"; 537}; 538 539&main_timer2 { 540 status = "reserved"; 541}; 542 543&main_timer3 { 544 status = "reserved"; 545}; 546 547&main_timer4 { 548 status = "reserved"; 549}; 550 551&main_timer5 { 552 status = "reserved"; 553}; 554 555&main_r5fss0_core0 { 556 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 557 memory-region = <&main_r5fss0_core0_dma_memory_region>, 558 <&main_r5fss0_core0_memory_region>; 559}; 560 561&main_r5fss0_core1 { 562 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 563 memory-region = <&main_r5fss0_core1_dma_memory_region>, 564 <&main_r5fss0_core1_memory_region>; 565}; 566 567&main_r5fss1_core0 { 568 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 569 memory-region = <&main_r5fss1_core0_dma_memory_region>, 570 <&main_r5fss1_core0_memory_region>; 571}; 572 573&main_r5fss1_core1 { 574 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 575 memory-region = <&main_r5fss1_core1_dma_memory_region>, 576 <&main_r5fss1_core1_memory_region>; 577}; 578 579&c71_0 { 580 status = "okay"; 581 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 582 memory-region = <&c71_0_dma_memory_region>, 583 <&c71_0_memory_region>; 584}; 585 586&c71_1 { 587 status = "okay"; 588 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 589 memory-region = <&c71_1_dma_memory_region>, 590 <&c71_1_memory_region>; 591}; 592