xref: /linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi (revision 1f20a5769446a1acae67ac9e63d07a594829a789)
1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * SoM: https://www.ti.com/lit/zip/sprr439
4 *
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8/dts-v1/;
9
10#include "k3-j721s2.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	memory@80000000 {
15		device_type = "memory";
16		/* 16 GB RAM */
17		reg = <0x00 0x80000000 0x00 0x80000000>,
18		      <0x08 0x80000000 0x03 0x80000000>;
19	};
20
21	/* Reserving memory regions still pending */
22	reserved_memory: reserved-memory {
23		#address-cells = <2>;
24		#size-cells = <2>;
25		ranges;
26
27		secure_ddr: optee@9e800000 {
28			reg = <0x00 0x9e800000 0x00 0x01800000>;
29			alignment = <0x1000>;
30			no-map;
31		};
32
33		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
34			compatible = "shared-dma-pool";
35			reg = <0x00 0xa0000000 0x00 0x100000>;
36			no-map;
37		};
38
39		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
40			compatible = "shared-dma-pool";
41			reg = <0x00 0xa0100000 0x00 0xf00000>;
42			no-map;
43		};
44
45		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
46			compatible = "shared-dma-pool";
47			reg = <0x00 0xa1000000 0x00 0x100000>;
48			no-map;
49		};
50
51		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
52			compatible = "shared-dma-pool";
53			reg = <0x00 0xa1100000 0x00 0xf00000>;
54			no-map;
55		};
56
57		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
58			compatible = "shared-dma-pool";
59			reg = <0x00 0xa2000000 0x00 0x100000>;
60			no-map;
61		};
62
63		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
64			compatible = "shared-dma-pool";
65			reg = <0x00 0xa2100000 0x00 0xf00000>;
66			no-map;
67		};
68
69		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
70			compatible = "shared-dma-pool";
71			reg = <0x00 0xa3000000 0x00 0x100000>;
72			no-map;
73		};
74
75		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
76			compatible = "shared-dma-pool";
77			reg = <0x00 0xa3100000 0x00 0xf00000>;
78			no-map;
79		};
80
81		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
82			compatible = "shared-dma-pool";
83			reg = <0x00 0xa4000000 0x00 0x100000>;
84			no-map;
85		};
86
87		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
88			compatible = "shared-dma-pool";
89			reg = <0x00 0xa4100000 0x00 0xf00000>;
90			no-map;
91		};
92
93		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
94			compatible = "shared-dma-pool";
95			reg = <0x00 0xa5000000 0x00 0x100000>;
96			no-map;
97		};
98
99		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
100			compatible = "shared-dma-pool";
101			reg = <0x00 0xa5100000 0x00 0xf00000>;
102			no-map;
103		};
104
105		c71_0_dma_memory_region: c71-dma-memory@a6000000 {
106			compatible = "shared-dma-pool";
107			reg = <0x00 0xa6000000 0x00 0x100000>;
108			no-map;
109		};
110
111		c71_0_memory_region: c71-memory@a6100000 {
112			compatible = "shared-dma-pool";
113			reg = <0x00 0xa6100000 0x00 0xf00000>;
114			no-map;
115		};
116
117		c71_1_dma_memory_region: c71-dma-memory@a7000000 {
118			compatible = "shared-dma-pool";
119			reg = <0x00 0xa7000000 0x00 0x100000>;
120			no-map;
121		};
122
123		c71_1_memory_region: c71-memory@a7100000 {
124			compatible = "shared-dma-pool";
125			reg = <0x00 0xa7100000 0x00 0xf00000>;
126			no-map;
127		};
128
129		rtos_ipc_memory_region: ipc-memories@a8000000 {
130			reg = <0x00 0xa8000000 0x00 0x01c00000>;
131			alignment = <0x1000>;
132			no-map;
133		};
134	};
135
136	mux0: mux-controller {
137		compatible = "gpio-mux";
138		#mux-state-cells = <1>;
139		mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
140	};
141
142	mux1: mux-controller {
143		compatible = "gpio-mux";
144		#mux-state-cells = <1>;
145		mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
146	};
147
148	transceiver0: can-phy0 {
149		/* standby pin has been grounded by default */
150		compatible = "ti,tcan1042";
151		#phy-cells = <0>;
152		max-bitrate = <5000000>;
153	};
154};
155
156&wkup_pmx0 {
157	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
158		pinctrl-single,pins = <
159			J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
160			J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
161			J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
162			J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
163			J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
164			J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
165			J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
166			J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
167			J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
168			J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
169			J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
170			J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
171		>;
172	};
173};
174
175&wkup_pmx1 {
176	pmic_irq_pins_default: pmic-irq-default-pins {
177		pinctrl-single,pins = <
178			/* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
179			J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7)
180		>;
181	};
182};
183
184&wkup_pmx2 {
185	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
186		pinctrl-single,pins = <
187			J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
188			J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
189		>;
190	};
191};
192
193&main_pmx0 {
194	main_i2c0_pins_default: main-i2c0-default-pins {
195		pinctrl-single,pins = <
196			J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
197			J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
198		>;
199	};
200
201	main_mcan16_pins_default: main-mcan16-default-pins {
202		pinctrl-single,pins = <
203			J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
204			J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
205		>;
206	};
207};
208
209&wkup_i2c0 {
210	status = "okay";
211	pinctrl-names = "default";
212	pinctrl-0 = <&wkup_i2c0_pins_default>;
213	clock-frequency = <400000>;
214
215	eeprom@50 {
216		/* CAV24C256WE-GT3 */
217		compatible = "atmel,24c256";
218		reg = <0x50>;
219	};
220
221	tps659411: pmic@48 {
222		compatible = "ti,tps6594-q1";
223		reg = <0x48>;
224		system-power-controller;
225		pinctrl-names = "default";
226		pinctrl-0 = <&pmic_irq_pins_default>;
227		interrupt-parent = <&wkup_gpio0>;
228		interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
229		gpio-controller;
230		#gpio-cells = <2>;
231		ti,primary-pmic;
232		buck1234-supply = <&vsys_3v3>;
233		buck5-supply = <&vsys_3v3>;
234		ldo1-supply = <&vsys_3v3>;
235		ldo2-supply = <&vsys_3v3>;
236		ldo3-supply = <&vsys_3v3>;
237		ldo4-supply = <&vsys_3v3>;
238
239		regulators {
240			bucka1234: buck1234 {
241				regulator-name = "vdd_cpu_avs";
242				regulator-min-microvolt = <600000>;
243				regulator-max-microvolt = <900000>;
244				regulator-boot-on;
245				regulator-always-on;
246				bootph-pre-ram;
247			};
248
249			bucka5: buck5 {
250				regulator-name = "vdd_mcu_0v85";
251				regulator-min-microvolt = <850000>;
252				regulator-max-microvolt = <850000>;
253				regulator-boot-on;
254				regulator-always-on;
255			};
256
257			ldoa1: ldo1 {
258				regulator-name = "vdd_mcuwk_0v8";
259				regulator-min-microvolt = <800000>;
260				regulator-max-microvolt = <800000>;
261				regulator-boot-on;
262				regulator-always-on;
263			};
264
265			ldoa2: ldo2 {
266				regulator-name = "vdd_mcu_gpioret_3v3";
267				regulator-min-microvolt = <3300000>;
268				regulator-max-microvolt = <3300000>;
269				regulator-boot-on;
270				regulator-always-on;
271			};
272
273			ldoa3: ldo3 {
274				regulator-name = "vdd_mcuio_1v8";
275				regulator-min-microvolt = <1800000>;
276				regulator-max-microvolt = <1800000>;
277				regulator-boot-on;
278				regulator-always-on;
279			};
280
281			ldoa4: ldo4 {
282				regulator-name = "vda_mcu_1v8";
283				regulator-min-microvolt = <1800000>;
284				regulator-max-microvolt = <1800000>;
285				regulator-boot-on;
286				regulator-always-on;
287			};
288		};
289	};
290
291	tps659414: pmic@4c {
292		compatible = "ti,tps6594-q1";
293		reg = <0x4c>;
294		system-power-controller;
295		interrupt-parent = <&wkup_gpio0>;
296		interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
297		gpio-controller;
298		#gpio-cells = <2>;
299		buck1-supply = <&vsys_3v3>;
300		buck2-supply = <&vsys_3v3>;
301		buck3-supply = <&vsys_3v3>;
302		buck4-supply = <&vsys_3v3>;
303		buck5-supply = <&vsys_3v3>;
304		ldo1-supply = <&vsys_3v3>;
305		ldo2-supply = <&vsys_3v3>;
306		ldo3-supply = <&vsys_3v3>;
307		ldo4-supply = <&vsys_3v3>;
308
309		regulators {
310			buckb1: buck1 {
311				regulator-name = "vdd_io_1v8_reg";
312				regulator-min-microvolt = <1800000>;
313				regulator-max-microvolt = <1800000>;
314				regulator-always-on;
315				regulator-boot-on;
316			};
317
318			buckb2: buck2 {
319				regulator-name = "vdd_fpd_1v1";
320				regulator-min-microvolt = <1100000>;
321				regulator-max-microvolt = <1100000>;
322				regulator-boot-on;
323				regulator-always-on;
324			};
325
326			buckb3: buck3 {
327				regulator-name = "vdd_phy_1v8";
328				regulator-min-microvolt = <1800000>;
329				regulator-max-microvolt = <1800000>;
330				regulator-boot-on;
331				regulator-always-on;
332			};
333
334			buckb4: buck4 {
335				regulator-name = "vdd_ddr_1v1";
336				regulator-min-microvolt = <1100000>;
337				regulator-max-microvolt = <1100000>;
338				regulator-boot-on;
339				regulator-always-on;
340			};
341
342			buckb5: buck5 {
343				regulator-name = "vdd_ram_0v85";
344				regulator-min-microvolt = <850000>;
345				regulator-max-microvolt = <850000>;
346				regulator-boot-on;
347				regulator-always-on;
348			};
349
350			ldob1: ldo1 {
351				regulator-name = "vdd_wk_0v8";
352				regulator-min-microvolt = <800000>;
353				regulator-max-microvolt = <800000>;
354				regulator-boot-on;
355				regulator-always-on;
356			};
357
358			ldob2: ldo2 {
359				regulator-name = "vdd_gpioret_3v3";
360				regulator-min-microvolt = <3300000>;
361				regulator-max-microvolt = <3300000>;
362				regulator-boot-on;
363				regulator-always-on;
364			};
365
366			ldob3: ldo3 {
367				regulator-name = "vda_dll_0v8";
368				regulator-min-microvolt = <800000>;
369				regulator-max-microvolt = <800000>;
370				regulator-boot-on;
371				regulator-always-on;
372			};
373
374			ldob4: ldo4 {
375				regulator-name = "vda_pll_1v8";
376				regulator-min-microvolt = <1800000>;
377				regulator-max-microvolt = <1800000>;
378				regulator-boot-on;
379				regulator-always-on;
380			};
381		};
382	};
383
384	lp876411: pmic@58 {
385		compatible = "ti,lp8764-q1";
386		reg = <0x58>;
387		system-power-controller;
388		interrupt-parent = <&wkup_gpio0>;
389		interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
390		gpio-controller;
391		#gpio-cells = <2>;
392		buck1234-supply = <&vsys_3v3>;
393
394		regulators {
395			buckc1234: buck1234 {
396				regulator-name = "vdd_core_0v8";
397				regulator-min-microvolt = <800000>;
398				regulator-max-microvolt = <800000>;
399				regulator-boot-on;
400				regulator-always-on;
401			};
402		};
403	};
404};
405
406&main_i2c0 {
407	status = "okay";
408	pinctrl-names = "default";
409	pinctrl-0 = <&main_i2c0_pins_default>;
410	clock-frequency = <400000>;
411
412	exp_som: gpio@21 {
413		compatible = "ti,tca6408";
414		reg = <0x21>;
415		gpio-controller;
416		#gpio-cells = <2>;
417		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
418				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
419				  "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
420				   "GPIO_LIN_EN", "CAN_STB";
421	};
422};
423
424&main_mcan16 {
425	status = "okay";
426	pinctrl-0 = <&main_mcan16_pins_default>;
427	pinctrl-names = "default";
428	phys = <&transceiver0>;
429};
430
431&ospi0 {
432	status = "okay";
433	pinctrl-names = "default";
434	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
435
436	flash@0 {
437		compatible = "jedec,spi-nor";
438		reg = <0x0>;
439		spi-tx-bus-width = <8>;
440		spi-rx-bus-width = <8>;
441		spi-max-frequency = <25000000>;
442		cdns,tshsl-ns = <60>;
443		cdns,tsd2d-ns = <60>;
444		cdns,tchsh-ns = <60>;
445		cdns,tslch-ns = <60>;
446		cdns,read-delay = <4>;
447	};
448};
449
450&mailbox0_cluster0 {
451	status = "okay";
452	interrupts = <436>;
453	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
454		ti,mbox-rx = <0 0 0>;
455		ti,mbox-tx = <1 0 0>;
456	};
457
458	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
459		ti,mbox-rx = <2 0 0>;
460		ti,mbox-tx = <3 0 0>;
461	};
462};
463
464&mailbox0_cluster1 {
465	status = "okay";
466	interrupts = <432>;
467	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
468		ti,mbox-rx = <0 0 0>;
469		ti,mbox-tx = <1 0 0>;
470	};
471
472	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
473		ti,mbox-rx = <2 0 0>;
474		ti,mbox-tx = <3 0 0>;
475	};
476};
477
478&mailbox0_cluster2 {
479	status = "okay";
480	interrupts = <428>;
481	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
482		ti,mbox-rx = <0 0 0>;
483		ti,mbox-tx = <1 0 0>;
484	};
485
486	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
487		ti,mbox-rx = <2 0 0>;
488		ti,mbox-tx = <3 0 0>;
489	};
490};
491
492&mailbox0_cluster4 {
493	status = "okay";
494	interrupts = <420>;
495	mbox_c71_0: mbox-c71-0 {
496		ti,mbox-rx = <0 0 0>;
497		ti,mbox-tx = <1 0 0>;
498	};
499
500	mbox_c71_1: mbox-c71-1 {
501		ti,mbox-rx = <2 0 0>;
502		ti,mbox-tx = <3 0 0>;
503	};
504};
505
506&mcu_r5fss0_core0 {
507	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
508	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
509			<&mcu_r5fss0_core0_memory_region>;
510};
511
512&mcu_r5fss0_core1 {
513	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
514	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
515			<&mcu_r5fss0_core1_memory_region>;
516};
517
518&main_r5fss0_core0 {
519	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
520	memory-region = <&main_r5fss0_core0_dma_memory_region>,
521			<&main_r5fss0_core0_memory_region>;
522};
523
524&main_r5fss0_core1 {
525	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
526	memory-region = <&main_r5fss0_core1_dma_memory_region>,
527			<&main_r5fss0_core1_memory_region>;
528};
529
530&main_r5fss1_core0 {
531	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
532	memory-region = <&main_r5fss1_core0_dma_memory_region>,
533			<&main_r5fss1_core0_memory_region>;
534};
535
536&main_r5fss1_core1 {
537	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
538	memory-region = <&main_r5fss1_core1_dma_memory_region>,
539			<&main_r5fss1_core1_memory_region>;
540};
541
542&c71_0 {
543	status = "okay";
544	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
545	memory-region = <&c71_0_dma_memory_region>,
546			<&c71_0_memory_region>;
547};
548
549&c71_1 {
550	status = "okay";
551	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
552	memory-region = <&c71_1_dma_memory_region>,
553			<&c71_1_memory_region>;
554};
555