1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 wkup_conf: bus@43000000 { 38 compatible = "simple-bus"; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 ranges = <0x0 0x00 0x43000000 0x20000>; 42 43 chipid: chipid@14 { 44 compatible = "ti,am654-chipid"; 45 reg = <0x14 0x4>; 46 }; 47 }; 48 49 secure_proxy_sa3: mailbox@43600000 { 50 compatible = "ti,am654-secure-proxy"; 51 #mbox-cells = <1>; 52 reg-names = "target_data", "rt", "scfg"; 53 reg = <0x00 0x43600000 0x00 0x10000>, 54 <0x00 0x44880000 0x00 0x20000>, 55 <0x00 0x44860000 0x00 0x20000>; 56 /* 57 * Marked Disabled: 58 * Node is incomplete as it is meant for bootloaders and 59 * firmware on non-MPU processors 60 */ 61 status = "disabled"; 62 }; 63 64 mcu_ram: sram@41c00000 { 65 compatible = "mmio-sram"; 66 reg = <0x00 0x41c00000 0x00 0x100000>; 67 ranges = <0x00 0x00 0x41c00000 0x100000>; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 }; 71 72 wkup_pmx0: pinctrl@4301c000 { 73 compatible = "pinctrl-single"; 74 /* Proxy 0 addressing */ 75 reg = <0x00 0x4301c000 0x00 0x034>; 76 #pinctrl-cells = <1>; 77 pinctrl-single,register-width = <32>; 78 pinctrl-single,function-mask = <0xffffffff>; 79 }; 80 81 wkup_pmx1: pinctrl@4301c038 { 82 compatible = "pinctrl-single"; 83 /* Proxy 0 addressing */ 84 reg = <0x00 0x4301c038 0x00 0x02C>; 85 #pinctrl-cells = <1>; 86 pinctrl-single,register-width = <32>; 87 pinctrl-single,function-mask = <0xffffffff>; 88 }; 89 90 wkup_pmx2: pinctrl@4301c068 { 91 compatible = "pinctrl-single"; 92 /* Proxy 0 addressing */ 93 reg = <0x00 0x4301c068 0x00 0x120>; 94 #pinctrl-cells = <1>; 95 pinctrl-single,register-width = <32>; 96 pinctrl-single,function-mask = <0xffffffff>; 97 }; 98 99 wkup_pmx3: pinctrl@4301c190 { 100 compatible = "pinctrl-single"; 101 /* Proxy 0 addressing */ 102 reg = <0x00 0x4301c190 0x00 0x004>; 103 #pinctrl-cells = <1>; 104 pinctrl-single,register-width = <32>; 105 pinctrl-single,function-mask = <0xffffffff>; 106 }; 107 108 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 109 mcu_timerio_input: pinctrl@40f04200 { 110 compatible = "pinctrl-single"; 111 reg = <0x00 0x40f04200 0x00 0x28>; 112 #pinctrl-cells = <1>; 113 pinctrl-single,register-width = <32>; 114 pinctrl-single,function-mask = <0x0000000f>; 115 /* Non-MPU Firmware usage */ 116 status = "reserved"; 117 }; 118 119 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 120 mcu_timerio_output: pinctrl@40f04280 { 121 compatible = "pinctrl-single"; 122 reg = <0x00 0x40f04280 0x00 0x28>; 123 #pinctrl-cells = <1>; 124 pinctrl-single,register-width = <32>; 125 pinctrl-single,function-mask = <0x0000000f>; 126 /* Non-MPU Firmware usage */ 127 status = "reserved"; 128 }; 129 130 wkup_gpio_intr: interrupt-controller@42200000 { 131 compatible = "ti,sci-intr"; 132 reg = <0x00 0x42200000 0x00 0x400>; 133 ti,intr-trigger-type = <1>; 134 interrupt-controller; 135 interrupt-parent = <&gic500>; 136 #interrupt-cells = <1>; 137 ti,sci = <&sms>; 138 ti,sci-dev-id = <125>; 139 ti,interrupt-ranges = <16 960 16>; 140 }; 141 142 mcu_conf: syscon@40f00000 { 143 compatible = "syscon", "simple-mfd"; 144 reg = <0x0 0x40f00000 0x0 0x20000>; 145 #address-cells = <1>; 146 #size-cells = <1>; 147 ranges = <0x0 0x0 0x40f00000 0x20000>; 148 149 phy_gmii_sel: phy@4040 { 150 compatible = "ti,am654-phy-gmii-sel"; 151 reg = <0x4040 0x4>; 152 #phy-cells = <1>; 153 }; 154 155 }; 156 157 mcu_timer0: timer@40400000 { 158 compatible = "ti,am654-timer"; 159 reg = <0x00 0x40400000 0x00 0x400>; 160 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&k3_clks 35 1>; 162 clock-names = "fck"; 163 assigned-clocks = <&k3_clks 35 1>; 164 assigned-clock-parents = <&k3_clks 35 2>; 165 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 166 ti,timer-pwm; 167 /* Non-MPU Firmware usage */ 168 status = "reserved"; 169 }; 170 171 mcu_timer1: timer@40410000 { 172 compatible = "ti,am654-timer"; 173 reg = <0x00 0x40410000 0x00 0x400>; 174 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&k3_clks 83 1>; 176 clock-names = "fck"; 177 assigned-clocks = <&k3_clks 83 1>; 178 assigned-clock-parents = <&k3_clks 83 2>; 179 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 180 ti,timer-pwm; 181 /* Non-MPU Firmware usage */ 182 status = "reserved"; 183 }; 184 185 mcu_timer2: timer@40420000 { 186 compatible = "ti,am654-timer"; 187 reg = <0x00 0x40420000 0x00 0x400>; 188 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&k3_clks 84 1>; 190 clock-names = "fck"; 191 assigned-clocks = <&k3_clks 84 1>; 192 assigned-clock-parents = <&k3_clks 84 2>; 193 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 194 ti,timer-pwm; 195 /* Non-MPU Firmware usage */ 196 status = "reserved"; 197 }; 198 199 mcu_timer3: timer@40430000 { 200 compatible = "ti,am654-timer"; 201 reg = <0x00 0x40430000 0x00 0x400>; 202 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&k3_clks 85 1>; 204 clock-names = "fck"; 205 assigned-clocks = <&k3_clks 85 1>; 206 assigned-clock-parents = <&k3_clks 85 2>; 207 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 208 ti,timer-pwm; 209 /* Non-MPU Firmware usage */ 210 status = "reserved"; 211 }; 212 213 mcu_timer4: timer@40440000 { 214 compatible = "ti,am654-timer"; 215 reg = <0x00 0x40440000 0x00 0x400>; 216 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&k3_clks 86 1>; 218 clock-names = "fck"; 219 assigned-clocks = <&k3_clks 86 1>; 220 assigned-clock-parents = <&k3_clks 86 2>; 221 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 222 ti,timer-pwm; 223 /* Non-MPU Firmware usage */ 224 status = "reserved"; 225 }; 226 227 mcu_timer5: timer@40450000 { 228 compatible = "ti,am654-timer"; 229 reg = <0x00 0x40450000 0x00 0x400>; 230 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&k3_clks 87 1>; 232 clock-names = "fck"; 233 assigned-clocks = <&k3_clks 87 1>; 234 assigned-clock-parents = <&k3_clks 87 2>; 235 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 236 ti,timer-pwm; 237 /* Non-MPU Firmware usage */ 238 status = "reserved"; 239 }; 240 241 mcu_timer6: timer@40460000 { 242 compatible = "ti,am654-timer"; 243 reg = <0x00 0x40460000 0x00 0x400>; 244 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&k3_clks 88 1>; 246 clock-names = "fck"; 247 assigned-clocks = <&k3_clks 88 1>; 248 assigned-clock-parents = <&k3_clks 88 2>; 249 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 250 ti,timer-pwm; 251 /* Non-MPU Firmware usage */ 252 status = "reserved"; 253 }; 254 255 mcu_timer7: timer@40470000 { 256 compatible = "ti,am654-timer"; 257 reg = <0x00 0x40470000 0x00 0x400>; 258 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&k3_clks 89 1>; 260 clock-names = "fck"; 261 assigned-clocks = <&k3_clks 89 1>; 262 assigned-clock-parents = <&k3_clks 89 2>; 263 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 264 ti,timer-pwm; 265 /* Non-MPU Firmware usage */ 266 status = "reserved"; 267 }; 268 269 mcu_timer8: timer@40480000 { 270 compatible = "ti,am654-timer"; 271 reg = <0x00 0x40480000 0x00 0x400>; 272 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&k3_clks 90 1>; 274 clock-names = "fck"; 275 assigned-clocks = <&k3_clks 90 1>; 276 assigned-clock-parents = <&k3_clks 90 2>; 277 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 278 ti,timer-pwm; 279 /* Non-MPU Firmware usage */ 280 status = "reserved"; 281 }; 282 283 mcu_timer9: timer@40490000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x40490000 0x00 0x400>; 286 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 91 1>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 91 1>; 290 assigned-clock-parents = <&k3_clks 91 2>; 291 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 /* Non-MPU Firmware usage */ 294 status = "reserved"; 295 }; 296 297 wkup_uart0: serial@42300000 { 298 compatible = "ti,j721e-uart", "ti,am654-uart"; 299 reg = <0x00 0x42300000 0x00 0x200>; 300 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&k3_clks 359 3>; 302 clock-names = "fclk"; 303 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 304 status = "disabled"; 305 }; 306 307 mcu_uart0: serial@40a00000 { 308 compatible = "ti,j721e-uart", "ti,am654-uart"; 309 reg = <0x00 0x40a00000 0x00 0x200>; 310 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 149 3>; 312 clock-names = "fclk"; 313 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 314 status = "disabled"; 315 }; 316 317 wkup_gpio0: gpio@42110000 { 318 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 319 reg = <0x00 0x42110000 0x00 0x100>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-parent = <&wkup_gpio_intr>; 323 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 ti,ngpio = <89>; 327 ti,davinci-gpio-unbanked = <0>; 328 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 329 clocks = <&k3_clks 115 0>; 330 clock-names = "gpio"; 331 status = "disabled"; 332 }; 333 334 wkup_gpio1: gpio@42100000 { 335 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 336 reg = <0x00 0x42100000 0x00 0x100>; 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-parent = <&wkup_gpio_intr>; 340 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 ti,ngpio = <89>; 344 ti,davinci-gpio-unbanked = <0>; 345 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 346 clocks = <&k3_clks 116 0>; 347 clock-names = "gpio"; 348 status = "disabled"; 349 }; 350 351 wkup_i2c0: i2c@42120000 { 352 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 353 reg = <0x00 0x42120000 0x00 0x100>; 354 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 clocks = <&k3_clks 223 1>; 358 clock-names = "fck"; 359 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 360 status = "disabled"; 361 }; 362 363 mcu_i2c0: i2c@40b00000 { 364 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 365 reg = <0x00 0x40b00000 0x00 0x100>; 366 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 clocks = <&k3_clks 221 1>; 370 clock-names = "fck"; 371 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 372 status = "disabled"; 373 }; 374 375 mcu_i2c1: i2c@40b10000 { 376 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 377 reg = <0x00 0x40b10000 0x00 0x100>; 378 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 clocks = <&k3_clks 222 1>; 382 clock-names = "fck"; 383 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 384 status = "disabled"; 385 }; 386 387 mcu_mcan0: can@40528000 { 388 compatible = "bosch,m_can"; 389 reg = <0x00 0x40528000 0x00 0x200>, 390 <0x00 0x40500000 0x00 0x8000>; 391 reg-names = "m_can", "message_ram"; 392 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; 393 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; 394 clock-names = "hclk", "cclk"; 395 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 397 interrupt-names = "int0", "int1"; 398 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 399 status = "disabled"; 400 }; 401 402 mcu_mcan1: can@40568000 { 403 compatible = "bosch,m_can"; 404 reg = <0x00 0x40568000 0x00 0x200>, 405 <0x00 0x40540000 0x00 0x8000>; 406 reg-names = "m_can", "message_ram"; 407 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; 408 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; 409 clock-names = "hclk", "cclk"; 410 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 412 interrupt-names = "int0", "int1"; 413 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 414 status = "disabled"; 415 }; 416 417 mcu_spi0: spi@40300000 { 418 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 419 reg = <0x00 0x040300000 0x00 0x400>; 420 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; 424 clocks = <&k3_clks 347 0>; 425 status = "disabled"; 426 }; 427 428 mcu_spi1: spi@40310000 { 429 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 430 reg = <0x00 0x040310000 0x00 0x400>; 431 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 435 clocks = <&k3_clks 348 0>; 436 status = "disabled"; 437 }; 438 439 mcu_spi2: spi@40320000 { 440 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 441 reg = <0x00 0x040320000 0x00 0x400>; 442 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 349 0>; 447 status = "disabled"; 448 }; 449 450 mcu_navss: bus@28380000 { 451 compatible = "simple-bus"; 452 #address-cells = <2>; 453 #size-cells = <2>; 454 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 455 dma-coherent; 456 dma-ranges; 457 458 ti,sci-dev-id = <267>; 459 460 mcu_ringacc: ringacc@2b800000 { 461 compatible = "ti,am654-navss-ringacc"; 462 reg = <0x0 0x2b800000 0x0 0x400000>, 463 <0x0 0x2b000000 0x0 0x400000>, 464 <0x0 0x28590000 0x0 0x100>, 465 <0x0 0x2a500000 0x0 0x40000>, 466 <0x0 0x28440000 0x0 0x40000>; 467 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 468 ti,num-rings = <286>; 469 ti,sci-rm-range-gp-rings = <0x1>; 470 ti,sci = <&sms>; 471 ti,sci-dev-id = <272>; 472 msi-parent = <&main_udmass_inta>; 473 }; 474 475 mcu_udmap: dma-controller@285c0000 { 476 compatible = "ti,j721e-navss-mcu-udmap"; 477 reg = <0x0 0x285c0000 0x0 0x100>, 478 <0x0 0x2a800000 0x0 0x40000>, 479 <0x0 0x2aa00000 0x0 0x40000>, 480 <0x0 0x284a0000 0x0 0x4000>, 481 <0x0 0x284c0000 0x0 0x4000>, 482 <0x0 0x28400000 0x0 0x2000>; 483 reg-names = "gcfg", "rchanrt", "tchanrt", 484 "tchan", "rchan", "rflow"; 485 msi-parent = <&main_udmass_inta>; 486 #dma-cells = <1>; 487 488 ti,sci = <&sms>; 489 ti,sci-dev-id = <273>; 490 ti,ringacc = <&mcu_ringacc>; 491 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 492 <0x0f>; /* TX_HCHAN */ 493 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 494 <0x0b>; /* RX_HCHAN */ 495 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 496 }; 497 }; 498 499 secure_proxy_mcu: mailbox@2a480000 { 500 compatible = "ti,am654-secure-proxy"; 501 #mbox-cells = <1>; 502 reg-names = "target_data", "rt", "scfg"; 503 reg = <0x00 0x2a480000 0x00 0x80000>, 504 <0x00 0x2a380000 0x00 0x80000>, 505 <0x00 0x2a400000 0x00 0x80000>; 506 /* 507 * Marked Disabled: 508 * Node is incomplete as it is meant for bootloaders and 509 * firmware on non-MPU processors 510 */ 511 status = "disabled"; 512 }; 513 514 mcu_cpsw: ethernet@46000000 { 515 compatible = "ti,j721e-cpsw-nuss"; 516 #address-cells = <2>; 517 #size-cells = <2>; 518 reg = <0x0 0x46000000 0x0 0x200000>; 519 reg-names = "cpsw_nuss"; 520 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 521 dma-coherent; 522 clocks = <&k3_clks 29 28>; 523 clock-names = "fck"; 524 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 525 526 dmas = <&mcu_udmap 0xf000>, 527 <&mcu_udmap 0xf001>, 528 <&mcu_udmap 0xf002>, 529 <&mcu_udmap 0xf003>, 530 <&mcu_udmap 0xf004>, 531 <&mcu_udmap 0xf005>, 532 <&mcu_udmap 0xf006>, 533 <&mcu_udmap 0xf007>, 534 <&mcu_udmap 0x7000>; 535 dma-names = "tx0", "tx1", "tx2", "tx3", 536 "tx4", "tx5", "tx6", "tx7", 537 "rx"; 538 539 ethernet-ports { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 543 cpsw_port1: port@1 { 544 reg = <1>; 545 ti,mac-only; 546 label = "port1"; 547 ti,syscon-efuse = <&mcu_conf 0x200>; 548 phys = <&phy_gmii_sel 1>; 549 }; 550 }; 551 552 davinci_mdio: mdio@f00 { 553 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 554 reg = <0x0 0xf00 0x0 0x100>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clocks = <&k3_clks 29 28>; 558 clock-names = "fck"; 559 bus_freq = <1000000>; 560 }; 561 562 cpts@3d000 { 563 compatible = "ti,am65-cpts"; 564 reg = <0x0 0x3d000 0x0 0x400>; 565 clocks = <&k3_clks 29 3>; 566 clock-names = "cpts"; 567 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ 568 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ 569 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 570 interrupt-names = "cpts"; 571 ti,cpts-ext-ts-inputs = <4>; 572 ti,cpts-periodic-outputs = <2>; 573 }; 574 }; 575 576 tscadc0: tscadc@40200000 { 577 compatible = "ti,am3359-tscadc"; 578 reg = <0x00 0x40200000 0x00 0x1000>; 579 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 580 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 581 clocks = <&k3_clks 0 0>; 582 assigned-clocks = <&k3_clks 0 2>; 583 assigned-clock-rates = <60000000>; 584 clock-names = "fck"; 585 dmas = <&main_udmap 0x7400>, 586 <&main_udmap 0x7401>; 587 dma-names = "fifo0", "fifo1"; 588 status = "disabled"; 589 590 adc { 591 #io-channel-cells = <1>; 592 compatible = "ti,am3359-adc"; 593 }; 594 }; 595 596 tscadc1: tscadc@40210000 { 597 compatible = "ti,am3359-tscadc"; 598 reg = <0x00 0x40210000 0x00 0x1000>; 599 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 600 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 601 clocks = <&k3_clks 1 0>; 602 assigned-clocks = <&k3_clks 1 2>; 603 assigned-clock-rates = <60000000>; 604 clock-names = "fck"; 605 dmas = <&main_udmap 0x7402>, 606 <&main_udmap 0x7403>; 607 dma-names = "fifo0", "fifo1"; 608 status = "disabled"; 609 610 adc { 611 #io-channel-cells = <1>; 612 compatible = "ti,am3359-adc"; 613 }; 614 }; 615 616 fss: bus@47000000 { 617 compatible = "simple-bus"; 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 621 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 622 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 623 624 ospi0: spi@47040000 { 625 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 626 reg = <0x00 0x47040000 0x00 0x100>, 627 <0x05 0x00000000 0x01 0x00000000>; 628 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 629 cdns,fifo-depth = <256>; 630 cdns,fifo-width = <4>; 631 cdns,trigger-address = <0x0>; 632 clocks = <&k3_clks 109 5>; 633 assigned-clocks = <&k3_clks 109 5>; 634 assigned-clock-parents = <&k3_clks 109 7>; 635 assigned-clock-rates = <166666666>; 636 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 640 status = "disabled"; /* Needs pinmux */ 641 }; 642 643 ospi1: spi@47050000 { 644 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 645 reg = <0x00 0x47050000 0x00 0x100>, 646 <0x07 0x00000000 0x01 0x00000000>; 647 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 648 cdns,fifo-depth = <256>; 649 cdns,fifo-width = <4>; 650 cdns,trigger-address = <0x0>; 651 clocks = <&k3_clks 110 5>; 652 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 656 status = "disabled"; /* Needs pinmux */ 657 }; 658 }; 659 660 wkup_vtm0: temperature-sensor@42040000 { 661 compatible = "ti,j7200-vtm"; 662 reg = <0x00 0x42040000 0x0 0x350>, 663 <0x00 0x42050000 0x0 0x350>; 664 power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; 665 #thermal-sensor-cells = <1>; 666 }; 667 668 mcu_r5fss0: r5fss@41000000 { 669 compatible = "ti,j721s2-r5fss"; 670 ti,cluster-mode = <1>; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 ranges = <0x41000000 0x00 0x41000000 0x20000>, 674 <0x41400000 0x00 0x41400000 0x20000>; 675 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 676 677 mcu_r5fss0_core0: r5f@41000000 { 678 compatible = "ti,j721s2-r5f"; 679 reg = <0x41000000 0x00010000>, 680 <0x41010000 0x00010000>; 681 reg-names = "atcm", "btcm"; 682 ti,sci = <&sms>; 683 ti,sci-dev-id = <284>; 684 ti,sci-proc-ids = <0x01 0xff>; 685 resets = <&k3_reset 284 1>; 686 firmware-name = "j721s2-mcu-r5f0_0-fw"; 687 ti,atcm-enable = <1>; 688 ti,btcm-enable = <1>; 689 ti,loczrama = <1>; 690 }; 691 692 mcu_r5fss0_core1: r5f@41400000 { 693 compatible = "ti,j721s2-r5f"; 694 reg = <0x41400000 0x00010000>, 695 <0x41410000 0x00010000>; 696 reg-names = "atcm", "btcm"; 697 ti,sci = <&sms>; 698 ti,sci-dev-id = <285>; 699 ti,sci-proc-ids = <0x02 0xff>; 700 resets = <&k3_reset 285 1>; 701 firmware-name = "j721s2-mcu-r5f0_1-fw"; 702 ti,atcm-enable = <1>; 703 ti,btcm-enable = <1>; 704 ti,loczrama = <1>; 705 }; 706 }; 707 708 mcu_esm: esm@40800000 { 709 compatible = "ti,j721e-esm"; 710 reg = <0x00 0x40800000 0x00 0x1000>; 711 ti,esm-pins = <95>; 712 bootph-pre-ram; 713 }; 714 715 wkup_esm: esm@42080000 { 716 compatible = "ti,j721e-esm"; 717 reg = <0x00 0x42080000 0x00 0x1000>; 718 ti,esm-pins = <63>; 719 bootph-pre-ram; 720 }; 721 722 /* 723 * The 2 RTI instances are couple with MCU R5Fs so keeping them 724 * reserved as these will be used by their respective firmware 725 */ 726 mcu_watchdog0: watchdog@40600000 { 727 compatible = "ti,j7-rti-wdt"; 728 reg = <0x00 0x40600000 0x00 0x100>; 729 clocks = <&k3_clks 295 1>; 730 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 731 assigned-clocks = <&k3_clks 295 1>; 732 assigned-clock-parents = <&k3_clks 295 5>; 733 /* reserved for MCU_R5F0_0 */ 734 status = "reserved"; 735 }; 736 737 mcu_watchdog1: watchdog@40610000 { 738 compatible = "ti,j7-rti-wdt"; 739 reg = <0x00 0x40610000 0x00 0x100>; 740 clocks = <&k3_clks 296 1>; 741 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; 742 assigned-clocks = <&k3_clks 296 1>; 743 assigned-clock-parents = <&k3_clks 296 5>; 744 /* reserved for MCU_R5F0_1 */ 745 status = "reserved"; 746 }; 747}; 748