1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 wkup_conf: bus@43000000 { 38 compatible = "simple-bus"; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 ranges = <0x0 0x00 0x43000000 0x20000>; 42 43 chipid: chipid@14 { 44 compatible = "ti,am654-chipid"; 45 reg = <0x14 0x4>; 46 }; 47 }; 48 49 secure_proxy_sa3: mailbox@43600000 { 50 compatible = "ti,am654-secure-proxy"; 51 #mbox-cells = <1>; 52 reg-names = "target_data", "rt", "scfg"; 53 reg = <0x00 0x43600000 0x00 0x10000>, 54 <0x00 0x44880000 0x00 0x20000>, 55 <0x00 0x44860000 0x00 0x20000>; 56 /* 57 * Marked Disabled: 58 * Node is incomplete as it is meant for bootloaders and 59 * firmware on non-MPU processors 60 */ 61 status = "disabled"; 62 }; 63 64 mcu_ram: sram@41c00000 { 65 compatible = "mmio-sram"; 66 reg = <0x00 0x41c00000 0x00 0x100000>; 67 ranges = <0x00 0x00 0x41c00000 0x100000>; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 }; 71 72 wkup_pmx0: pinctrl@4301c000 { 73 compatible = "pinctrl-single"; 74 /* Proxy 0 addressing */ 75 reg = <0x00 0x4301c000 0x00 0x034>; 76 #pinctrl-cells = <1>; 77 pinctrl-single,register-width = <32>; 78 pinctrl-single,function-mask = <0xffffffff>; 79 }; 80 81 wkup_pmx1: pinctrl@4301c038 { 82 compatible = "pinctrl-single"; 83 /* Proxy 0 addressing */ 84 reg = <0x00 0x4301c038 0x00 0x02C>; 85 #pinctrl-cells = <1>; 86 pinctrl-single,register-width = <32>; 87 pinctrl-single,function-mask = <0xffffffff>; 88 }; 89 90 wkup_pmx2: pinctrl@4301c068 { 91 compatible = "pinctrl-single"; 92 /* Proxy 0 addressing */ 93 reg = <0x00 0x4301c068 0x00 0x120>; 94 #pinctrl-cells = <1>; 95 pinctrl-single,register-width = <32>; 96 pinctrl-single,function-mask = <0xffffffff>; 97 }; 98 99 wkup_pmx3: pinctrl@4301c190 { 100 compatible = "pinctrl-single"; 101 /* Proxy 0 addressing */ 102 reg = <0x00 0x4301c190 0x00 0x004>; 103 #pinctrl-cells = <1>; 104 pinctrl-single,register-width = <32>; 105 pinctrl-single,function-mask = <0xffffffff>; 106 }; 107 108 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 109 mcu_timerio_input: pinctrl@40f04200 { 110 compatible = "pinctrl-single"; 111 reg = <0x00 0x40f04200 0x00 0x28>; 112 #pinctrl-cells = <1>; 113 pinctrl-single,register-width = <32>; 114 pinctrl-single,function-mask = <0x0000000f>; 115 /* Non-MPU Firmware usage */ 116 status = "reserved"; 117 }; 118 119 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 120 mcu_timerio_output: pinctrl@40f04280 { 121 compatible = "pinctrl-single"; 122 reg = <0x00 0x40f04280 0x00 0x28>; 123 #pinctrl-cells = <1>; 124 pinctrl-single,register-width = <32>; 125 pinctrl-single,function-mask = <0x0000000f>; 126 /* Non-MPU Firmware usage */ 127 status = "reserved"; 128 }; 129 130 wkup_gpio_intr: interrupt-controller@42200000 { 131 compatible = "ti,sci-intr"; 132 reg = <0x00 0x42200000 0x00 0x400>; 133 ti,intr-trigger-type = <1>; 134 interrupt-controller; 135 interrupt-parent = <&gic500>; 136 #interrupt-cells = <1>; 137 ti,sci = <&sms>; 138 ti,sci-dev-id = <125>; 139 ti,interrupt-ranges = <16 960 16>; 140 }; 141 142 mcu_conf: bus@40f00000 { 143 compatible = "simple-bus"; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0x0 0x0 0x40f00000 0x20000>; 147 148 cpsw_mac_syscon: ethernet-mac-syscon@200 { 149 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 150 reg = <0x200 0x8>; 151 }; 152 153 phy_gmii_sel: phy@4040 { 154 compatible = "ti,am654-phy-gmii-sel"; 155 reg = <0x4040 0x4>; 156 #phy-cells = <1>; 157 }; 158 159 }; 160 161 mcu_timer0: timer@40400000 { 162 compatible = "ti,am654-timer"; 163 reg = <0x00 0x40400000 0x00 0x400>; 164 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&k3_clks 35 1>; 166 clock-names = "fck"; 167 assigned-clocks = <&k3_clks 35 1>; 168 assigned-clock-parents = <&k3_clks 35 2>; 169 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 170 ti,timer-pwm; 171 /* Non-MPU Firmware usage */ 172 status = "reserved"; 173 }; 174 175 mcu_timer1: timer@40410000 { 176 compatible = "ti,am654-timer"; 177 reg = <0x00 0x40410000 0x00 0x400>; 178 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&k3_clks 83 1>; 180 clock-names = "fck"; 181 assigned-clocks = <&k3_clks 83 1>; 182 assigned-clock-parents = <&k3_clks 83 2>; 183 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 184 ti,timer-pwm; 185 /* Non-MPU Firmware usage */ 186 status = "reserved"; 187 }; 188 189 mcu_timer2: timer@40420000 { 190 compatible = "ti,am654-timer"; 191 reg = <0x00 0x40420000 0x00 0x400>; 192 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&k3_clks 84 1>; 194 clock-names = "fck"; 195 assigned-clocks = <&k3_clks 84 1>; 196 assigned-clock-parents = <&k3_clks 84 2>; 197 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 198 ti,timer-pwm; 199 /* Non-MPU Firmware usage */ 200 status = "reserved"; 201 }; 202 203 mcu_timer3: timer@40430000 { 204 compatible = "ti,am654-timer"; 205 reg = <0x00 0x40430000 0x00 0x400>; 206 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&k3_clks 85 1>; 208 clock-names = "fck"; 209 assigned-clocks = <&k3_clks 85 1>; 210 assigned-clock-parents = <&k3_clks 85 2>; 211 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 212 ti,timer-pwm; 213 /* Non-MPU Firmware usage */ 214 status = "reserved"; 215 }; 216 217 mcu_timer4: timer@40440000 { 218 compatible = "ti,am654-timer"; 219 reg = <0x00 0x40440000 0x00 0x400>; 220 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&k3_clks 86 1>; 222 clock-names = "fck"; 223 assigned-clocks = <&k3_clks 86 1>; 224 assigned-clock-parents = <&k3_clks 86 2>; 225 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 226 ti,timer-pwm; 227 /* Non-MPU Firmware usage */ 228 status = "reserved"; 229 }; 230 231 mcu_timer5: timer@40450000 { 232 compatible = "ti,am654-timer"; 233 reg = <0x00 0x40450000 0x00 0x400>; 234 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&k3_clks 87 1>; 236 clock-names = "fck"; 237 assigned-clocks = <&k3_clks 87 1>; 238 assigned-clock-parents = <&k3_clks 87 2>; 239 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 240 ti,timer-pwm; 241 /* Non-MPU Firmware usage */ 242 status = "reserved"; 243 }; 244 245 mcu_timer6: timer@40460000 { 246 compatible = "ti,am654-timer"; 247 reg = <0x00 0x40460000 0x00 0x400>; 248 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&k3_clks 88 1>; 250 clock-names = "fck"; 251 assigned-clocks = <&k3_clks 88 1>; 252 assigned-clock-parents = <&k3_clks 88 2>; 253 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 254 ti,timer-pwm; 255 /* Non-MPU Firmware usage */ 256 status = "reserved"; 257 }; 258 259 mcu_timer7: timer@40470000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x40470000 0x00 0x400>; 262 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 89 1>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 89 1>; 266 assigned-clock-parents = <&k3_clks 89 2>; 267 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 /* Non-MPU Firmware usage */ 270 status = "reserved"; 271 }; 272 273 mcu_timer8: timer@40480000 { 274 compatible = "ti,am654-timer"; 275 reg = <0x00 0x40480000 0x00 0x400>; 276 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&k3_clks 90 1>; 278 clock-names = "fck"; 279 assigned-clocks = <&k3_clks 90 1>; 280 assigned-clock-parents = <&k3_clks 90 2>; 281 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 282 ti,timer-pwm; 283 /* Non-MPU Firmware usage */ 284 status = "reserved"; 285 }; 286 287 mcu_timer9: timer@40490000 { 288 compatible = "ti,am654-timer"; 289 reg = <0x00 0x40490000 0x00 0x400>; 290 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&k3_clks 91 1>; 292 clock-names = "fck"; 293 assigned-clocks = <&k3_clks 91 1>; 294 assigned-clock-parents = <&k3_clks 91 2>; 295 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 296 ti,timer-pwm; 297 /* Non-MPU Firmware usage */ 298 status = "reserved"; 299 }; 300 301 wkup_uart0: serial@42300000 { 302 compatible = "ti,j721e-uart", "ti,am654-uart"; 303 reg = <0x00 0x42300000 0x00 0x200>; 304 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&k3_clks 359 3>; 306 clock-names = "fclk"; 307 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 308 status = "disabled"; 309 }; 310 311 mcu_uart0: serial@40a00000 { 312 compatible = "ti,j721e-uart", "ti,am654-uart"; 313 reg = <0x00 0x40a00000 0x00 0x200>; 314 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&k3_clks 149 3>; 316 clock-names = "fclk"; 317 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 318 status = "disabled"; 319 }; 320 321 wkup_gpio0: gpio@42110000 { 322 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 323 reg = <0x00 0x42110000 0x00 0x100>; 324 gpio-controller; 325 #gpio-cells = <2>; 326 interrupt-parent = <&wkup_gpio_intr>; 327 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 ti,ngpio = <89>; 331 ti,davinci-gpio-unbanked = <0>; 332 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 333 clocks = <&k3_clks 115 0>; 334 clock-names = "gpio"; 335 status = "disabled"; 336 }; 337 338 wkup_gpio1: gpio@42100000 { 339 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 340 reg = <0x00 0x42100000 0x00 0x100>; 341 gpio-controller; 342 #gpio-cells = <2>; 343 interrupt-parent = <&wkup_gpio_intr>; 344 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 ti,ngpio = <89>; 348 ti,davinci-gpio-unbanked = <0>; 349 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 350 clocks = <&k3_clks 116 0>; 351 clock-names = "gpio"; 352 status = "disabled"; 353 }; 354 355 wkup_i2c0: i2c@42120000 { 356 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 357 reg = <0x00 0x42120000 0x00 0x100>; 358 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&k3_clks 223 1>; 362 clock-names = "fck"; 363 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 364 status = "disabled"; 365 }; 366 367 mcu_i2c0: i2c@40b00000 { 368 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 369 reg = <0x00 0x40b00000 0x00 0x100>; 370 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 clocks = <&k3_clks 221 1>; 374 clock-names = "fck"; 375 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 376 status = "disabled"; 377 }; 378 379 mcu_i2c1: i2c@40b10000 { 380 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 381 reg = <0x00 0x40b10000 0x00 0x100>; 382 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&k3_clks 222 1>; 386 clock-names = "fck"; 387 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 388 status = "disabled"; 389 }; 390 391 mcu_mcan0: can@40528000 { 392 compatible = "bosch,m_can"; 393 reg = <0x00 0x40528000 0x00 0x200>, 394 <0x00 0x40500000 0x00 0x8000>; 395 reg-names = "m_can", "message_ram"; 396 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; 397 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; 398 clock-names = "hclk", "cclk"; 399 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 401 interrupt-names = "int0", "int1"; 402 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 403 status = "disabled"; 404 }; 405 406 mcu_mcan1: can@40568000 { 407 compatible = "bosch,m_can"; 408 reg = <0x00 0x40568000 0x00 0x200>, 409 <0x00 0x40540000 0x00 0x8000>; 410 reg-names = "m_can", "message_ram"; 411 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; 412 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; 413 clock-names = "hclk", "cclk"; 414 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "int0", "int1"; 417 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 418 status = "disabled"; 419 }; 420 421 mcu_spi0: spi@40300000 { 422 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 423 reg = <0x00 0x040300000 0x00 0x400>; 424 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; 428 clocks = <&k3_clks 347 0>; 429 status = "disabled"; 430 }; 431 432 mcu_spi1: spi@40310000 { 433 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 434 reg = <0x00 0x040310000 0x00 0x400>; 435 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 439 clocks = <&k3_clks 348 0>; 440 status = "disabled"; 441 }; 442 443 mcu_spi2: spi@40320000 { 444 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 445 reg = <0x00 0x040320000 0x00 0x400>; 446 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 450 clocks = <&k3_clks 349 0>; 451 status = "disabled"; 452 }; 453 454 mcu_navss: bus@28380000 { 455 compatible = "simple-bus"; 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 459 dma-coherent; 460 dma-ranges; 461 462 ti,sci-dev-id = <267>; 463 464 mcu_ringacc: ringacc@2b800000 { 465 compatible = "ti,am654-navss-ringacc"; 466 reg = <0x0 0x2b800000 0x0 0x400000>, 467 <0x0 0x2b000000 0x0 0x400000>, 468 <0x0 0x28590000 0x0 0x100>, 469 <0x0 0x2a500000 0x0 0x40000>, 470 <0x0 0x28440000 0x0 0x40000>; 471 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 472 ti,num-rings = <286>; 473 ti,sci-rm-range-gp-rings = <0x1>; 474 ti,sci = <&sms>; 475 ti,sci-dev-id = <272>; 476 msi-parent = <&main_udmass_inta>; 477 }; 478 479 mcu_udmap: dma-controller@285c0000 { 480 compatible = "ti,j721e-navss-mcu-udmap"; 481 reg = <0x0 0x285c0000 0x0 0x100>, 482 <0x0 0x2a800000 0x0 0x40000>, 483 <0x0 0x2aa00000 0x0 0x40000>, 484 <0x0 0x284a0000 0x0 0x4000>, 485 <0x0 0x284c0000 0x0 0x4000>, 486 <0x0 0x28400000 0x0 0x2000>; 487 reg-names = "gcfg", "rchanrt", "tchanrt", 488 "tchan", "rchan", "rflow"; 489 msi-parent = <&main_udmass_inta>; 490 #dma-cells = <1>; 491 492 ti,sci = <&sms>; 493 ti,sci-dev-id = <273>; 494 ti,ringacc = <&mcu_ringacc>; 495 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 496 <0x0f>; /* TX_HCHAN */ 497 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 498 <0x0b>; /* RX_HCHAN */ 499 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 500 }; 501 }; 502 503 secure_proxy_mcu: mailbox@2a480000 { 504 compatible = "ti,am654-secure-proxy"; 505 #mbox-cells = <1>; 506 reg-names = "target_data", "rt", "scfg"; 507 reg = <0x00 0x2a480000 0x00 0x80000>, 508 <0x00 0x2a380000 0x00 0x80000>, 509 <0x00 0x2a400000 0x00 0x80000>; 510 /* 511 * Marked Disabled: 512 * Node is incomplete as it is meant for bootloaders and 513 * firmware on non-MPU processors 514 */ 515 status = "disabled"; 516 }; 517 518 mcu_cpsw: ethernet@46000000 { 519 compatible = "ti,j721e-cpsw-nuss"; 520 #address-cells = <2>; 521 #size-cells = <2>; 522 reg = <0x0 0x46000000 0x0 0x200000>; 523 reg-names = "cpsw_nuss"; 524 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 525 dma-coherent; 526 clocks = <&k3_clks 29 28>; 527 clock-names = "fck"; 528 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 529 530 dmas = <&mcu_udmap 0xf000>, 531 <&mcu_udmap 0xf001>, 532 <&mcu_udmap 0xf002>, 533 <&mcu_udmap 0xf003>, 534 <&mcu_udmap 0xf004>, 535 <&mcu_udmap 0xf005>, 536 <&mcu_udmap 0xf006>, 537 <&mcu_udmap 0xf007>, 538 <&mcu_udmap 0x7000>; 539 dma-names = "tx0", "tx1", "tx2", "tx3", 540 "tx4", "tx5", "tx6", "tx7", 541 "rx"; 542 543 ethernet-ports { 544 #address-cells = <1>; 545 #size-cells = <0>; 546 547 cpsw_port1: port@1 { 548 reg = <1>; 549 ti,mac-only; 550 label = "port1"; 551 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 552 phys = <&phy_gmii_sel 1>; 553 }; 554 }; 555 556 davinci_mdio: mdio@f00 { 557 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 558 reg = <0x0 0xf00 0x0 0x100>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&k3_clks 29 28>; 562 clock-names = "fck"; 563 bus_freq = <1000000>; 564 }; 565 566 cpts@3d000 { 567 compatible = "ti,am65-cpts"; 568 reg = <0x0 0x3d000 0x0 0x400>; 569 clocks = <&k3_clks 29 3>; 570 clock-names = "cpts"; 571 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ 572 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ 573 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "cpts"; 575 ti,cpts-ext-ts-inputs = <4>; 576 ti,cpts-periodic-outputs = <2>; 577 }; 578 }; 579 580 tscadc0: tscadc@40200000 { 581 compatible = "ti,am3359-tscadc"; 582 reg = <0x00 0x40200000 0x00 0x1000>; 583 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 584 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 585 clocks = <&k3_clks 0 0>; 586 assigned-clocks = <&k3_clks 0 2>; 587 assigned-clock-rates = <60000000>; 588 clock-names = "fck"; 589 dmas = <&main_udmap 0x7400>, 590 <&main_udmap 0x7401>; 591 dma-names = "fifo0", "fifo1"; 592 status = "disabled"; 593 594 adc { 595 #io-channel-cells = <1>; 596 compatible = "ti,am3359-adc"; 597 }; 598 }; 599 600 tscadc1: tscadc@40210000 { 601 compatible = "ti,am3359-tscadc"; 602 reg = <0x00 0x40210000 0x00 0x1000>; 603 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 604 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 605 clocks = <&k3_clks 1 0>; 606 assigned-clocks = <&k3_clks 1 2>; 607 assigned-clock-rates = <60000000>; 608 clock-names = "fck"; 609 dmas = <&main_udmap 0x7402>, 610 <&main_udmap 0x7403>; 611 dma-names = "fifo0", "fifo1"; 612 status = "disabled"; 613 614 adc { 615 #io-channel-cells = <1>; 616 compatible = "ti,am3359-adc"; 617 }; 618 }; 619 620 fss: bus@47000000 { 621 compatible = "simple-bus"; 622 #address-cells = <2>; 623 #size-cells = <2>; 624 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 625 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 626 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; 627 628 ospi0: spi@47040000 { 629 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 630 reg = <0x00 0x47040000 0x00 0x100>, 631 <0x05 0x00000000 0x01 0x00000000>; 632 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 633 cdns,fifo-depth = <256>; 634 cdns,fifo-width = <4>; 635 cdns,trigger-address = <0x0>; 636 clocks = <&k3_clks 109 5>; 637 assigned-clocks = <&k3_clks 109 5>; 638 assigned-clock-parents = <&k3_clks 109 7>; 639 assigned-clock-rates = <166666666>; 640 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 644 status = "disabled"; /* Needs pinmux */ 645 }; 646 647 ospi1: spi@47050000 { 648 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 649 reg = <0x00 0x47050000 0x00 0x100>, 650 <0x07 0x00000000 0x01 0x00000000>; 651 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 652 cdns,fifo-depth = <256>; 653 cdns,fifo-width = <4>; 654 cdns,trigger-address = <0x0>; 655 clocks = <&k3_clks 110 5>; 656 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 status = "disabled"; /* Needs pinmux */ 661 }; 662 }; 663 664 wkup_vtm0: temperature-sensor@42040000 { 665 compatible = "ti,j7200-vtm"; 666 reg = <0x00 0x42040000 0x0 0x350>, 667 <0x00 0x42050000 0x0 0x350>; 668 power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; 669 #thermal-sensor-cells = <1>; 670 }; 671 672 mcu_r5fss0: r5fss@41000000 { 673 compatible = "ti,j721s2-r5fss"; 674 ti,cluster-mode = <1>; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges = <0x41000000 0x00 0x41000000 0x20000>, 678 <0x41400000 0x00 0x41400000 0x20000>; 679 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 680 681 mcu_r5fss0_core0: r5f@41000000 { 682 compatible = "ti,j721s2-r5f"; 683 reg = <0x41000000 0x00010000>, 684 <0x41010000 0x00010000>; 685 reg-names = "atcm", "btcm"; 686 ti,sci = <&sms>; 687 ti,sci-dev-id = <284>; 688 ti,sci-proc-ids = <0x01 0xff>; 689 resets = <&k3_reset 284 1>; 690 firmware-name = "j721s2-mcu-r5f0_0-fw"; 691 ti,atcm-enable = <1>; 692 ti,btcm-enable = <1>; 693 ti,loczrama = <1>; 694 }; 695 696 mcu_r5fss0_core1: r5f@41400000 { 697 compatible = "ti,j721s2-r5f"; 698 reg = <0x41400000 0x00010000>, 699 <0x41410000 0x00010000>; 700 reg-names = "atcm", "btcm"; 701 ti,sci = <&sms>; 702 ti,sci-dev-id = <285>; 703 ti,sci-proc-ids = <0x02 0xff>; 704 resets = <&k3_reset 285 1>; 705 firmware-name = "j721s2-mcu-r5f0_1-fw"; 706 ti,atcm-enable = <1>; 707 ti,btcm-enable = <1>; 708 ti,loczrama = <1>; 709 }; 710 }; 711 712 mcu_esm: esm@40800000 { 713 compatible = "ti,j721e-esm"; 714 reg = <0x00 0x40800000 0x00 0x1000>; 715 ti,esm-pins = <95>; 716 bootph-pre-ram; 717 }; 718 719 wkup_esm: esm@42080000 { 720 compatible = "ti,j721e-esm"; 721 reg = <0x00 0x42080000 0x00 0x1000>; 722 ti,esm-pins = <63>; 723 bootph-pre-ram; 724 }; 725 726 /* 727 * The 2 RTI instances are couple with MCU R5Fs so keeping them 728 * reserved as these will be used by their respective firmware 729 */ 730 mcu_watchdog0: watchdog@40600000 { 731 compatible = "ti,j7-rti-wdt"; 732 reg = <0x00 0x40600000 0x00 0x100>; 733 clocks = <&k3_clks 295 1>; 734 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 735 assigned-clocks = <&k3_clks 295 1>; 736 assigned-clock-parents = <&k3_clks 295 5>; 737 /* reserved for MCU_R5F0_0 */ 738 status = "reserved"; 739 }; 740 741 mcu_watchdog1: watchdog@40610000 { 742 compatible = "ti,j7-rti-wdt"; 743 reg = <0x00 0x40610000 0x00 0x100>; 744 clocks = <&k3_clks 296 1>; 745 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; 746 assigned-clocks = <&k3_clks 296 1>; 747 assigned-clock-parents = <&k3_clks 296 5>; 748 /* reserved for MCU_R5F0_1 */ 749 status = "reserved"; 750 }; 751}; 752