1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 msmc_ram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x0 0x70000000 0x0 0x400000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x0 0x70000000 0x400000>; 26 27 atf-sram@0 { 28 reg = <0x0 0x20000>; 29 }; 30 31 tifs-sram@1f0000 { 32 reg = <0x1f0000 0x10000>; 33 }; 34 35 l3cache-sram@200000 { 36 reg = <0x200000 0x200000>; 37 }; 38 }; 39 40 scm_conf: syscon@104000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x00 0x00104000 0x00 0x18000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x00 0x00 0x00104000 0x18000>; 46 47 usb_serdes_mux: mux-controller@0 { 48 compatible = "reg-mux"; 49 reg = <0x0 0x4>; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 52 }; 53 54 phy_gmii_sel_cpsw: phy@34 { 55 compatible = "ti,am654-phy-gmii-sel"; 56 reg = <0x34 0x4>; 57 #phy-cells = <1>; 58 }; 59 60 serdes_ln_ctrl: mux-controller@80 { 61 compatible = "reg-mux"; 62 reg = <0x80 0x10>; 63 #mux-control-cells = <1>; 64 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 65 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ 66 }; 67 68 ehrpwm_tbclk: clock-controller@140 { 69 compatible = "ti,am654-ehrpwm-tbclk"; 70 reg = <0x140 0x18>; 71 #clock-cells = <1>; 72 }; 73 }; 74 75 main_ehrpwm0: pwm@3000000 { 76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 77 #pwm-cells = <3>; 78 reg = <0x00 0x3000000 0x00 0x100>; 79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 80 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; 81 clock-names = "tbclk", "fck"; 82 status = "disabled"; 83 }; 84 85 main_ehrpwm1: pwm@3010000 { 86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 87 #pwm-cells = <3>; 88 reg = <0x00 0x3010000 0x00 0x100>; 89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 90 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; 91 clock-names = "tbclk", "fck"; 92 status = "disabled"; 93 }; 94 95 main_ehrpwm2: pwm@3020000 { 96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 97 #pwm-cells = <3>; 98 reg = <0x00 0x3020000 0x00 0x100>; 99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; 101 clock-names = "tbclk", "fck"; 102 status = "disabled"; 103 }; 104 105 main_ehrpwm3: pwm@3030000 { 106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 107 #pwm-cells = <3>; 108 reg = <0x00 0x3030000 0x00 0x100>; 109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 110 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; 111 clock-names = "tbclk", "fck"; 112 status = "disabled"; 113 }; 114 115 main_ehrpwm4: pwm@3040000 { 116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 117 #pwm-cells = <3>; 118 reg = <0x00 0x3040000 0x00 0x100>; 119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 120 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; 121 clock-names = "tbclk", "fck"; 122 status = "disabled"; 123 }; 124 125 main_ehrpwm5: pwm@3050000 { 126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 127 #pwm-cells = <3>; 128 reg = <0x00 0x3050000 0x00 0x100>; 129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 130 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; 131 clock-names = "tbclk", "fck"; 132 status = "disabled"; 133 }; 134 135 gic500: interrupt-controller@1800000 { 136 compatible = "arm,gic-v3"; 137 #address-cells = <2>; 138 #size-cells = <2>; 139 ranges; 140 #interrupt-cells = <3>; 141 interrupt-controller; 142 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ 143 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 144 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 145 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 146 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 147 148 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 150 151 gic_its: msi-controller@1820000 { 152 compatible = "arm,gic-v3-its"; 153 reg = <0x00 0x01820000 0x00 0x10000>; 154 socionext,synquacer-pre-its = <0x1000000 0x400000>; 155 msi-controller; 156 #msi-cells = <1>; 157 }; 158 }; 159 160 main_gpio_intr: interrupt-controller@a00000 { 161 compatible = "ti,sci-intr"; 162 reg = <0x00 0x00a00000 0x00 0x800>; 163 ti,intr-trigger-type = <1>; 164 interrupt-controller; 165 interrupt-parent = <&gic500>; 166 #interrupt-cells = <1>; 167 ti,sci = <&sms>; 168 ti,sci-dev-id = <148>; 169 ti,interrupt-ranges = <8 392 56>; 170 }; 171 172 main_pmx0: pinctrl@11c000 { 173 compatible = "pinctrl-single"; 174 /* Proxy 0 addressing */ 175 reg = <0x0 0x11c000 0x0 0x120>; 176 #pinctrl-cells = <1>; 177 pinctrl-single,register-width = <32>; 178 pinctrl-single,function-mask = <0xffffffff>; 179 }; 180 181 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 182 main_timerio_input: pinctrl@104200 { 183 compatible = "pinctrl-single"; 184 reg = <0x00 0x104200 0x00 0x50>; 185 #pinctrl-cells = <1>; 186 pinctrl-single,register-width = <32>; 187 pinctrl-single,function-mask = <0x00000007>; 188 }; 189 190 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 191 main_timerio_output: pinctrl@104280 { 192 compatible = "pinctrl-single"; 193 reg = <0x00 0x104280 0x00 0x20>; 194 #pinctrl-cells = <1>; 195 pinctrl-single,register-width = <32>; 196 pinctrl-single,function-mask = <0x0000001f>; 197 }; 198 199 main_crypto: crypto@4e00000 { 200 compatible = "ti,j721e-sa2ul"; 201 reg = <0x00 0x04e00000 0x00 0x1200>; 202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 206 207 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 208 <&main_udmap 0x4a41>; 209 dma-names = "tx", "rx1", "rx2"; 210 211 rng: rng@4e10000 { 212 compatible = "inside-secure,safexcel-eip76"; 213 reg = <0x00 0x04e10000 0x00 0x7d>; 214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 215 }; 216 }; 217 218 main_timer0: timer@2400000 { 219 compatible = "ti,am654-timer"; 220 reg = <0x00 0x2400000 0x00 0x400>; 221 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&k3_clks 63 1>; 223 clock-names = "fck"; 224 assigned-clocks = <&k3_clks 63 1>; 225 assigned-clock-parents = <&k3_clks 63 2>; 226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 227 ti,timer-pwm; 228 }; 229 230 main_timer1: timer@2410000 { 231 compatible = "ti,am654-timer"; 232 reg = <0x00 0x2410000 0x00 0x400>; 233 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&k3_clks 64 1>; 235 clock-names = "fck"; 236 assigned-clocks = <&k3_clks 64 1>; 237 assigned-clock-parents = <&k3_clks 64 2>; 238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 239 ti,timer-pwm; 240 }; 241 242 main_timer2: timer@2420000 { 243 compatible = "ti,am654-timer"; 244 reg = <0x00 0x2420000 0x00 0x400>; 245 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&k3_clks 65 1>; 247 clock-names = "fck"; 248 assigned-clocks = <&k3_clks 65 1>; 249 assigned-clock-parents = <&k3_clks 65 2>; 250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 251 ti,timer-pwm; 252 }; 253 254 main_timer3: timer@2430000 { 255 compatible = "ti,am654-timer"; 256 reg = <0x00 0x2430000 0x00 0x400>; 257 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&k3_clks 66 1>; 259 clock-names = "fck"; 260 assigned-clocks = <&k3_clks 66 1>; 261 assigned-clock-parents = <&k3_clks 66 2>; 262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 263 ti,timer-pwm; 264 }; 265 266 main_timer4: timer@2440000 { 267 compatible = "ti,am654-timer"; 268 reg = <0x00 0x2440000 0x00 0x400>; 269 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&k3_clks 67 1>; 271 clock-names = "fck"; 272 assigned-clocks = <&k3_clks 67 1>; 273 assigned-clock-parents = <&k3_clks 67 2>; 274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 275 ti,timer-pwm; 276 }; 277 278 main_timer5: timer@2450000 { 279 compatible = "ti,am654-timer"; 280 reg = <0x00 0x2450000 0x00 0x400>; 281 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&k3_clks 68 1>; 283 clock-names = "fck"; 284 assigned-clocks = <&k3_clks 68 1>; 285 assigned-clock-parents = <&k3_clks 68 2>; 286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 287 ti,timer-pwm; 288 }; 289 290 main_timer6: timer@2460000 { 291 compatible = "ti,am654-timer"; 292 reg = <0x00 0x2460000 0x00 0x400>; 293 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&k3_clks 69 1>; 295 clock-names = "fck"; 296 assigned-clocks = <&k3_clks 69 1>; 297 assigned-clock-parents = <&k3_clks 69 2>; 298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 299 ti,timer-pwm; 300 }; 301 302 main_timer7: timer@2470000 { 303 compatible = "ti,am654-timer"; 304 reg = <0x00 0x2470000 0x00 0x400>; 305 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&k3_clks 70 1>; 307 clock-names = "fck"; 308 assigned-clocks = <&k3_clks 70 1>; 309 assigned-clock-parents = <&k3_clks 70 2>; 310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 311 ti,timer-pwm; 312 }; 313 314 main_timer8: timer@2480000 { 315 compatible = "ti,am654-timer"; 316 reg = <0x00 0x2480000 0x00 0x400>; 317 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&k3_clks 71 1>; 319 clock-names = "fck"; 320 assigned-clocks = <&k3_clks 71 1>; 321 assigned-clock-parents = <&k3_clks 71 2>; 322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 323 ti,timer-pwm; 324 }; 325 326 main_timer9: timer@2490000 { 327 compatible = "ti,am654-timer"; 328 reg = <0x00 0x2490000 0x00 0x400>; 329 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&k3_clks 72 1>; 331 clock-names = "fck"; 332 assigned-clocks = <&k3_clks 72 1>; 333 assigned-clock-parents = <&k3_clks 72 2>; 334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 335 ti,timer-pwm; 336 }; 337 338 main_timer10: timer@24a0000 { 339 compatible = "ti,am654-timer"; 340 reg = <0x00 0x24a0000 0x00 0x400>; 341 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&k3_clks 73 1>; 343 clock-names = "fck"; 344 assigned-clocks = <&k3_clks 73 1>; 345 assigned-clock-parents = <&k3_clks 73 2>; 346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 347 ti,timer-pwm; 348 }; 349 350 main_timer11: timer@24b0000 { 351 compatible = "ti,am654-timer"; 352 reg = <0x00 0x24b0000 0x00 0x400>; 353 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&k3_clks 74 1>; 355 clock-names = "fck"; 356 assigned-clocks = <&k3_clks 74 1>; 357 assigned-clock-parents = <&k3_clks 74 2>; 358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 359 ti,timer-pwm; 360 }; 361 362 main_timer12: timer@24c0000 { 363 compatible = "ti,am654-timer"; 364 reg = <0x00 0x24c0000 0x00 0x400>; 365 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&k3_clks 75 1>; 367 clock-names = "fck"; 368 assigned-clocks = <&k3_clks 75 1>; 369 assigned-clock-parents = <&k3_clks 75 2>; 370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 371 ti,timer-pwm; 372 }; 373 374 main_timer13: timer@24d0000 { 375 compatible = "ti,am654-timer"; 376 reg = <0x00 0x24d0000 0x00 0x400>; 377 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&k3_clks 76 1>; 379 clock-names = "fck"; 380 assigned-clocks = <&k3_clks 76 1>; 381 assigned-clock-parents = <&k3_clks 76 2>; 382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 383 ti,timer-pwm; 384 }; 385 386 main_timer14: timer@24e0000 { 387 compatible = "ti,am654-timer"; 388 reg = <0x00 0x24e0000 0x00 0x400>; 389 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&k3_clks 77 1>; 391 clock-names = "fck"; 392 assigned-clocks = <&k3_clks 77 1>; 393 assigned-clock-parents = <&k3_clks 77 2>; 394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 395 ti,timer-pwm; 396 }; 397 398 main_timer15: timer@24f0000 { 399 compatible = "ti,am654-timer"; 400 reg = <0x00 0x24f0000 0x00 0x400>; 401 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&k3_clks 78 1>; 403 clock-names = "fck"; 404 assigned-clocks = <&k3_clks 78 1>; 405 assigned-clock-parents = <&k3_clks 78 2>; 406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 407 ti,timer-pwm; 408 }; 409 410 main_timer16: timer@2500000 { 411 compatible = "ti,am654-timer"; 412 reg = <0x00 0x2500000 0x00 0x400>; 413 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&k3_clks 79 1>; 415 clock-names = "fck"; 416 assigned-clocks = <&k3_clks 79 1>; 417 assigned-clock-parents = <&k3_clks 79 2>; 418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 419 ti,timer-pwm; 420 }; 421 422 main_timer17: timer@2510000 { 423 compatible = "ti,am654-timer"; 424 reg = <0x00 0x2510000 0x00 0x400>; 425 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&k3_clks 80 1>; 427 clock-names = "fck"; 428 assigned-clocks = <&k3_clks 80 1>; 429 assigned-clock-parents = <&k3_clks 80 2>; 430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 431 ti,timer-pwm; 432 }; 433 434 main_timer18: timer@2520000 { 435 compatible = "ti,am654-timer"; 436 reg = <0x00 0x2520000 0x00 0x400>; 437 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&k3_clks 81 1>; 439 clock-names = "fck"; 440 assigned-clocks = <&k3_clks 81 1>; 441 assigned-clock-parents = <&k3_clks 81 2>; 442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 443 ti,timer-pwm; 444 }; 445 446 main_timer19: timer@2530000 { 447 compatible = "ti,am654-timer"; 448 reg = <0x00 0x2530000 0x00 0x400>; 449 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&k3_clks 82 1>; 451 clock-names = "fck"; 452 assigned-clocks = <&k3_clks 82 1>; 453 assigned-clock-parents = <&k3_clks 82 2>; 454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 455 ti,timer-pwm; 456 }; 457 458 main_uart0: serial@2800000 { 459 compatible = "ti,j721e-uart", "ti,am654-uart"; 460 reg = <0x00 0x02800000 0x00 0x200>; 461 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&k3_clks 146 3>; 463 clock-names = "fclk"; 464 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 465 status = "disabled"; 466 }; 467 468 main_uart1: serial@2810000 { 469 compatible = "ti,j721e-uart", "ti,am654-uart"; 470 reg = <0x00 0x02810000 0x00 0x200>; 471 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&k3_clks 350 3>; 473 clock-names = "fclk"; 474 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 475 status = "disabled"; 476 }; 477 478 main_uart2: serial@2820000 { 479 compatible = "ti,j721e-uart", "ti,am654-uart"; 480 reg = <0x00 0x02820000 0x00 0x200>; 481 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&k3_clks 351 3>; 483 clock-names = "fclk"; 484 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 485 status = "disabled"; 486 }; 487 488 main_uart3: serial@2830000 { 489 compatible = "ti,j721e-uart", "ti,am654-uart"; 490 reg = <0x00 0x02830000 0x00 0x200>; 491 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&k3_clks 352 3>; 493 clock-names = "fclk"; 494 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 495 status = "disabled"; 496 }; 497 498 main_uart4: serial@2840000 { 499 compatible = "ti,j721e-uart", "ti,am654-uart"; 500 reg = <0x00 0x02840000 0x00 0x200>; 501 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&k3_clks 353 3>; 503 clock-names = "fclk"; 504 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 505 status = "disabled"; 506 }; 507 508 main_uart5: serial@2850000 { 509 compatible = "ti,j721e-uart", "ti,am654-uart"; 510 reg = <0x00 0x02850000 0x00 0x200>; 511 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&k3_clks 354 3>; 513 clock-names = "fclk"; 514 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 515 status = "disabled"; 516 }; 517 518 main_uart6: serial@2860000 { 519 compatible = "ti,j721e-uart", "ti,am654-uart"; 520 reg = <0x00 0x02860000 0x00 0x200>; 521 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&k3_clks 355 3>; 523 clock-names = "fclk"; 524 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 525 status = "disabled"; 526 }; 527 528 main_uart7: serial@2870000 { 529 compatible = "ti,j721e-uart", "ti,am654-uart"; 530 reg = <0x00 0x02870000 0x00 0x200>; 531 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&k3_clks 356 3>; 533 clock-names = "fclk"; 534 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 535 status = "disabled"; 536 }; 537 538 main_uart8: serial@2880000 { 539 compatible = "ti,j721e-uart", "ti,am654-uart"; 540 reg = <0x00 0x02880000 0x00 0x200>; 541 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&k3_clks 357 3>; 543 clock-names = "fclk"; 544 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 545 status = "disabled"; 546 }; 547 548 main_uart9: serial@2890000 { 549 compatible = "ti,j721e-uart", "ti,am654-uart"; 550 reg = <0x00 0x02890000 0x00 0x200>; 551 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&k3_clks 358 3>; 553 clock-names = "fclk"; 554 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 555 status = "disabled"; 556 }; 557 558 main_gpio0: gpio@600000 { 559 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 560 reg = <0x00 0x00600000 0x00 0x100>; 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-parent = <&main_gpio_intr>; 564 interrupts = <145>, <146>, <147>, <148>, <149>; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 ti,ngpio = <66>; 568 ti,davinci-gpio-unbanked = <0>; 569 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 570 clocks = <&k3_clks 111 0>; 571 clock-names = "gpio"; 572 status = "disabled"; 573 }; 574 575 main_gpio2: gpio@610000 { 576 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 577 reg = <0x00 0x00610000 0x00 0x100>; 578 gpio-controller; 579 #gpio-cells = <2>; 580 interrupt-parent = <&main_gpio_intr>; 581 interrupts = <154>, <155>, <156>, <157>, <158>; 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 ti,ngpio = <66>; 585 ti,davinci-gpio-unbanked = <0>; 586 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 587 clocks = <&k3_clks 112 0>; 588 clock-names = "gpio"; 589 status = "disabled"; 590 }; 591 592 main_gpio4: gpio@620000 { 593 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 594 reg = <0x00 0x00620000 0x00 0x100>; 595 gpio-controller; 596 #gpio-cells = <2>; 597 interrupt-parent = <&main_gpio_intr>; 598 interrupts = <163>, <164>, <165>, <166>, <167>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 ti,ngpio = <66>; 602 ti,davinci-gpio-unbanked = <0>; 603 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 604 clocks = <&k3_clks 113 0>; 605 clock-names = "gpio"; 606 status = "disabled"; 607 }; 608 609 main_gpio6: gpio@630000 { 610 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 611 reg = <0x00 0x00630000 0x00 0x100>; 612 gpio-controller; 613 #gpio-cells = <2>; 614 interrupt-parent = <&main_gpio_intr>; 615 interrupts = <172>, <173>, <174>, <175>, <176>; 616 interrupt-controller; 617 #interrupt-cells = <2>; 618 ti,ngpio = <66>; 619 ti,davinci-gpio-unbanked = <0>; 620 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 621 clocks = <&k3_clks 114 0>; 622 clock-names = "gpio"; 623 status = "disabled"; 624 }; 625 626 main_i2c0: i2c@2000000 { 627 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 628 reg = <0x00 0x02000000 0x00 0x100>; 629 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 clocks = <&k3_clks 214 1>; 633 clock-names = "fck"; 634 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 635 }; 636 637 main_i2c1: i2c@2010000 { 638 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 639 reg = <0x00 0x02010000 0x00 0x100>; 640 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 clocks = <&k3_clks 215 1>; 644 clock-names = "fck"; 645 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 646 status = "disabled"; 647 }; 648 649 main_i2c2: i2c@2020000 { 650 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 651 reg = <0x00 0x02020000 0x00 0x100>; 652 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 clocks = <&k3_clks 216 1>; 656 clock-names = "fck"; 657 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 658 status = "disabled"; 659 }; 660 661 main_i2c3: i2c@2030000 { 662 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 663 reg = <0x00 0x02030000 0x00 0x100>; 664 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 clocks = <&k3_clks 217 1>; 668 clock-names = "fck"; 669 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 670 status = "disabled"; 671 }; 672 673 main_i2c4: i2c@2040000 { 674 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 675 reg = <0x00 0x02040000 0x00 0x100>; 676 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&k3_clks 218 1>; 680 clock-names = "fck"; 681 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 682 status = "disabled"; 683 }; 684 685 main_i2c5: i2c@2050000 { 686 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 687 reg = <0x00 0x02050000 0x00 0x100>; 688 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 clocks = <&k3_clks 219 1>; 692 clock-names = "fck"; 693 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 694 status = "disabled"; 695 }; 696 697 main_i2c6: i2c@2060000 { 698 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 699 reg = <0x00 0x02060000 0x00 0x100>; 700 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 clocks = <&k3_clks 220 1>; 704 clock-names = "fck"; 705 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 706 status = "disabled"; 707 }; 708 709 vpu: video-codec@4210000 { 710 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 711 reg = <0x00 0x4210000 0x00 0x10000>; 712 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&k3_clks 179 2>; 714 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 715 }; 716 717 main_sdhci0: mmc@4f80000 { 718 compatible = "ti,j721e-sdhci-8bit"; 719 reg = <0x00 0x04f80000 0x00 0x1000>, 720 <0x00 0x04f88000 0x00 0x400>; 721 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 722 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 723 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; 724 clock-names = "clk_ahb", "clk_xin"; 725 assigned-clocks = <&k3_clks 98 1>; 726 assigned-clock-parents = <&k3_clks 98 2>; 727 bus-width = <8>; 728 ti,otap-del-sel-legacy = <0x0>; 729 ti,otap-del-sel-mmc-hs = <0x0>; 730 ti,otap-del-sel-ddr52 = <0x6>; 731 ti,otap-del-sel-hs200 = <0x8>; 732 ti,otap-del-sel-hs400 = <0x5>; 733 ti,itap-del-sel-legacy = <0x10>; 734 ti,itap-del-sel-mmc-hs = <0xa>; 735 ti,strobe-sel = <0x77>; 736 ti,clkbuf-sel = <0x7>; 737 ti,trm-icp = <0x8>; 738 mmc-ddr-1_8v; 739 mmc-hs200-1_8v; 740 mmc-hs400-1_8v; 741 dma-coherent; 742 status = "disabled"; 743 }; 744 745 main_sdhci1: mmc@4fb0000 { 746 compatible = "ti,j721e-sdhci-4bit"; 747 reg = <0x00 0x04fb0000 0x00 0x1000>, 748 <0x00 0x04fb8000 0x00 0x400>; 749 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 750 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 751 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; 752 clock-names = "clk_ahb", "clk_xin"; 753 assigned-clocks = <&k3_clks 99 1>; 754 assigned-clock-parents = <&k3_clks 99 2>; 755 bus-width = <4>; 756 ti,otap-del-sel-legacy = <0x0>; 757 ti,otap-del-sel-sd-hs = <0x0>; 758 ti,otap-del-sel-sdr12 = <0xf>; 759 ti,otap-del-sel-sdr25 = <0xf>; 760 ti,otap-del-sel-sdr50 = <0xc>; 761 ti,otap-del-sel-sdr104 = <0x5>; 762 ti,otap-del-sel-ddr50 = <0xc>; 763 ti,itap-del-sel-legacy = <0x0>; 764 ti,itap-del-sel-sd-hs = <0x0>; 765 ti,itap-del-sel-sdr12 = <0x0>; 766 ti,itap-del-sel-sdr25 = <0x0>; 767 ti,itap-del-sel-ddr50 = <0x2>; 768 ti,clkbuf-sel = <0x7>; 769 ti,trm-icp = <0x8>; 770 dma-coherent; 771 status = "disabled"; 772 }; 773 774 main_navss: bus@30000000 { 775 compatible = "simple-bus"; 776 #address-cells = <2>; 777 #size-cells = <2>; 778 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 779 ti,sci-dev-id = <224>; 780 dma-coherent; 781 dma-ranges; 782 783 main_navss_intr: interrupt-controller@310e0000 { 784 compatible = "ti,sci-intr"; 785 reg = <0x00 0x310e0000 0x00 0x4000>; 786 ti,intr-trigger-type = <4>; 787 interrupt-controller; 788 interrupt-parent = <&gic500>; 789 #interrupt-cells = <1>; 790 ti,sci = <&sms>; 791 ti,sci-dev-id = <227>; 792 ti,interrupt-ranges = <0 64 64>, 793 <64 448 64>, 794 <128 672 64>; 795 }; 796 797 main_udmass_inta: msi-controller@33d00000 { 798 compatible = "ti,sci-inta"; 799 reg = <0x00 0x33d00000 0x00 0x100000>; 800 interrupt-controller; 801 #interrupt-cells = <0>; 802 interrupt-parent = <&main_navss_intr>; 803 msi-controller; 804 ti,sci = <&sms>; 805 ti,sci-dev-id = <265>; 806 ti,interrupt-ranges = <0 0 256>; 807 ti,unmapped-event-sources = <&main_bcdma_csi>; 808 }; 809 810 secure_proxy_main: mailbox@32c00000 { 811 compatible = "ti,am654-secure-proxy"; 812 #mbox-cells = <1>; 813 reg-names = "target_data", "rt", "scfg"; 814 reg = <0x00 0x32c00000 0x00 0x100000>, 815 <0x00 0x32400000 0x00 0x100000>, 816 <0x00 0x32800000 0x00 0x100000>; 817 interrupt-names = "rx_011"; 818 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 819 bootph-all; 820 }; 821 822 hwspinlock: spinlock@30e00000 { 823 compatible = "ti,am654-hwspinlock"; 824 reg = <0x00 0x30e00000 0x00 0x1000>; 825 #hwlock-cells = <1>; 826 }; 827 828 mailbox0_cluster0: mailbox@31f80000 { 829 compatible = "ti,am654-mailbox"; 830 reg = <0x00 0x31f80000 0x00 0x200>; 831 #mbox-cells = <1>; 832 ti,mbox-num-users = <4>; 833 ti,mbox-num-fifos = <16>; 834 interrupt-parent = <&main_navss_intr>; 835 status = "disabled"; 836 }; 837 838 mailbox0_cluster1: mailbox@31f81000 { 839 compatible = "ti,am654-mailbox"; 840 reg = <0x00 0x31f81000 0x00 0x200>; 841 #mbox-cells = <1>; 842 ti,mbox-num-users = <4>; 843 ti,mbox-num-fifos = <16>; 844 interrupt-parent = <&main_navss_intr>; 845 status = "disabled"; 846 }; 847 848 mailbox0_cluster2: mailbox@31f82000 { 849 compatible = "ti,am654-mailbox"; 850 reg = <0x00 0x31f82000 0x00 0x200>; 851 #mbox-cells = <1>; 852 ti,mbox-num-users = <4>; 853 ti,mbox-num-fifos = <16>; 854 interrupt-parent = <&main_navss_intr>; 855 status = "disabled"; 856 }; 857 858 mailbox0_cluster3: mailbox@31f83000 { 859 compatible = "ti,am654-mailbox"; 860 reg = <0x00 0x31f83000 0x00 0x200>; 861 #mbox-cells = <1>; 862 ti,mbox-num-users = <4>; 863 ti,mbox-num-fifos = <16>; 864 interrupt-parent = <&main_navss_intr>; 865 status = "disabled"; 866 }; 867 868 mailbox0_cluster4: mailbox@31f84000 { 869 compatible = "ti,am654-mailbox"; 870 reg = <0x00 0x31f84000 0x00 0x200>; 871 #mbox-cells = <1>; 872 ti,mbox-num-users = <4>; 873 ti,mbox-num-fifos = <16>; 874 interrupt-parent = <&main_navss_intr>; 875 status = "disabled"; 876 }; 877 878 mailbox0_cluster5: mailbox@31f85000 { 879 compatible = "ti,am654-mailbox"; 880 reg = <0x00 0x31f85000 0x00 0x200>; 881 #mbox-cells = <1>; 882 ti,mbox-num-users = <4>; 883 ti,mbox-num-fifos = <16>; 884 interrupt-parent = <&main_navss_intr>; 885 status = "disabled"; 886 }; 887 888 mailbox0_cluster6: mailbox@31f86000 { 889 compatible = "ti,am654-mailbox"; 890 reg = <0x00 0x31f86000 0x00 0x200>; 891 #mbox-cells = <1>; 892 ti,mbox-num-users = <4>; 893 ti,mbox-num-fifos = <16>; 894 interrupt-parent = <&main_navss_intr>; 895 status = "disabled"; 896 }; 897 898 mailbox0_cluster7: mailbox@31f87000 { 899 compatible = "ti,am654-mailbox"; 900 reg = <0x00 0x31f87000 0x00 0x200>; 901 #mbox-cells = <1>; 902 ti,mbox-num-users = <4>; 903 ti,mbox-num-fifos = <16>; 904 interrupt-parent = <&main_navss_intr>; 905 status = "disabled"; 906 }; 907 908 mailbox0_cluster8: mailbox@31f88000 { 909 compatible = "ti,am654-mailbox"; 910 reg = <0x00 0x31f88000 0x00 0x200>; 911 #mbox-cells = <1>; 912 ti,mbox-num-users = <4>; 913 ti,mbox-num-fifos = <16>; 914 interrupt-parent = <&main_navss_intr>; 915 status = "disabled"; 916 }; 917 918 mailbox0_cluster9: mailbox@31f89000 { 919 compatible = "ti,am654-mailbox"; 920 reg = <0x00 0x31f89000 0x00 0x200>; 921 #mbox-cells = <1>; 922 ti,mbox-num-users = <4>; 923 ti,mbox-num-fifos = <16>; 924 interrupt-parent = <&main_navss_intr>; 925 status = "disabled"; 926 }; 927 928 mailbox0_cluster10: mailbox@31f8a000 { 929 compatible = "ti,am654-mailbox"; 930 reg = <0x00 0x31f8a000 0x00 0x200>; 931 #mbox-cells = <1>; 932 ti,mbox-num-users = <4>; 933 ti,mbox-num-fifos = <16>; 934 interrupt-parent = <&main_navss_intr>; 935 status = "disabled"; 936 }; 937 938 mailbox0_cluster11: mailbox@31f8b000 { 939 compatible = "ti,am654-mailbox"; 940 reg = <0x00 0x31f8b000 0x00 0x200>; 941 #mbox-cells = <1>; 942 ti,mbox-num-users = <4>; 943 ti,mbox-num-fifos = <16>; 944 interrupt-parent = <&main_navss_intr>; 945 status = "disabled"; 946 }; 947 948 mailbox1_cluster0: mailbox@31f90000 { 949 compatible = "ti,am654-mailbox"; 950 reg = <0x00 0x31f90000 0x00 0x200>; 951 #mbox-cells = <1>; 952 ti,mbox-num-users = <4>; 953 ti,mbox-num-fifos = <16>; 954 interrupt-parent = <&main_navss_intr>; 955 status = "disabled"; 956 }; 957 958 mailbox1_cluster1: mailbox@31f91000 { 959 compatible = "ti,am654-mailbox"; 960 reg = <0x00 0x31f91000 0x00 0x200>; 961 #mbox-cells = <1>; 962 ti,mbox-num-users = <4>; 963 ti,mbox-num-fifos = <16>; 964 interrupt-parent = <&main_navss_intr>; 965 status = "disabled"; 966 }; 967 968 mailbox1_cluster2: mailbox@31f92000 { 969 compatible = "ti,am654-mailbox"; 970 reg = <0x00 0x31f92000 0x00 0x200>; 971 #mbox-cells = <1>; 972 ti,mbox-num-users = <4>; 973 ti,mbox-num-fifos = <16>; 974 interrupt-parent = <&main_navss_intr>; 975 status = "disabled"; 976 }; 977 978 mailbox1_cluster3: mailbox@31f93000 { 979 compatible = "ti,am654-mailbox"; 980 reg = <0x00 0x31f93000 0x00 0x200>; 981 #mbox-cells = <1>; 982 ti,mbox-num-users = <4>; 983 ti,mbox-num-fifos = <16>; 984 interrupt-parent = <&main_navss_intr>; 985 status = "disabled"; 986 }; 987 988 mailbox1_cluster4: mailbox@31f94000 { 989 compatible = "ti,am654-mailbox"; 990 reg = <0x00 0x31f94000 0x00 0x200>; 991 #mbox-cells = <1>; 992 ti,mbox-num-users = <4>; 993 ti,mbox-num-fifos = <16>; 994 interrupt-parent = <&main_navss_intr>; 995 status = "disabled"; 996 }; 997 998 mailbox1_cluster5: mailbox@31f95000 { 999 compatible = "ti,am654-mailbox"; 1000 reg = <0x00 0x31f95000 0x00 0x200>; 1001 #mbox-cells = <1>; 1002 ti,mbox-num-users = <4>; 1003 ti,mbox-num-fifos = <16>; 1004 interrupt-parent = <&main_navss_intr>; 1005 status = "disabled"; 1006 }; 1007 1008 mailbox1_cluster6: mailbox@31f96000 { 1009 compatible = "ti,am654-mailbox"; 1010 reg = <0x00 0x31f96000 0x00 0x200>; 1011 #mbox-cells = <1>; 1012 ti,mbox-num-users = <4>; 1013 ti,mbox-num-fifos = <16>; 1014 interrupt-parent = <&main_navss_intr>; 1015 status = "disabled"; 1016 }; 1017 1018 mailbox1_cluster7: mailbox@31f97000 { 1019 compatible = "ti,am654-mailbox"; 1020 reg = <0x00 0x31f97000 0x00 0x200>; 1021 #mbox-cells = <1>; 1022 ti,mbox-num-users = <4>; 1023 ti,mbox-num-fifos = <16>; 1024 interrupt-parent = <&main_navss_intr>; 1025 status = "disabled"; 1026 }; 1027 1028 mailbox1_cluster8: mailbox@31f98000 { 1029 compatible = "ti,am654-mailbox"; 1030 reg = <0x00 0x31f98000 0x00 0x200>; 1031 #mbox-cells = <1>; 1032 ti,mbox-num-users = <4>; 1033 ti,mbox-num-fifos = <16>; 1034 interrupt-parent = <&main_navss_intr>; 1035 status = "disabled"; 1036 }; 1037 1038 mailbox1_cluster9: mailbox@31f99000 { 1039 compatible = "ti,am654-mailbox"; 1040 reg = <0x00 0x31f99000 0x00 0x200>; 1041 #mbox-cells = <1>; 1042 ti,mbox-num-users = <4>; 1043 ti,mbox-num-fifos = <16>; 1044 interrupt-parent = <&main_navss_intr>; 1045 status = "disabled"; 1046 }; 1047 1048 mailbox1_cluster10: mailbox@31f9a000 { 1049 compatible = "ti,am654-mailbox"; 1050 reg = <0x00 0x31f9a000 0x00 0x200>; 1051 #mbox-cells = <1>; 1052 ti,mbox-num-users = <4>; 1053 ti,mbox-num-fifos = <16>; 1054 interrupt-parent = <&main_navss_intr>; 1055 status = "disabled"; 1056 }; 1057 1058 mailbox1_cluster11: mailbox@31f9b000 { 1059 compatible = "ti,am654-mailbox"; 1060 reg = <0x00 0x31f9b000 0x00 0x200>; 1061 #mbox-cells = <1>; 1062 ti,mbox-num-users = <4>; 1063 ti,mbox-num-fifos = <16>; 1064 interrupt-parent = <&main_navss_intr>; 1065 status = "disabled"; 1066 }; 1067 1068 main_ringacc: ringacc@3c000000 { 1069 compatible = "ti,am654-navss-ringacc"; 1070 reg = <0x0 0x3c000000 0x0 0x400000>, 1071 <0x0 0x38000000 0x0 0x400000>, 1072 <0x0 0x31120000 0x0 0x100>, 1073 <0x0 0x33000000 0x0 0x40000>, 1074 <0x0 0x31080000 0x0 0x40000>; 1075 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1076 ti,num-rings = <1024>; 1077 ti,sci-rm-range-gp-rings = <0x1>; 1078 ti,sci = <&sms>; 1079 ti,sci-dev-id = <259>; 1080 msi-parent = <&main_udmass_inta>; 1081 }; 1082 1083 main_udmap: dma-controller@31150000 { 1084 compatible = "ti,j721e-navss-main-udmap"; 1085 reg = <0x0 0x31150000 0x0 0x100>, 1086 <0x0 0x34000000 0x0 0x80000>, 1087 <0x0 0x35000000 0x0 0x200000>, 1088 <0x0 0x30b00000 0x0 0x20000>, 1089 <0x0 0x30c00000 0x0 0x8000>, 1090 <0x0 0x30d00000 0x0 0x4000>; 1091 reg-names = "gcfg", "rchanrt", "tchanrt", 1092 "tchan", "rchan", "rflow"; 1093 msi-parent = <&main_udmass_inta>; 1094 #dma-cells = <1>; 1095 1096 ti,sci = <&sms>; 1097 ti,sci-dev-id = <263>; 1098 ti,ringacc = <&main_ringacc>; 1099 1100 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1101 <0x0f>, /* TX_HCHAN */ 1102 <0x10>; /* TX_UHCHAN */ 1103 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1104 <0x0b>, /* RX_HCHAN */ 1105 <0x0c>; /* RX_UHCHAN */ 1106 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1107 }; 1108 1109 main_bcdma_csi: dma-controller@311a0000 { 1110 compatible = "ti,j721s2-dmss-bcdma-csi"; 1111 reg = <0x00 0x311a0000 0x00 0x100>, 1112 <0x00 0x35d00000 0x00 0x20000>, 1113 <0x00 0x35c00000 0x00 0x10000>, 1114 <0x00 0x35e00000 0x00 0x80000>; 1115 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1116 msi-parent = <&main_udmass_inta>; 1117 #dma-cells = <3>; 1118 ti,sci = <&sms>; 1119 ti,sci-dev-id = <225>; 1120 ti,sci-rm-range-rchan = <0x21>; 1121 ti,sci-rm-range-tchan = <0x22>; 1122 }; 1123 1124 cpts@310d0000 { 1125 compatible = "ti,j721e-cpts"; 1126 reg = <0x0 0x310d0000 0x0 0x400>; 1127 reg-names = "cpts"; 1128 clocks = <&k3_clks 226 5>; 1129 clock-names = "cpts"; 1130 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ 1131 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ 1132 interrupts-extended = <&main_navss_intr 391>; 1133 interrupt-names = "cpts"; 1134 ti,cpts-periodic-outputs = <6>; 1135 ti,cpts-ext-ts-inputs = <8>; 1136 }; 1137 }; 1138 1139 main_cpsw: ethernet@c200000 { 1140 compatible = "ti,j721e-cpsw-nuss"; 1141 reg = <0x00 0xc200000 0x00 0x200000>; 1142 reg-names = "cpsw_nuss"; 1143 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; 1144 #address-cells = <2>; 1145 #size-cells = <2>; 1146 dma-coherent; 1147 clocks = <&k3_clks 28 28>; 1148 clock-names = "fck"; 1149 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 1150 1151 dmas = <&main_udmap 0xc640>, 1152 <&main_udmap 0xc641>, 1153 <&main_udmap 0xc642>, 1154 <&main_udmap 0xc643>, 1155 <&main_udmap 0xc644>, 1156 <&main_udmap 0xc645>, 1157 <&main_udmap 0xc646>, 1158 <&main_udmap 0xc647>, 1159 <&main_udmap 0x4640>; 1160 dma-names = "tx0", "tx1", "tx2", "tx3", 1161 "tx4", "tx5", "tx6", "tx7", 1162 "rx"; 1163 1164 status = "disabled"; 1165 1166 ethernet-ports { 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 1170 main_cpsw_port1: port@1 { 1171 reg = <1>; 1172 ti,mac-only; 1173 label = "port1"; 1174 phys = <&phy_gmii_sel_cpsw 1>; 1175 status = "disabled"; 1176 }; 1177 }; 1178 1179 main_cpsw_mdio: mdio@f00 { 1180 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1181 reg = <0x00 0xf00 0x00 0x100>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 clocks = <&k3_clks 28 28>; 1185 clock-names = "fck"; 1186 bus_freq = <1000000>; 1187 status = "disabled"; 1188 }; 1189 1190 cpts@3d000 { 1191 compatible = "ti,am65-cpts"; 1192 reg = <0x00 0x3d000 0x00 0x400>; 1193 clocks = <&k3_clks 28 3>; 1194 clock-names = "cpts"; 1195 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1196 interrupt-names = "cpts"; 1197 ti,cpts-ext-ts-inputs = <4>; 1198 ti,cpts-periodic-outputs = <2>; 1199 }; 1200 }; 1201 1202 usbss0: cdns-usb@4104000 { 1203 compatible = "ti,j721e-usb"; 1204 reg = <0x00 0x04104000 0x00 0x100>; 1205 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; 1206 clock-names = "ref", "lpm"; 1207 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ 1208 assigned-clock-parents = <&k3_clks 360 17>; 1209 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 1210 #address-cells = <2>; 1211 #size-cells = <2>; 1212 ranges; 1213 dma-coherent; 1214 1215 status = "disabled"; /* Needs pinmux */ 1216 1217 usb0: usb@6000000 { 1218 compatible = "cdns,usb3"; 1219 reg = <0x00 0x06000000 0x00 0x10000>, 1220 <0x00 0x06010000 0x00 0x10000>, 1221 <0x00 0x06020000 0x00 0x10000>; 1222 reg-names = "otg", "xhci", "dev"; 1223 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1226 interrupt-names = "host", "peripheral", "otg"; 1227 maximum-speed = "super-speed"; 1228 dr_mode = "otg"; 1229 }; 1230 }; 1231 1232 ti_csi2rx0: ticsi2rx@4500000 { 1233 compatible = "ti,j721e-csi2rx-shim"; 1234 reg = <0x00 0x04500000 0x00 0x1000>; 1235 ranges; 1236 #address-cells = <2>; 1237 #size-cells = <2>; 1238 dmas = <&main_bcdma_csi 0 0x4940 0>; 1239 dma-names = "rx0"; 1240 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 1241 status = "disabled"; 1242 1243 cdns_csi2rx0: csi-bridge@4504000 { 1244 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1245 reg = <0x00 0x04504000 0x00 0x1000>; 1246 clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, 1247 <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; 1248 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1249 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1250 phys = <&dphy0>; 1251 phy-names = "dphy"; 1252 1253 ports { 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 1257 csi0_port0: port@0 { 1258 reg = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 csi0_port1: port@1 { 1263 reg = <1>; 1264 status = "disabled"; 1265 }; 1266 1267 csi0_port2: port@2 { 1268 reg = <2>; 1269 status = "disabled"; 1270 }; 1271 1272 csi0_port3: port@3 { 1273 reg = <3>; 1274 status = "disabled"; 1275 }; 1276 1277 csi0_port4: port@4 { 1278 reg = <4>; 1279 status = "disabled"; 1280 }; 1281 }; 1282 }; 1283 }; 1284 1285 ti_csi2rx1: ticsi2rx@4510000 { 1286 compatible = "ti,j721e-csi2rx-shim"; 1287 reg = <0x00 0x04510000 0x00 0x1000>; 1288 ranges; 1289 #address-cells = <2>; 1290 #size-cells = <2>; 1291 dmas = <&main_bcdma_csi 0 0x4960 0>; 1292 dma-names = "rx0"; 1293 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 1294 status = "disabled"; 1295 1296 cdns_csi2rx1: csi-bridge@4514000 { 1297 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1298 reg = <0x00 0x04514000 0x00 0x1000>; 1299 clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, 1300 <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; 1301 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1302 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1303 phys = <&dphy1>; 1304 phy-names = "dphy"; 1305 1306 ports { 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 1310 csi1_port0: port@0 { 1311 reg = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 csi1_port1: port@1 { 1316 reg = <1>; 1317 status = "disabled"; 1318 }; 1319 1320 csi1_port2: port@2 { 1321 reg = <2>; 1322 status = "disabled"; 1323 }; 1324 1325 csi1_port3: port@3 { 1326 reg = <3>; 1327 status = "disabled"; 1328 }; 1329 1330 csi1_port4: port@4 { 1331 reg = <4>; 1332 status = "disabled"; 1333 }; 1334 }; 1335 }; 1336 }; 1337 1338 dphy0: phy@4580000 { 1339 compatible = "cdns,dphy-rx"; 1340 reg = <0x00 0x04580000 0x00 0x1100>; 1341 #phy-cells = <0>; 1342 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1343 status = "disabled"; 1344 }; 1345 1346 dphy1: phy@4590000 { 1347 compatible = "cdns,dphy-rx"; 1348 reg = <0x00 0x04590000 0x00 0x1100>; 1349 #phy-cells = <0>; 1350 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 1351 status = "disabled"; 1352 }; 1353 1354 serdes_wiz0: wiz@5060000 { 1355 compatible = "ti,j721s2-wiz-10g"; 1356 #address-cells = <1>; 1357 #size-cells = <1>; 1358 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1359 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; 1360 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1361 num-lanes = <4>; 1362 #reset-cells = <1>; 1363 #clock-cells = <1>; 1364 ranges = <0x5060000 0x0 0x5060000 0x10000>; 1365 1366 assigned-clocks = <&k3_clks 365 3>; 1367 assigned-clock-parents = <&k3_clks 365 7>; 1368 1369 serdes0: serdes@5060000 { 1370 compatible = "ti,j721e-serdes-10g"; 1371 reg = <0x05060000 0x00010000>; 1372 reg-names = "torrent_phy"; 1373 resets = <&serdes_wiz0 0>; 1374 reset-names = "torrent_reset"; 1375 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1376 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1377 clock-names = "refclk", "phy_en_refclk"; 1378 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1379 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1380 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1381 assigned-clock-parents = <&k3_clks 365 3>, 1382 <&k3_clks 365 3>, 1383 <&k3_clks 365 3>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 #clock-cells = <1>; 1387 1388 status = "disabled"; /* Needs lane config */ 1389 }; 1390 }; 1391 1392 pcie1_rc: pcie@2910000 { 1393 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 1394 reg = <0x00 0x02910000 0x00 0x1000>, 1395 <0x00 0x02917000 0x00 0x400>, 1396 <0x00 0x0d800000 0x00 0x800000>, 1397 <0x00 0x18000000 0x00 0x1000>; 1398 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1399 interrupt-names = "link_state"; 1400 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1401 device_type = "pci"; 1402 ti,syscon-pcie-ctrl = <&scm_conf 0x074>; 1403 max-link-speed = <3>; 1404 num-lanes = <4>; 1405 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 1406 clocks = <&k3_clks 276 41>; 1407 clock-names = "fck"; 1408 #address-cells = <3>; 1409 #size-cells = <2>; 1410 bus-range = <0x0 0xff>; 1411 vendor-id = <0x104c>; 1412 device-id = <0xb013>; 1413 msi-map = <0x0 &gic_its 0x0 0x10000>; 1414 dma-coherent; 1415 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1416 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1417 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1418 #interrupt-cells = <1>; 1419 interrupt-map-mask = <0 0 0 7>; 1420 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ 1421 <0 0 0 2 &pcie1_intc 0>, /* INT B */ 1422 <0 0 0 3 &pcie1_intc 0>, /* INT C */ 1423 <0 0 0 4 &pcie1_intc 0>; /* INT D */ 1424 1425 status = "disabled"; /* Needs gpio and serdes info */ 1426 1427 pcie1_intc: interrupt-controller { 1428 interrupt-controller; 1429 #interrupt-cells = <1>; 1430 interrupt-parent = <&gic500>; 1431 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; 1432 }; 1433 }; 1434 1435 main_mcan0: can@2701000 { 1436 compatible = "bosch,m_can"; 1437 reg = <0x00 0x02701000 0x00 0x200>, 1438 <0x00 0x02708000 0x00 0x8000>; 1439 reg-names = "m_can", "message_ram"; 1440 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1441 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; 1442 clock-names = "hclk", "cclk"; 1443 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1445 interrupt-names = "int0", "int1"; 1446 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1447 status = "disabled"; 1448 }; 1449 1450 main_mcan1: can@2711000 { 1451 compatible = "bosch,m_can"; 1452 reg = <0x00 0x02711000 0x00 0x200>, 1453 <0x00 0x02718000 0x00 0x8000>; 1454 reg-names = "m_can", "message_ram"; 1455 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1456 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; 1457 clock-names = "hclk", "cclk"; 1458 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1460 interrupt-names = "int0", "int1"; 1461 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1462 status = "disabled"; 1463 }; 1464 1465 main_mcan2: can@2721000 { 1466 compatible = "bosch,m_can"; 1467 reg = <0x00 0x02721000 0x00 0x200>, 1468 <0x00 0x02728000 0x00 0x8000>; 1469 reg-names = "m_can", "message_ram"; 1470 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1471 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; 1472 clock-names = "hclk", "cclk"; 1473 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1475 interrupt-names = "int0", "int1"; 1476 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1477 status = "disabled"; 1478 }; 1479 1480 main_mcan3: can@2731000 { 1481 compatible = "bosch,m_can"; 1482 reg = <0x00 0x02731000 0x00 0x200>, 1483 <0x00 0x02738000 0x00 0x8000>; 1484 reg-names = "m_can", "message_ram"; 1485 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1486 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; 1487 clock-names = "hclk", "cclk"; 1488 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1490 interrupt-names = "int0", "int1"; 1491 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1492 status = "disabled"; 1493 }; 1494 1495 main_mcan4: can@2741000 { 1496 compatible = "bosch,m_can"; 1497 reg = <0x00 0x02741000 0x00 0x200>, 1498 <0x00 0x02748000 0x00 0x8000>; 1499 reg-names = "m_can", "message_ram"; 1500 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1501 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; 1502 clock-names = "hclk", "cclk"; 1503 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1505 interrupt-names = "int0", "int1"; 1506 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1507 status = "disabled"; 1508 }; 1509 1510 main_mcan5: can@2751000 { 1511 compatible = "bosch,m_can"; 1512 reg = <0x00 0x02751000 0x00 0x200>, 1513 <0x00 0x02758000 0x00 0x8000>; 1514 reg-names = "m_can", "message_ram"; 1515 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 1516 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; 1517 clock-names = "hclk", "cclk"; 1518 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1520 interrupt-names = "int0", "int1"; 1521 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1522 status = "disabled"; 1523 }; 1524 1525 main_mcan6: can@2761000 { 1526 compatible = "bosch,m_can"; 1527 reg = <0x00 0x02761000 0x00 0x200>, 1528 <0x00 0x02768000 0x00 0x8000>; 1529 reg-names = "m_can", "message_ram"; 1530 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1531 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; 1532 clock-names = "hclk", "cclk"; 1533 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1535 interrupt-names = "int0", "int1"; 1536 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1537 status = "disabled"; 1538 }; 1539 1540 main_mcan7: can@2771000 { 1541 compatible = "bosch,m_can"; 1542 reg = <0x00 0x02771000 0x00 0x200>, 1543 <0x00 0x02778000 0x00 0x8000>; 1544 reg-names = "m_can", "message_ram"; 1545 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1546 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; 1547 clock-names = "hclk", "cclk"; 1548 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1550 interrupt-names = "int0", "int1"; 1551 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1552 status = "disabled"; 1553 }; 1554 1555 main_mcan8: can@2781000 { 1556 compatible = "bosch,m_can"; 1557 reg = <0x00 0x02781000 0x00 0x200>, 1558 <0x00 0x02788000 0x00 0x8000>; 1559 reg-names = "m_can", "message_ram"; 1560 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1561 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; 1562 clock-names = "hclk", "cclk"; 1563 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1565 interrupt-names = "int0", "int1"; 1566 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1567 status = "disabled"; 1568 }; 1569 1570 main_mcan9: can@2791000 { 1571 compatible = "bosch,m_can"; 1572 reg = <0x00 0x02791000 0x00 0x200>, 1573 <0x00 0x02798000 0x00 0x8000>; 1574 reg-names = "m_can", "message_ram"; 1575 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1576 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; 1577 clock-names = "hclk", "cclk"; 1578 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1580 interrupt-names = "int0", "int1"; 1581 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1582 status = "disabled"; 1583 }; 1584 1585 main_mcan10: can@27a1000 { 1586 compatible = "bosch,m_can"; 1587 reg = <0x00 0x027a1000 0x00 0x200>, 1588 <0x00 0x027a8000 0x00 0x8000>; 1589 reg-names = "m_can", "message_ram"; 1590 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1591 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; 1592 clock-names = "hclk", "cclk"; 1593 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1595 interrupt-names = "int0", "int1"; 1596 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1597 status = "disabled"; 1598 }; 1599 1600 main_mcan11: can@27b1000 { 1601 compatible = "bosch,m_can"; 1602 reg = <0x00 0x027b1000 0x00 0x200>, 1603 <0x00 0x027b8000 0x00 0x8000>; 1604 reg-names = "m_can", "message_ram"; 1605 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1606 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; 1607 clock-names = "hclk", "cclk"; 1608 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1610 interrupt-names = "int0", "int1"; 1611 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1612 status = "disabled"; 1613 }; 1614 1615 main_mcan12: can@27c1000 { 1616 compatible = "bosch,m_can"; 1617 reg = <0x00 0x027c1000 0x00 0x200>, 1618 <0x00 0x027c8000 0x00 0x8000>; 1619 reg-names = "m_can", "message_ram"; 1620 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 1621 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; 1622 clock-names = "hclk", "cclk"; 1623 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1625 interrupt-names = "int0", "int1"; 1626 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1627 status = "disabled"; 1628 }; 1629 1630 main_mcan13: can@27d1000 { 1631 compatible = "bosch,m_can"; 1632 reg = <0x00 0x027d1000 0x00 0x200>, 1633 <0x00 0x027d8000 0x00 0x8000>; 1634 reg-names = "m_can", "message_ram"; 1635 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 1636 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; 1637 clock-names = "hclk", "cclk"; 1638 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1640 interrupt-names = "int0", "int1"; 1641 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1642 status = "disabled"; 1643 }; 1644 1645 main_mcan14: can@2681000 { 1646 compatible = "bosch,m_can"; 1647 reg = <0x00 0x02681000 0x00 0x200>, 1648 <0x00 0x02688000 0x00 0x8000>; 1649 reg-names = "m_can", "message_ram"; 1650 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; 1651 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; 1652 clock-names = "hclk", "cclk"; 1653 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1655 interrupt-names = "int0", "int1"; 1656 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1657 status = "disabled"; 1658 }; 1659 1660 main_mcan15: can@2691000 { 1661 compatible = "bosch,m_can"; 1662 reg = <0x00 0x02691000 0x00 0x200>, 1663 <0x00 0x02698000 0x00 0x8000>; 1664 reg-names = "m_can", "message_ram"; 1665 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; 1666 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; 1667 clock-names = "hclk", "cclk"; 1668 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1670 interrupt-names = "int0", "int1"; 1671 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1672 status = "disabled"; 1673 }; 1674 1675 main_mcan16: can@26a1000 { 1676 compatible = "bosch,m_can"; 1677 reg = <0x00 0x026a1000 0x00 0x200>, 1678 <0x00 0x026a8000 0x00 0x8000>; 1679 reg-names = "m_can", "message_ram"; 1680 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1681 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; 1682 clock-names = "hclk", "cclk"; 1683 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1685 interrupt-names = "int0", "int1"; 1686 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1687 status = "disabled"; 1688 }; 1689 1690 main_mcan17: can@26b1000 { 1691 compatible = "bosch,m_can"; 1692 reg = <0x00 0x026b1000 0x00 0x200>, 1693 <0x00 0x026b8000 0x00 0x8000>; 1694 reg-names = "m_can", "message_ram"; 1695 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; 1696 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; 1697 clock-names = "hclk", "cclk"; 1698 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1700 interrupt-names = "int0", "int1"; 1701 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1702 status = "disabled"; 1703 }; 1704 1705 main_spi0: spi@2100000 { 1706 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1707 reg = <0x00 0x02100000 0x00 0x400>; 1708 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 1712 clocks = <&k3_clks 339 2>; 1713 status = "disabled"; 1714 }; 1715 1716 main_spi1: spi@2110000 { 1717 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1718 reg = <0x00 0x02110000 0x00 0x400>; 1719 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 1723 clocks = <&k3_clks 340 2>; 1724 status = "disabled"; 1725 }; 1726 1727 main_spi2: spi@2120000 { 1728 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1729 reg = <0x00 0x02120000 0x00 0x400>; 1730 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 1734 clocks = <&k3_clks 341 2>; 1735 status = "disabled"; 1736 }; 1737 1738 main_spi3: spi@2130000 { 1739 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1740 reg = <0x00 0x02130000 0x00 0x400>; 1741 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 1745 clocks = <&k3_clks 342 2>; 1746 status = "disabled"; 1747 }; 1748 1749 main_spi4: spi@2140000 { 1750 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1751 reg = <0x00 0x02140000 0x00 0x400>; 1752 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1753 #address-cells = <1>; 1754 #size-cells = <0>; 1755 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 1756 clocks = <&k3_clks 343 2>; 1757 status = "disabled"; 1758 }; 1759 1760 main_spi5: spi@2150000 { 1761 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1762 reg = <0x00 0x02150000 0x00 0x400>; 1763 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 1767 clocks = <&k3_clks 344 2>; 1768 status = "disabled"; 1769 }; 1770 1771 main_spi6: spi@2160000 { 1772 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1773 reg = <0x00 0x02160000 0x00 0x400>; 1774 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 1778 clocks = <&k3_clks 345 2>; 1779 status = "disabled"; 1780 }; 1781 1782 main_spi7: spi@2170000 { 1783 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1784 reg = <0x00 0x02170000 0x00 0x400>; 1785 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 1789 clocks = <&k3_clks 346 2>; 1790 status = "disabled"; 1791 }; 1792 1793 dss: dss@4a00000 { 1794 compatible = "ti,j721e-dss"; 1795 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1796 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1797 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1798 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1799 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1800 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1801 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1802 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1803 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1804 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1805 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1806 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1807 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1808 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1809 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1810 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1811 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1812 reg-names = "common_m", "common_s0", 1813 "common_s1", "common_s2", 1814 "vidl1", "vidl2","vid1","vid2", 1815 "ovr1", "ovr2", "ovr3", "ovr4", 1816 "vp1", "vp2", "vp3", "vp4", 1817 "wb"; 1818 clocks = <&k3_clks 158 0>, 1819 <&k3_clks 158 2>, 1820 <&k3_clks 158 5>, 1821 <&k3_clks 158 14>, 1822 <&k3_clks 158 18>; 1823 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1824 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 1825 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1829 interrupt-names = "common_m", 1830 "common_s0", 1831 "common_s1", 1832 "common_s2"; 1833 status = "disabled"; 1834 1835 dss_ports: ports { 1836 }; 1837 }; 1838 1839 main_r5fss0: r5fss@5c00000 { 1840 compatible = "ti,j721s2-r5fss"; 1841 ti,cluster-mode = <1>; 1842 #address-cells = <1>; 1843 #size-cells = <1>; 1844 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1845 <0x5d00000 0x00 0x5d00000 0x20000>; 1846 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1847 1848 main_r5fss0_core0: r5f@5c00000 { 1849 compatible = "ti,j721s2-r5f"; 1850 reg = <0x5c00000 0x00010000>, 1851 <0x5c10000 0x00010000>; 1852 reg-names = "atcm", "btcm"; 1853 ti,sci = <&sms>; 1854 ti,sci-dev-id = <279>; 1855 ti,sci-proc-ids = <0x06 0xff>; 1856 resets = <&k3_reset 279 1>; 1857 firmware-name = "j721s2-main-r5f0_0-fw"; 1858 ti,atcm-enable = <1>; 1859 ti,btcm-enable = <1>; 1860 ti,loczrama = <1>; 1861 }; 1862 1863 main_r5fss0_core1: r5f@5d00000 { 1864 compatible = "ti,j721s2-r5f"; 1865 reg = <0x5d00000 0x00010000>, 1866 <0x5d10000 0x00010000>; 1867 reg-names = "atcm", "btcm"; 1868 ti,sci = <&sms>; 1869 ti,sci-dev-id = <280>; 1870 ti,sci-proc-ids = <0x07 0xff>; 1871 resets = <&k3_reset 280 1>; 1872 firmware-name = "j721s2-main-r5f0_1-fw"; 1873 ti,atcm-enable = <1>; 1874 ti,btcm-enable = <1>; 1875 ti,loczrama = <1>; 1876 }; 1877 }; 1878 1879 main_r5fss1: r5fss@5e00000 { 1880 compatible = "ti,j721s2-r5fss"; 1881 ti,cluster-mode = <1>; 1882 #address-cells = <1>; 1883 #size-cells = <1>; 1884 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1885 <0x5f00000 0x00 0x5f00000 0x20000>; 1886 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1887 1888 main_r5fss1_core0: r5f@5e00000 { 1889 compatible = "ti,j721s2-r5f"; 1890 reg = <0x5e00000 0x00010000>, 1891 <0x5e10000 0x00010000>; 1892 reg-names = "atcm", "btcm"; 1893 ti,sci = <&sms>; 1894 ti,sci-dev-id = <281>; 1895 ti,sci-proc-ids = <0x08 0xff>; 1896 resets = <&k3_reset 281 1>; 1897 firmware-name = "j721s2-main-r5f1_0-fw"; 1898 ti,atcm-enable = <1>; 1899 ti,btcm-enable = <1>; 1900 ti,loczrama = <1>; 1901 }; 1902 1903 main_r5fss1_core1: r5f@5f00000 { 1904 compatible = "ti,j721s2-r5f"; 1905 reg = <0x5f00000 0x00010000>, 1906 <0x5f10000 0x00010000>; 1907 reg-names = "atcm", "btcm"; 1908 ti,sci = <&sms>; 1909 ti,sci-dev-id = <282>; 1910 ti,sci-proc-ids = <0x09 0xff>; 1911 resets = <&k3_reset 282 1>; 1912 firmware-name = "j721s2-main-r5f1_1-fw"; 1913 ti,atcm-enable = <1>; 1914 ti,btcm-enable = <1>; 1915 ti,loczrama = <1>; 1916 }; 1917 }; 1918 1919 c71_0: dsp@64800000 { 1920 compatible = "ti,j721s2-c71-dsp"; 1921 reg = <0x00 0x64800000 0x00 0x00080000>, 1922 <0x00 0x64e00000 0x00 0x0000c000>; 1923 reg-names = "l2sram", "l1dram"; 1924 ti,sci = <&sms>; 1925 ti,sci-dev-id = <8>; 1926 ti,sci-proc-ids = <0x30 0xff>; 1927 resets = <&k3_reset 8 1>; 1928 firmware-name = "j721s2-c71_0-fw"; 1929 status = "disabled"; 1930 }; 1931 1932 c71_1: dsp@65800000 { 1933 compatible = "ti,j721s2-c71-dsp"; 1934 reg = <0x00 0x65800000 0x00 0x00080000>, 1935 <0x00 0x65e00000 0x00 0x0000c000>; 1936 reg-names = "l2sram", "l1dram"; 1937 ti,sci = <&sms>; 1938 ti,sci-dev-id = <11>; 1939 ti,sci-proc-ids = <0x31 0xff>; 1940 resets = <&k3_reset 11 1>; 1941 firmware-name = "j721s2-c71_1-fw"; 1942 status = "disabled"; 1943 }; 1944 1945 main_esm: esm@700000 { 1946 compatible = "ti,j721e-esm"; 1947 reg = <0x00 0x700000 0x00 0x1000>; 1948 ti,esm-pins = <688>, <689>; 1949 bootph-pre-ram; 1950 }; 1951 1952 watchdog0: watchdog@2200000 { 1953 compatible = "ti,j7-rti-wdt"; 1954 reg = <0x00 0x2200000 0x00 0x100>; 1955 clocks = <&k3_clks 286 1>; 1956 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1957 assigned-clocks = <&k3_clks 286 1>; 1958 assigned-clock-parents = <&k3_clks 286 5>; 1959 }; 1960 1961 watchdog1: watchdog@2210000 { 1962 compatible = "ti,j7-rti-wdt"; 1963 reg = <0x00 0x2210000 0x00 0x100>; 1964 clocks = <&k3_clks 287 1>; 1965 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 1966 assigned-clocks = <&k3_clks 287 1>; 1967 assigned-clock-parents = <&k3_clks 287 5>; 1968 }; 1969 1970 /* 1971 * The following RTI instances are coupled with MCU R5Fs, c7x and 1972 * GPU so keeping them reserved as these will be used by their 1973 * respective firmware 1974 */ 1975 watchdog2: watchdog@22f0000 { 1976 compatible = "ti,j7-rti-wdt"; 1977 reg = <0x00 0x22f0000 0x00 0x100>; 1978 clocks = <&k3_clks 290 1>; 1979 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; 1980 assigned-clocks = <&k3_clks 290 1>; 1981 assigned-clock-parents = <&k3_clks 290 5>; 1982 /* reserved for GPU */ 1983 status = "reserved"; 1984 }; 1985 1986 watchdog3: watchdog@2300000 { 1987 compatible = "ti,j7-rti-wdt"; 1988 reg = <0x00 0x2300000 0x00 0x100>; 1989 clocks = <&k3_clks 288 1>; 1990 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1991 assigned-clocks = <&k3_clks 288 1>; 1992 assigned-clock-parents = <&k3_clks 288 5>; 1993 /* reserved for C7X_0 */ 1994 status = "reserved"; 1995 }; 1996 1997 watchdog4: watchdog@2310000 { 1998 compatible = "ti,j7-rti-wdt"; 1999 reg = <0x00 0x2310000 0x00 0x100>; 2000 clocks = <&k3_clks 289 1>; 2001 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 2002 assigned-clocks = <&k3_clks 289 1>; 2003 assigned-clock-parents = <&k3_clks 289 5>; 2004 /* reserved for C7X_1 */ 2005 status = "reserved"; 2006 }; 2007 2008 watchdog5: watchdog@23c0000 { 2009 compatible = "ti,j7-rti-wdt"; 2010 reg = <0x00 0x23c0000 0x00 0x100>; 2011 clocks = <&k3_clks 291 1>; 2012 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; 2013 assigned-clocks = <&k3_clks 291 1>; 2014 assigned-clock-parents = <&k3_clks 291 5>; 2015 /* reserved for MAIN_R5F0_0 */ 2016 status = "reserved"; 2017 }; 2018 2019 watchdog6: watchdog@23d0000 { 2020 compatible = "ti,j7-rti-wdt"; 2021 reg = <0x00 0x23d0000 0x00 0x100>; 2022 clocks = <&k3_clks 292 1>; 2023 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 2024 assigned-clocks = <&k3_clks 292 1>; 2025 assigned-clock-parents = <&k3_clks 292 5>; 2026 /* reserved for MAIN_R5F0_1 */ 2027 status = "reserved"; 2028 }; 2029 2030 watchdog7: watchdog@23e0000 { 2031 compatible = "ti,j7-rti-wdt"; 2032 reg = <0x00 0x23e0000 0x00 0x100>; 2033 clocks = <&k3_clks 293 1>; 2034 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 2035 assigned-clocks = <&k3_clks 293 1>; 2036 assigned-clock-parents = <&k3_clks 293 5>; 2037 /* reserved for MAIN_R5F1_0 */ 2038 status = "reserved"; 2039 }; 2040 2041 watchdog8: watchdog@23f0000 { 2042 compatible = "ti,j7-rti-wdt"; 2043 reg = <0x00 0x23f0000 0x00 0x100>; 2044 clocks = <&k3_clks 294 1>; 2045 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 2046 assigned-clocks = <&k3_clks 294 1>; 2047 assigned-clock-parents = <&k3_clks 294 5>; 2048 /* reserved for MAIN_R5F1_1 */ 2049 status = "reserved"; 2050 }; 2051}; 2052