1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721s2-som-p0.dtsi" 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-cadence.h> 13#include <dt-bindings/phy/phy.h> 14 15#include "k3-serdes.h" 16 17/ { 18 compatible = "ti,j721s2-evm", "ti,j721s2"; 19 model = "Texas Instruments J721S2 EVM"; 20 21 chosen { 22 stdout-path = "serial2:115200n8"; 23 }; 24 25 aliases { 26 serial1 = &mcu_uart0; 27 serial2 = &main_uart8; 28 mmc0 = &main_sdhci0; 29 mmc1 = &main_sdhci1; 30 can0 = &main_mcan16; 31 can1 = &mcu_mcan0; 32 can2 = &mcu_mcan1; 33 can3 = &main_mcan3; 34 can4 = &main_mcan5; 35 }; 36 37 evm_12v0: fixedregulator-evm12v0 { 38 /* main supply */ 39 compatible = "regulator-fixed"; 40 regulator-name = "evm_12v0"; 41 regulator-min-microvolt = <12000000>; 42 regulator-max-microvolt = <12000000>; 43 regulator-always-on; 44 regulator-boot-on; 45 }; 46 47 vsys_3v3: fixedregulator-vsys3v3 { 48 /* Output of LM5140 */ 49 compatible = "regulator-fixed"; 50 regulator-name = "vsys_3v3"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 vin-supply = <&evm_12v0>; 54 regulator-always-on; 55 regulator-boot-on; 56 }; 57 58 vsys_5v0: fixedregulator-vsys5v0 { 59 /* Output of LM5140 */ 60 compatible = "regulator-fixed"; 61 regulator-name = "vsys_5v0"; 62 regulator-min-microvolt = <5000000>; 63 regulator-max-microvolt = <5000000>; 64 vin-supply = <&evm_12v0>; 65 regulator-always-on; 66 regulator-boot-on; 67 }; 68 69 vdd_mmc1: fixedregulator-sd { 70 /* Output of TPS22918 */ 71 compatible = "regulator-fixed"; 72 regulator-name = "vdd_mmc1"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-boot-on; 76 enable-active-high; 77 vin-supply = <&vsys_3v3>; 78 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 79 }; 80 81 vdd_sd_dv: gpio-regulator-TLV71033 { 82 /* Output of TLV71033 */ 83 compatible = "regulator-gpio"; 84 regulator-name = "tlv71033"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&vdd_sd_dv_pins_default>; 87 regulator-min-microvolt = <1800000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-boot-on; 90 vin-supply = <&vsys_5v0>; 91 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 92 states = <1800000 0x0>, 93 <3300000 0x1>; 94 }; 95 96 transceiver1: can-phy1 { 97 compatible = "ti,tcan1043"; 98 #phy-cells = <0>; 99 max-bitrate = <5000000>; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 102 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; 103 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 104 }; 105 106 transceiver2: can-phy2 { 107 compatible = "ti,tcan1042"; 108 #phy-cells = <0>; 109 max-bitrate = <5000000>; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 112 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 113 }; 114 115 transceiver3: can-phy3 { 116 compatible = "ti,tcan1043"; 117 #phy-cells = <0>; 118 max-bitrate = <5000000>; 119 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; 120 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 121 mux-states = <&mux0 1>; 122 }; 123 124 transceiver4: can-phy4 { 125 compatible = "ti,tcan1042"; 126 #phy-cells = <0>; 127 max-bitrate = <5000000>; 128 standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; 129 mux-states = <&mux1 1>; 130 }; 131}; 132 133&main_pmx0 { 134 main_uart8_pins_default: main-uart8-default-pins { 135 pinctrl-single,pins = < 136 J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ 137 J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ 138 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ 139 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ 140 >; 141 }; 142 143 main_i2c3_pins_default: main-i2c3-default-pins { 144 pinctrl-single,pins = < 145 J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ 146 J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ 147 >; 148 }; 149 150 main_i2c5_pins_default: main-i2c5-default-pins { 151 pinctrl-single,pins = < 152 J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ 153 J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ 154 >; 155 }; 156 157 main_mmc1_pins_default: main-mmc1-default-pins { 158 pinctrl-single,pins = < 159 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ 160 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ 161 J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ 162 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ 163 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 164 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ 165 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ 166 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ 167 >; 168 }; 169 170 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 171 pinctrl-single,pins = < 172 J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ 173 >; 174 }; 175 176 main_usbss0_pins_default: main-usbss0-default-pins { 177 pinctrl-single,pins = < 178 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ 179 >; 180 }; 181 182 main_mcan3_pins_default: main-mcan3-default-pins { 183 pinctrl-single,pins = < 184 J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ 185 J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ 186 >; 187 }; 188 189 main_mcan5_pins_default: main-mcan5-default-pins { 190 pinctrl-single,pins = < 191 J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ 192 J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ 193 >; 194 }; 195}; 196 197&wkup_pmx2 { 198 wkup_uart0_pins_default: wkup-uart0-default-pins { 199 pinctrl-single,pins = < 200 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ 201 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ 202 >; 203 }; 204 205 mcu_uart0_pins_default: mcu-uart0-default-pins { 206 pinctrl-single,pins = < 207 J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ 208 J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ 209 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ 210 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ 211 >; 212 }; 213 214 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 215 pinctrl-single,pins = < 216 J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ 217 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ 218 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ 219 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ 220 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ 221 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ 222 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ 223 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ 224 J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ 225 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ 226 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ 227 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ 228 >; 229 }; 230 231 mcu_mdio_pins_default: mcu-mdio-default-pins { 232 pinctrl-single,pins = < 233 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ 234 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ 235 >; 236 }; 237 238 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 239 pinctrl-single,pins = < 240 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ 241 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ 242 >; 243 }; 244 245 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 246 pinctrl-single,pins = < 247 J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ 248 J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ 249 >; 250 }; 251 252 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 253 pinctrl-single,pins = < 254 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ 255 J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ 256 >; 257 }; 258 259 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 260 pinctrl-single,pins = < 261 J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ 262 >; 263 }; 264 265 mcu_adc0_pins_default: mcu-adc0-default-pins { 266 pinctrl-single,pins = < 267 J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ 268 J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ 269 J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ 270 J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ 271 J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ 272 J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ 273 J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ 274 J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ 275 >; 276 }; 277 278 mcu_adc1_pins_default: mcu-adc1-default-pins { 279 pinctrl-single,pins = < 280 J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ 281 J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ 282 J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ 283 J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ 284 J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ 285 J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ 286 J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ 287 J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ 288 >; 289 }; 290}; 291 292&wkup_pmx1 { 293 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 294 pinctrl-single,pins = < 295 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ 296 J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ 297 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ 298 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ 299 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ 300 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ 301 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ 302 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ 303 >; 304 }; 305}; 306 307&main_gpio0 { 308 status = "okay"; 309}; 310 311&wkup_gpio0 { 312 status = "okay"; 313}; 314 315&wkup_uart0 { 316 status = "reserved"; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&wkup_uart0_pins_default>; 319}; 320 321&mcu_uart0 { 322 status = "okay"; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&mcu_uart0_pins_default>; 325}; 326 327&main_uart8 { 328 status = "okay"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&main_uart8_pins_default>; 331 /* Shared with TFA on this platform */ 332 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; 333}; 334 335&main_i2c0 { 336 clock-frequency = <400000>; 337 338 exp1: gpio@20 { 339 compatible = "ti,tca6416"; 340 reg = <0x20>; 341 gpio-controller; 342 #gpio-cells = <2>; 343 gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", 344 "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", 345 "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", 346 "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", 347 "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; 348 }; 349 350 exp2: gpio@22 { 351 compatible = "ti,tca6424"; 352 reg = <0x22>; 353 gpio-controller; 354 #gpio-cells = <2>; 355 gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", 356 "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", 357 "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", 358 "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", 359 "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", 360 "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; 361 }; 362}; 363 364&main_i2c5 { 365 pinctrl-names = "default"; 366 pinctrl-0 = <&main_i2c5_pins_default>; 367 clock-frequency = <400000>; 368 status = "okay"; 369 370 exp5: gpio@20 { 371 compatible = "ti,tca6408"; 372 reg = <0x20>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", 376 "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", 377 "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", 378 "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; 379 }; 380}; 381 382&main_sdhci0 { 383 /* eMMC */ 384 status = "okay"; 385 non-removable; 386 ti,driver-strength-ohm = <50>; 387 disable-wp; 388}; 389 390&main_sdhci1 { 391 /* SD card */ 392 status = "okay"; 393 pinctrl-0 = <&main_mmc1_pins_default>; 394 pinctrl-names = "default"; 395 disable-wp; 396 vmmc-supply = <&vdd_mmc1>; 397 vqmmc-supply = <&vdd_sd_dv>; 398}; 399 400&mcu_cpsw { 401 pinctrl-names = "default"; 402 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 403}; 404 405&davinci_mdio { 406 phy0: ethernet-phy@0 { 407 reg = <0>; 408 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 409 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 410 ti,min-output-impedance; 411 }; 412}; 413 414&cpsw_port1 { 415 phy-mode = "rgmii-rxid"; 416 phy-handle = <&phy0>; 417}; 418 419&serdes_ln_ctrl { 420 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, 421 <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; 422}; 423 424&serdes_refclk { 425 clock-frequency = <100000000>; 426}; 427 428&serdes0 { 429 status = "okay"; 430 serdes0_pcie_link: phy@0 { 431 reg = <0>; 432 cdns,num-lanes = <1>; 433 #phy-cells = <0>; 434 cdns,phy-type = <PHY_TYPE_PCIE>; 435 resets = <&serdes_wiz0 1>; 436 }; 437}; 438 439&usb_serdes_mux { 440 idle-states = <1>; /* USB0 to SERDES lane 1 */ 441}; 442 443&usbss0 { 444 status = "okay"; 445 pinctrl-0 = <&main_usbss0_pins_default>; 446 pinctrl-names = "default"; 447 ti,vbus-divider; 448 ti,usb2-only; 449}; 450 451&usb0 { 452 dr_mode = "otg"; 453 maximum-speed = "high-speed"; 454}; 455 456&ospi1 { 457 status = "okay"; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 460 461 flash@0 { 462 compatible = "jedec,spi-nor"; 463 reg = <0x0>; 464 spi-tx-bus-width = <1>; 465 spi-rx-bus-width = <4>; 466 spi-max-frequency = <40000000>; 467 cdns,tshsl-ns = <60>; 468 cdns,tsd2d-ns = <60>; 469 cdns,tchsh-ns = <60>; 470 cdns,tslch-ns = <60>; 471 cdns,read-delay = <2>; 472 }; 473}; 474 475&pcie1_rc { 476 status = "okay"; 477 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 478 phys = <&serdes0_pcie_link>; 479 phy-names = "pcie-phy"; 480 num-lanes = <1>; 481}; 482 483&mcu_mcan0 { 484 status = "okay"; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&mcu_mcan0_pins_default>; 487 phys = <&transceiver1>; 488}; 489 490&mcu_mcan1 { 491 status = "okay"; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&mcu_mcan1_pins_default>; 494 phys = <&transceiver2>; 495}; 496 497&tscadc0 { 498 pinctrl-0 = <&mcu_adc0_pins_default>; 499 pinctrl-names = "default"; 500 status = "okay"; 501 adc { 502 ti,adc-channels = <0 1 2 3 4 5 6 7>; 503 }; 504}; 505 506&tscadc1 { 507 pinctrl-0 = <&mcu_adc1_pins_default>; 508 pinctrl-names = "default"; 509 status = "okay"; 510 adc { 511 ti,adc-channels = <0 1 2 3 4 5 6 7>; 512 }; 513}; 514 515&main_mcan3 { 516 status = "okay"; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&main_mcan3_pins_default>; 519 phys = <&transceiver3>; 520}; 521 522&main_mcan5 { 523 status = "okay"; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&main_mcan5_pins_default>; 526 phys = <&transceiver4>; 527}; 528