1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721s2-som-p0.dtsi" 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-cadence.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/mux/ti-serdes.h> 15 16/ { 17 compatible = "ti,j721s2-evm", "ti,j721s2"; 18 model = "Texas Instruments J721S2 EVM"; 19 20 chosen { 21 stdout-path = "serial2:115200n8"; 22 }; 23 24 aliases { 25 serial1 = &mcu_uart0; 26 serial2 = &main_uart8; 27 mmc0 = &main_sdhci0; 28 mmc1 = &main_sdhci1; 29 can0 = &main_mcan16; 30 can1 = &mcu_mcan0; 31 can2 = &mcu_mcan1; 32 }; 33 34 evm_12v0: fixedregulator-evm12v0 { 35 /* main supply */ 36 compatible = "regulator-fixed"; 37 regulator-name = "evm_12v0"; 38 regulator-min-microvolt = <12000000>; 39 regulator-max-microvolt = <12000000>; 40 regulator-always-on; 41 regulator-boot-on; 42 }; 43 44 vsys_3v3: fixedregulator-vsys3v3 { 45 /* Output of LM5140 */ 46 compatible = "regulator-fixed"; 47 regulator-name = "vsys_3v3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 vin-supply = <&evm_12v0>; 51 regulator-always-on; 52 regulator-boot-on; 53 }; 54 55 vsys_5v0: fixedregulator-vsys5v0 { 56 /* Output of LM5140 */ 57 compatible = "regulator-fixed"; 58 regulator-name = "vsys_5v0"; 59 regulator-min-microvolt = <5000000>; 60 regulator-max-microvolt = <5000000>; 61 vin-supply = <&evm_12v0>; 62 regulator-always-on; 63 regulator-boot-on; 64 }; 65 66 vdd_mmc1: fixedregulator-sd { 67 /* Output of TPS22918 */ 68 compatible = "regulator-fixed"; 69 regulator-name = "vdd_mmc1"; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 regulator-boot-on; 73 enable-active-high; 74 vin-supply = <&vsys_3v3>; 75 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 76 }; 77 78 vdd_sd_dv: gpio-regulator-TLV71033 { 79 /* Output of TLV71033 */ 80 compatible = "regulator-gpio"; 81 regulator-name = "tlv71033"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&vdd_sd_dv_pins_default>; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <3300000>; 86 regulator-boot-on; 87 vin-supply = <&vsys_5v0>; 88 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 89 states = <1800000 0x0>, 90 <3300000 0x1>; 91 }; 92 93 transceiver1: can-phy1 { 94 compatible = "ti,tcan1043"; 95 #phy-cells = <0>; 96 max-bitrate = <5000000>; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 99 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; 100 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 101 }; 102 103 transceiver2: can-phy2 { 104 compatible = "ti,tcan1042"; 105 #phy-cells = <0>; 106 max-bitrate = <5000000>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 109 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 110 }; 111 112}; 113 114&main_pmx0 { 115 main_uart8_pins_default: main-uart8-default-pins { 116 pinctrl-single,pins = < 117 J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ 118 J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ 119 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ 120 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ 121 >; 122 }; 123 124 main_i2c3_pins_default: main-i2c3-default-pins { 125 pinctrl-single,pins = < 126 J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ 127 J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ 128 >; 129 }; 130 131 main_mmc1_pins_default: main-mmc1-default-pins { 132 pinctrl-single,pins = < 133 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ 134 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ 135 J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ 136 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ 137 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 138 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ 139 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ 140 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ 141 >; 142 }; 143 144 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 145 pinctrl-single,pins = < 146 J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ 147 >; 148 }; 149 150 main_usbss0_pins_default: main-usbss0-default-pins { 151 pinctrl-single,pins = < 152 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ 153 >; 154 }; 155}; 156 157&wkup_pmx2 { 158 wkup_uart0_pins_default: wkup-uart0-default-pins { 159 pinctrl-single,pins = < 160 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 161 J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ 162 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ 163 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ 164 >; 165 }; 166 167 mcu_uart0_pins_default: mcu-uart0-default-pins { 168 pinctrl-single,pins = < 169 J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ 170 J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ 171 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ 172 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ 173 >; 174 }; 175 176 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 177 pinctrl-single,pins = < 178 J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ 179 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ 180 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ 181 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ 182 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ 183 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ 184 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ 185 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ 186 J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ 187 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ 188 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ 189 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ 190 >; 191 }; 192 193 mcu_mdio_pins_default: mcu-mdio-default-pins { 194 pinctrl-single,pins = < 195 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ 196 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ 197 >; 198 }; 199 200 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 201 pinctrl-single,pins = < 202 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ 203 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ 204 >; 205 }; 206 207 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 208 pinctrl-single,pins = < 209 J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ 210 J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ 211 >; 212 }; 213 214 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 215 pinctrl-single,pins = < 216 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ 217 J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ 218 >; 219 }; 220 221 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 222 pinctrl-single,pins = < 223 J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ 224 >; 225 }; 226 227 mcu_adc0_pins_default: mcu-adc0-default-pins { 228 pinctrl-single,pins = < 229 J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ 230 J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ 231 J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ 232 J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ 233 J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ 234 J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ 235 J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ 236 J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ 237 >; 238 }; 239 240 mcu_adc1_pins_default: mcu-adc1-default-pins { 241 pinctrl-single,pins = < 242 J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ 243 J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ 244 J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ 245 J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ 246 J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ 247 J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ 248 J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ 249 J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ 250 >; 251 }; 252 253 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 254 pinctrl-single,pins = < 255 J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ 256 J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ 257 J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ 258 J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ 259 J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ 260 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ 261 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ 262 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ 263 J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ 264 >; 265 }; 266}; 267 268&main_gpio2 { 269 status = "disabled"; 270}; 271 272&main_gpio4 { 273 status = "disabled"; 274}; 275 276&main_gpio6 { 277 status = "disabled"; 278}; 279 280&wkup_gpio1 { 281 status = "disabled"; 282}; 283 284&wkup_uart0 { 285 status = "reserved"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&wkup_uart0_pins_default>; 288}; 289 290&mcu_uart0 { 291 status = "okay"; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&mcu_uart0_pins_default>; 294}; 295 296&main_uart8 { 297 status = "okay"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&main_uart8_pins_default>; 300 /* Shared with TFA on this platform */ 301 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; 302}; 303 304&main_i2c0 { 305 clock-frequency = <400000>; 306 307 exp1: gpio@20 { 308 compatible = "ti,tca6416"; 309 reg = <0x20>; 310 gpio-controller; 311 #gpio-cells = <2>; 312 gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", 313 "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", 314 "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", 315 "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", 316 "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; 317 }; 318 319 exp2: gpio@22 { 320 compatible = "ti,tca6424"; 321 reg = <0x22>; 322 gpio-controller; 323 #gpio-cells = <2>; 324 gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", 325 "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", 326 "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", 327 "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", 328 "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", 329 "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; 330 }; 331}; 332 333&main_sdhci0 { 334 /* eMMC */ 335 non-removable; 336 ti,driver-strength-ohm = <50>; 337 disable-wp; 338}; 339 340&main_sdhci1 { 341 /* SD card */ 342 pinctrl-0 = <&main_mmc1_pins_default>; 343 pinctrl-names = "default"; 344 disable-wp; 345 vmmc-supply = <&vdd_mmc1>; 346 vqmmc-supply = <&vdd_sd_dv>; 347}; 348 349&mcu_cpsw { 350 pinctrl-names = "default"; 351 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 352}; 353 354&davinci_mdio { 355 phy0: ethernet-phy@0 { 356 reg = <0>; 357 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 358 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 359 ti,min-output-impedance; 360 }; 361}; 362 363&cpsw_port1 { 364 phy-mode = "rgmii-rxid"; 365 phy-handle = <&phy0>; 366}; 367 368&serdes_ln_ctrl { 369 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, 370 <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; 371}; 372 373&serdes_refclk { 374 clock-frequency = <100000000>; 375}; 376 377&serdes0 { 378 status = "okay"; 379 serdes0_pcie_link: phy@0 { 380 reg = <0>; 381 cdns,num-lanes = <1>; 382 #phy-cells = <0>; 383 cdns,phy-type = <PHY_TYPE_PCIE>; 384 resets = <&serdes_wiz0 1>; 385 }; 386}; 387 388&usb_serdes_mux { 389 idle-states = <1>; /* USB0 to SERDES lane 1 */ 390}; 391 392&usbss0 { 393 status = "okay"; 394 pinctrl-0 = <&main_usbss0_pins_default>; 395 pinctrl-names = "default"; 396 ti,vbus-divider; 397 ti,usb2-only; 398}; 399 400&usb0 { 401 dr_mode = "otg"; 402 maximum-speed = "high-speed"; 403}; 404 405&ospi1 { 406 status = "okay"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 409 410 flash@0{ 411 compatible = "jedec,spi-nor"; 412 reg = <0x0>; 413 spi-tx-bus-width = <1>; 414 spi-rx-bus-width = <4>; 415 spi-max-frequency = <40000000>; 416 cdns,tshsl-ns = <60>; 417 cdns,tsd2d-ns = <60>; 418 cdns,tchsh-ns = <60>; 419 cdns,tslch-ns = <60>; 420 cdns,read-delay = <2>; 421 }; 422}; 423 424&pcie1_rc { 425 status = "okay"; 426 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 427 phys = <&serdes0_pcie_link>; 428 phy-names = "pcie-phy"; 429 num-lanes = <1>; 430}; 431 432&mcu_mcan0 { 433 status = "okay"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&mcu_mcan0_pins_default>; 436 phys = <&transceiver1>; 437}; 438 439&mcu_mcan1 { 440 status = "okay"; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&mcu_mcan1_pins_default>; 443 phys = <&transceiver2>; 444}; 445 446&tscadc0 { 447 pinctrl-0 = <&mcu_adc0_pins_default>; 448 pinctrl-names = "default"; 449 status = "okay"; 450 adc { 451 ti,adc-channels = <0 1 2 3 4 5 6 7>; 452 }; 453}; 454 455&tscadc1 { 456 pinctrl-0 = <&mcu_adc1_pins_default>; 457 pinctrl-names = "default"; 458 status = "okay"; 459 adc { 460 ti,adc-channels = <0 1 2 3 4 5 6 7>; 461 }; 462}; 463