1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * Device Tree Source for enabling IPC using TI SDK firmware on J721E SoCs 4 * 5 * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&reserved_memory { 9 mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { 10 compatible = "shared-dma-pool"; 11 reg = <0x00 0xa1000000 0x00 0x100000>; 12 no-map; 13 }; 14 15 mcu_r5fss0_core1_memory_region: memory@a1100000 { 16 compatible = "shared-dma-pool"; 17 reg = <0x00 0xa1100000 0x00 0xf00000>; 18 no-map; 19 }; 20 21 main_r5fss0_core0_dma_memory_region: memory@a2000000 { 22 compatible = "shared-dma-pool"; 23 reg = <0x00 0xa2000000 0x00 0x100000>; 24 no-map; 25 }; 26 27 main_r5fss0_core0_memory_region: memory@a2100000 { 28 compatible = "shared-dma-pool"; 29 reg = <0x00 0xa2100000 0x00 0xf00000>; 30 no-map; 31 }; 32 33 main_r5fss0_core1_dma_memory_region: memory@a3000000 { 34 compatible = "shared-dma-pool"; 35 reg = <0x00 0xa3000000 0x00 0x100000>; 36 no-map; 37 }; 38 39 main_r5fss0_core1_memory_region: memory@a3100000 { 40 compatible = "shared-dma-pool"; 41 reg = <0x00 0xa3100000 0x00 0xf00000>; 42 no-map; 43 }; 44 45 main_r5fss1_core0_dma_memory_region: memory@a4000000 { 46 compatible = "shared-dma-pool"; 47 reg = <0x00 0xa4000000 0x00 0x100000>; 48 no-map; 49 }; 50 51 main_r5fss1_core0_memory_region: memory@a4100000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x00 0xa4100000 0x00 0xf00000>; 54 no-map; 55 }; 56 57 main_r5fss1_core1_dma_memory_region: memory@a5000000 { 58 compatible = "shared-dma-pool"; 59 reg = <0x00 0xa5000000 0x00 0x100000>; 60 no-map; 61 }; 62 63 main_r5fss1_core1_memory_region: memory@a5100000 { 64 compatible = "shared-dma-pool"; 65 reg = <0x00 0xa5100000 0x00 0xf00000>; 66 no-map; 67 }; 68 69 /* Carveout locations are flipped due to caching */ 70 c66_1_dma_memory_region: memory@a6000000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa6000000 0x00 0x100000>; 73 no-map; 74 }; 75 76 c66_0_memory_region: memory@a6100000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa6100000 0x00 0xf00000>; 79 no-map; 80 }; 81 82 /* Carveout locations are flipped due to caching */ 83 c66_0_dma_memory_region: memory@a7000000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa7000000 0x00 0x100000>; 86 no-map; 87 }; 88 89 c66_1_memory_region: memory@a7100000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x00 0xa7100000 0x00 0xf00000>; 92 no-map; 93 }; 94 95 c71_0_dma_memory_region: memory@a8000000 { 96 compatible = "shared-dma-pool"; 97 reg = <0x00 0xa8000000 0x00 0x100000>; 98 no-map; 99 }; 100 101 c71_0_memory_region: memory@a8100000 { 102 compatible = "shared-dma-pool"; 103 reg = <0x00 0xa8100000 0x00 0xf00000>; 104 no-map; 105 }; 106 107 rtos_ipc_memory_region: memory@aa000000 { 108 reg = <0x00 0xaa000000 0x00 0x01c00000>; 109 alignment = <0x1000>; 110 no-map; 111 }; 112}; 113 114&mailbox0_cluster0 { 115 status = "okay"; 116 interrupts = <436>; 117 118 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 119 ti,mbox-rx = <0 0 0>; 120 ti,mbox-tx = <1 0 0>; 121 }; 122 123 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 124 ti,mbox-rx = <2 0 0>; 125 ti,mbox-tx = <3 0 0>; 126 }; 127}; 128 129&mailbox0_cluster1 { 130 status = "okay"; 131 interrupts = <432>; 132 133 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 134 ti,mbox-rx = <0 0 0>; 135 ti,mbox-tx = <1 0 0>; 136 }; 137 138 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 139 ti,mbox-rx = <2 0 0>; 140 ti,mbox-tx = <3 0 0>; 141 }; 142}; 143 144&mailbox0_cluster2 { 145 status = "okay"; 146 interrupts = <428>; 147 148 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 149 ti,mbox-rx = <0 0 0>; 150 ti,mbox-tx = <1 0 0>; 151 }; 152 153 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 154 ti,mbox-rx = <2 0 0>; 155 ti,mbox-tx = <3 0 0>; 156 }; 157}; 158 159&mailbox0_cluster3 { 160 status = "okay"; 161 interrupts = <424>; 162 163 mbox_c66_0: mbox-c66-0 { 164 ti,mbox-rx = <0 0 0>; 165 ti,mbox-tx = <1 0 0>; 166 }; 167 168 mbox_c66_1: mbox-c66-1 { 169 ti,mbox-rx = <2 0 0>; 170 ti,mbox-tx = <3 0 0>; 171 }; 172}; 173 174&mailbox0_cluster4 { 175 status = "okay"; 176 interrupts = <420>; 177 178 mbox_c71_0: mbox-c71-0 { 179 ti,mbox-rx = <0 0 0>; 180 ti,mbox-tx = <1 0 0>; 181 }; 182}; 183 184/* Timers are used by Remoteproc firmware */ 185&main_timer0 { 186 status = "reserved"; 187}; 188 189&main_timer1 { 190 status = "reserved"; 191}; 192 193&main_timer2 { 194 status = "reserved"; 195}; 196 197&main_timer12 { 198 status = "reserved"; 199}; 200 201&main_timer13 { 202 status = "reserved"; 203}; 204 205&main_timer14 { 206 status = "reserved"; 207}; 208 209&main_timer15 { 210 status = "reserved"; 211}; 212 213&mcu_r5fss0 { 214 status = "okay"; 215}; 216 217&mcu_r5fss0_core0 { 218 status = "okay"; 219 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 220 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 221 <&mcu_r5fss0_core0_memory_region>; 222}; 223 224&mcu_r5fss0_core1 { 225 status = "okay"; 226 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 227 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 228 <&mcu_r5fss0_core1_memory_region>; 229}; 230 231&main_r5fss0 { 232 status = "okay"; 233 ti,cluster-mode = <0>; 234}; 235 236&main_r5fss0_core0 { 237 status = "okay"; 238 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 239 memory-region = <&main_r5fss0_core0_dma_memory_region>, 240 <&main_r5fss0_core0_memory_region>; 241}; 242 243&main_r5fss0_core1 { 244 status = "okay"; 245 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 246 memory-region = <&main_r5fss0_core1_dma_memory_region>, 247 <&main_r5fss0_core1_memory_region>; 248}; 249 250&main_r5fss1 { 251 status = "okay"; 252 ti,cluster-mode = <0>; 253}; 254 255&main_r5fss1_core0 { 256 status = "okay"; 257 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 258 memory-region = <&main_r5fss1_core0_dma_memory_region>, 259 <&main_r5fss1_core0_memory_region>; 260}; 261 262&main_r5fss1_core1 { 263 status = "okay"; 264 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 265 memory-region = <&main_r5fss1_core1_dma_memory_region>, 266 <&main_r5fss1_core1_memory_region>; 267}; 268 269&c66_0 { 270 status = "okay"; 271 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 272 memory-region = <&c66_0_dma_memory_region>, 273 <&c66_0_memory_region>; 274}; 275 276&c66_1 { 277 status = "okay"; 278 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 279 memory-region = <&c66_1_dma_memory_region>, 280 <&c66_1_memory_region>; 281}; 282 283&c71_0 { 284 status = "okay"; 285 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 286 memory-region = <&c71_0_dma_memory_region>, 287 <&c71_0_memory_region>; 288}; 289