1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Product Link: https://www.ti.com/tool/J721EXSOMXEVM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11 12/ { 13 memory@80000000 { 14 device_type = "memory"; 15 /* 4G RAM */ 16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 17 <0x00000008 0x80000000 0x00000000 0x80000000>; 18 }; 19 20 reserved_memory: reserved-memory { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 secure_ddr: optee@9e800000 { 26 reg = <0x00 0x9e800000 0x00 0x01800000>; 27 alignment = <0x1000>; 28 no-map; 29 }; 30 31 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 32 compatible = "shared-dma-pool"; 33 reg = <0x00 0xa0000000 0x00 0x100000>; 34 no-map; 35 }; 36 37 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 38 compatible = "shared-dma-pool"; 39 reg = <0x00 0xa0100000 0x00 0xf00000>; 40 no-map; 41 }; 42 43 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 44 compatible = "shared-dma-pool"; 45 reg = <0x00 0xa1000000 0x00 0x100000>; 46 no-map; 47 }; 48 49 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 50 compatible = "shared-dma-pool"; 51 reg = <0x00 0xa1100000 0x00 0xf00000>; 52 no-map; 53 }; 54 55 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa2000000 0x00 0x100000>; 58 no-map; 59 }; 60 61 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa2100000 0x00 0xf00000>; 64 no-map; 65 }; 66 67 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa3000000 0x00 0x100000>; 70 no-map; 71 }; 72 73 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa3100000 0x00 0xf00000>; 76 no-map; 77 }; 78 79 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa4000000 0x00 0x100000>; 82 no-map; 83 }; 84 85 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa4100000 0x00 0xf00000>; 88 no-map; 89 }; 90 91 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa5000000 0x00 0x100000>; 94 no-map; 95 }; 96 97 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa5100000 0x00 0xf00000>; 100 no-map; 101 }; 102 103 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa6000000 0x00 0x100000>; 106 no-map; 107 }; 108 109 c66_0_memory_region: c66-memory@a6100000 { 110 compatible = "shared-dma-pool"; 111 reg = <0x00 0xa6100000 0x00 0xf00000>; 112 no-map; 113 }; 114 115 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 116 compatible = "shared-dma-pool"; 117 reg = <0x00 0xa7000000 0x00 0x100000>; 118 no-map; 119 }; 120 121 c66_1_memory_region: c66-memory@a7100000 { 122 compatible = "shared-dma-pool"; 123 reg = <0x00 0xa7100000 0x00 0xf00000>; 124 no-map; 125 }; 126 127 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 128 compatible = "shared-dma-pool"; 129 reg = <0x00 0xa8000000 0x00 0x100000>; 130 no-map; 131 }; 132 133 c71_0_memory_region: c71-memory@a8100000 { 134 compatible = "shared-dma-pool"; 135 reg = <0x00 0xa8100000 0x00 0xf00000>; 136 no-map; 137 }; 138 139 rtos_ipc_memory_region: ipc-memories@aa000000 { 140 reg = <0x00 0xaa000000 0x00 0x01c00000>; 141 alignment = <0x1000>; 142 no-map; 143 }; 144 }; 145}; 146 147&wkup_pmx0 { 148 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 149 pinctrl-single,pins = < 150 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 151 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 152 >; 153 }; 154 155 pmic_irq_pins_default: pmic-irq-default-pins { 156 pinctrl-single,pins = < 157 J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */ 158 >; 159 }; 160 161 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 162 pinctrl-single,pins = < 163 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 164 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 165 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 166 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 167 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 168 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 169 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 170 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 171 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 172 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 173 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 174 >; 175 }; 176 177 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { 178 pinctrl-single,pins = < 179 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ 180 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ 181 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ 182 J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ 183 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ 184 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ 185 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ 186 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ 187 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ 188 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ 189 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ 190 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ 191 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ 192 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ 193 >; 194 }; 195}; 196 197&wkup_i2c0 { 198 status = "okay"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&wkup_i2c0_pins_default>; 201 clock-frequency = <400000>; 202 203 eeprom@50 { 204 /* CAV24C256WE-GT3 */ 205 compatible = "atmel,24c256"; 206 reg = <0x50>; 207 }; 208 209 tps659413: pmic@48 { 210 compatible = "ti,tps6594-q1"; 211 reg = <0x48>; 212 system-power-controller; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pmic_irq_pins_default>; 215 interrupt-parent = <&wkup_gpio0>; 216 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 217 gpio-controller; 218 #gpio-cells = <2>; 219 ti,primary-pmic; 220 buck12-supply = <&vsys_3v3>; 221 buck3-supply = <&vsys_3v3>; 222 buck4-supply = <&vsys_3v3>; 223 buck5-supply = <&vsys_3v3>; 224 ldo1-supply = <&vsys_3v3>; 225 ldo2-supply = <&vsys_3v3>; 226 ldo3-supply = <&vsys_3v3>; 227 ldo4-supply = <&vsys_3v3>; 228 229 regulators { 230 bucka12: buck12 { 231 regulator-name = "vdd_cpu_avs"; 232 regulator-min-microvolt = <600000>; 233 regulator-max-microvolt = <900000>; 234 regulator-boot-on; 235 regulator-always-on; 236 bootph-pre-ram; 237 }; 238 239 bucka3: buck3 { 240 regulator-name = "vdd_mcu_0v85"; 241 regulator-min-microvolt = <850000>; 242 regulator-max-microvolt = <850000>; 243 regulator-boot-on; 244 regulator-always-on; 245 }; 246 247 bucka4: buck4 { 248 regulator-name = "vdd_ddr_1v1"; 249 regulator-min-microvolt = <1100000>; 250 regulator-max-microvolt = <1100000>; 251 regulator-boot-on; 252 regulator-always-on; 253 }; 254 255 bucka5: buck5 { 256 regulator-name = "vdd_phyio_1v8"; 257 regulator-min-microvolt = <1800000>; 258 regulator-max-microvolt = <1800000>; 259 regulator-boot-on; 260 regulator-always-on; 261 }; 262 263 ldoa1: ldo1 { 264 regulator-name = "vdd1_lpddr4_1v8"; 265 regulator-min-microvolt = <1800000>; 266 regulator-max-microvolt = <1800000>; 267 regulator-boot-on; 268 regulator-always-on; 269 }; 270 271 ldoa2: ldo2 { 272 regulator-name = "vdd_mcuio_1v8"; 273 regulator-min-microvolt = <1800000>; 274 regulator-max-microvolt = <1800000>; 275 regulator-boot-on; 276 regulator-always-on; 277 }; 278 279 ldoa3: ldo3 { 280 regulator-name = "vdda_dll_0v8"; 281 regulator-min-microvolt = <800000>; 282 regulator-max-microvolt = <800000>; 283 regulator-boot-on; 284 regulator-always-on; 285 }; 286 287 ldoa4: ldo4 { 288 regulator-name = "vda_mcu_1v8"; 289 regulator-min-microvolt = <1800000>; 290 regulator-max-microvolt = <1800000>; 291 regulator-boot-on; 292 regulator-always-on; 293 }; 294 }; 295 }; 296 297 tps659411: pmic@4c { 298 compatible = "ti,tps6594-q1"; 299 reg = <0x4c>; 300 system-power-controller; 301 interrupt-parent = <&wkup_gpio0>; 302 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 303 gpio-controller; 304 #gpio-cells = <2>; 305 buck1234-supply = <&vsys_3v3>; 306 buck5-supply = <&vsys_3v3>; 307 ldo1-supply = <&vsys_3v3>; 308 ldo2-supply = <&vsys_3v3>; 309 ldo3-supply = <&vsys_3v3>; 310 ldo4-supply = <&vsys_3v3>; 311 312 regulators { 313 buckb1234: buck1234 { 314 regulator-name = "vdd_core_0v8"; 315 regulator-min-microvolt = <800000>; 316 regulator-max-microvolt = <800000>; 317 regulator-boot-on; 318 regulator-always-on; 319 }; 320 321 buckb5: buck5 { 322 regulator-name = "vdd_ram_0v85"; 323 regulator-min-microvolt = <850000>; 324 regulator-max-microvolt = <850000>; 325 regulator-boot-on; 326 regulator-always-on; 327 }; 328 329 ldob1: ldo1 { 330 regulator-name = "vdd_sd_dv"; 331 regulator-min-microvolt = <1800000>; 332 regulator-max-microvolt = <3300000>; 333 regulator-boot-on; 334 regulator-always-on; 335 }; 336 337 ldob2: ldo2 { 338 regulator-name = "vdd_usb_3v3"; 339 regulator-min-microvolt = <3300000>; 340 regulator-max-microvolt = <3300000>; 341 regulator-boot-on; 342 regulator-always-on; 343 }; 344 345 ldob3: ldo3 { 346 regulator-name = "vdd_io_1v8"; 347 regulator-min-microvolt = <1800000>; 348 regulator-max-microvolt = <1800000>; 349 regulator-boot-on; 350 regulator-always-on; 351 }; 352 353 ldob4: ldo4 { 354 regulator-name = "vda_pll_1v8"; 355 regulator-min-microvolt = <1800000>; 356 regulator-max-microvolt = <1800000>; 357 regulator-boot-on; 358 regulator-always-on; 359 }; 360 }; 361 }; 362}; 363 364&ospi0 { 365 status = "okay"; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 368 369 flash@0 { 370 compatible = "jedec,spi-nor"; 371 reg = <0x0>; 372 spi-tx-bus-width = <8>; 373 spi-rx-bus-width = <8>; 374 spi-max-frequency = <25000000>; 375 cdns,tshsl-ns = <60>; 376 cdns,tsd2d-ns = <60>; 377 cdns,tchsh-ns = <60>; 378 cdns,tslch-ns = <60>; 379 cdns,read-delay = <0>; 380 381 partitions { 382 compatible = "fixed-partitions"; 383 #address-cells = <1>; 384 #size-cells = <1>; 385 386 partition@0 { 387 label = "ospi.tiboot3"; 388 reg = <0x0 0x80000>; 389 }; 390 391 partition@80000 { 392 label = "ospi.tispl"; 393 reg = <0x80000 0x200000>; 394 }; 395 396 partition@280000 { 397 label = "ospi.u-boot"; 398 reg = <0x280000 0x400000>; 399 }; 400 401 partition@680000 { 402 label = "ospi.env"; 403 reg = <0x680000 0x20000>; 404 }; 405 406 partition@6a0000 { 407 label = "ospi.env.backup"; 408 reg = <0x6a0000 0x20000>; 409 }; 410 411 partition@6c0000 { 412 label = "ospi.sysfw"; 413 reg = <0x6c0000 0x100000>; 414 }; 415 416 partition@800000 { 417 label = "ospi.rootfs"; 418 reg = <0x800000 0x37c0000>; 419 }; 420 421 partition@3fe0000 { 422 label = "ospi.phypattern"; 423 reg = <0x3fe0000 0x20000>; 424 }; 425 }; 426 }; 427}; 428 429&hbmc { 430 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 431 * appropriate node based on board detection 432 */ 433 status = "disabled"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 436 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 437 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 438 439 flash@0,0 { 440 compatible = "cypress,hyperflash", "cfi-flash"; 441 reg = <0x00 0x00 0x4000000>; 442 443 partitions { 444 compatible = "fixed-partitions"; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 448 partition@0 { 449 label = "hbmc.tiboot3"; 450 reg = <0x0 0x80000>; 451 }; 452 453 partition@80000 { 454 label = "hbmc.tispl"; 455 reg = <0x80000 0x200000>; 456 }; 457 458 partition@280000 { 459 label = "hbmc.u-boot"; 460 reg = <0x280000 0x400000>; 461 }; 462 463 partition@680000 { 464 label = "hbmc.env"; 465 reg = <0x680000 0x40000>; 466 }; 467 468 partition@6c0000 { 469 label = "hbmc.sysfw"; 470 reg = <0x6c0000 0x100000>; 471 }; 472 473 partition@800000 { 474 label = "hbmc.rootfs"; 475 reg = <0x800000 0x3800000>; 476 }; 477 }; 478 }; 479}; 480 481&mailbox0_cluster0 { 482 status = "okay"; 483 interrupts = <436>; 484 485 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 486 ti,mbox-rx = <0 0 0>; 487 ti,mbox-tx = <1 0 0>; 488 }; 489 490 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 491 ti,mbox-rx = <2 0 0>; 492 ti,mbox-tx = <3 0 0>; 493 }; 494}; 495 496&mailbox0_cluster1 { 497 status = "okay"; 498 interrupts = <432>; 499 500 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 501 ti,mbox-rx = <0 0 0>; 502 ti,mbox-tx = <1 0 0>; 503 }; 504 505 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 506 ti,mbox-rx = <2 0 0>; 507 ti,mbox-tx = <3 0 0>; 508 }; 509}; 510 511&mailbox0_cluster2 { 512 status = "okay"; 513 interrupts = <428>; 514 515 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 516 ti,mbox-rx = <0 0 0>; 517 ti,mbox-tx = <1 0 0>; 518 }; 519 520 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 521 ti,mbox-rx = <2 0 0>; 522 ti,mbox-tx = <3 0 0>; 523 }; 524}; 525 526&mailbox0_cluster3 { 527 status = "okay"; 528 interrupts = <424>; 529 530 mbox_c66_0: mbox-c66-0 { 531 ti,mbox-rx = <0 0 0>; 532 ti,mbox-tx = <1 0 0>; 533 }; 534 535 mbox_c66_1: mbox-c66-1 { 536 ti,mbox-rx = <2 0 0>; 537 ti,mbox-tx = <3 0 0>; 538 }; 539}; 540 541&mailbox0_cluster4 { 542 status = "okay"; 543 interrupts = <420>; 544 545 mbox_c71_0: mbox-c71-0 { 546 ti,mbox-rx = <0 0 0>; 547 ti,mbox-tx = <1 0 0>; 548 }; 549}; 550 551&mcu_r5fss0_core0 { 552 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 553 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 554 <&mcu_r5fss0_core0_memory_region>; 555}; 556 557&mcu_r5fss0_core1 { 558 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 559 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 560 <&mcu_r5fss0_core1_memory_region>; 561}; 562 563&main_r5fss0_core0 { 564 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 565 memory-region = <&main_r5fss0_core0_dma_memory_region>, 566 <&main_r5fss0_core0_memory_region>; 567}; 568 569&main_r5fss0_core1 { 570 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 571 memory-region = <&main_r5fss0_core1_dma_memory_region>, 572 <&main_r5fss0_core1_memory_region>; 573}; 574 575&main_r5fss1_core0 { 576 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 577 memory-region = <&main_r5fss1_core0_dma_memory_region>, 578 <&main_r5fss1_core0_memory_region>; 579}; 580 581&main_r5fss1_core1 { 582 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 583 memory-region = <&main_r5fss1_core1_dma_memory_region>, 584 <&main_r5fss1_core1_memory_region>; 585}; 586 587&c66_0 { 588 status = "okay"; 589 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 590 memory-region = <&c66_0_dma_memory_region>, 591 <&c66_0_memory_region>; 592}; 593 594&c66_1 { 595 status = "okay"; 596 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 597 memory-region = <&c66_1_dma_memory_region>, 598 <&c66_1_memory_region>; 599}; 600 601&c71_0 { 602 status = "okay"; 603 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 604 memory-region = <&c71_0_dma_memory_region>, 605 <&c71_0_memory_region>; 606}; 607