1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 ethernet0 = &cpsw_port1; 25 mmc1 = &main_sdhci1; 26 }; 27 28 chosen { 29 stdout-path = "serial2:115200n8"; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 bootph-all; 35 /* 4G RAM */ 36 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 37 <0x00000008 0x80000000 0x00000000 0x80000000>; 38 }; 39 40 reserved_memory: reserved-memory { 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges; 44 45 secure_ddr: optee@9e800000 { 46 reg = <0x00 0x9e800000 0x00 0x01800000>; 47 alignment = <0x1000>; 48 no-map; 49 }; 50 51 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x00 0xa0000000 0x00 0x100000>; 54 no-map; 55 }; 56 57 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 58 compatible = "shared-dma-pool"; 59 reg = <0x00 0xa0100000 0x00 0xf00000>; 60 no-map; 61 }; 62 63 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 64 compatible = "shared-dma-pool"; 65 reg = <0x00 0xa1000000 0x00 0x100000>; 66 no-map; 67 }; 68 69 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 70 compatible = "shared-dma-pool"; 71 reg = <0x00 0xa1100000 0x00 0xf00000>; 72 no-map; 73 }; 74 75 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 76 compatible = "shared-dma-pool"; 77 reg = <0x00 0xa2000000 0x00 0x100000>; 78 no-map; 79 }; 80 81 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 82 compatible = "shared-dma-pool"; 83 reg = <0x00 0xa2100000 0x00 0xf00000>; 84 no-map; 85 }; 86 87 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 88 compatible = "shared-dma-pool"; 89 reg = <0x00 0xa3000000 0x00 0x100000>; 90 no-map; 91 }; 92 93 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 94 compatible = "shared-dma-pool"; 95 reg = <0x00 0xa3100000 0x00 0xf00000>; 96 no-map; 97 }; 98 99 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 100 compatible = "shared-dma-pool"; 101 reg = <0x00 0xa4000000 0x00 0x100000>; 102 no-map; 103 }; 104 105 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 106 compatible = "shared-dma-pool"; 107 reg = <0x00 0xa4100000 0x00 0xf00000>; 108 no-map; 109 }; 110 111 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 112 compatible = "shared-dma-pool"; 113 reg = <0x00 0xa5000000 0x00 0x100000>; 114 no-map; 115 }; 116 117 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 118 compatible = "shared-dma-pool"; 119 reg = <0x00 0xa5100000 0x00 0xf00000>; 120 no-map; 121 }; 122 123 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 124 compatible = "shared-dma-pool"; 125 reg = <0x00 0xa6000000 0x00 0x100000>; 126 no-map; 127 }; 128 129 c66_0_memory_region: c66-memory@a6100000 { 130 compatible = "shared-dma-pool"; 131 reg = <0x00 0xa6100000 0x00 0xf00000>; 132 no-map; 133 }; 134 135 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 136 compatible = "shared-dma-pool"; 137 reg = <0x00 0xa7000000 0x00 0x100000>; 138 no-map; 139 }; 140 141 c66_1_memory_region: c66-memory@a7100000 { 142 compatible = "shared-dma-pool"; 143 reg = <0x00 0xa7100000 0x00 0xf00000>; 144 no-map; 145 }; 146 147 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 148 compatible = "shared-dma-pool"; 149 reg = <0x00 0xa8000000 0x00 0x100000>; 150 no-map; 151 }; 152 153 c71_0_memory_region: c71-memory@a8100000 { 154 compatible = "shared-dma-pool"; 155 reg = <0x00 0xa8100000 0x00 0xf00000>; 156 no-map; 157 }; 158 159 rtos_ipc_memory_region: ipc-memories@aa000000 { 160 reg = <0x00 0xaa000000 0x00 0x01c00000>; 161 alignment = <0x1000>; 162 no-map; 163 }; 164 }; 165 166 vusb_main: fixedregulator-vusb-main5v0 { 167 /* USB MAIN INPUT 5V DC */ 168 compatible = "regulator-fixed"; 169 regulator-name = "vusb-main5v0"; 170 regulator-min-microvolt = <5000000>; 171 regulator-max-microvolt = <5000000>; 172 regulator-always-on; 173 regulator-boot-on; 174 }; 175 176 vsys_3v3: fixedregulator-vsys3v3 { 177 /* Output of LM5141 */ 178 compatible = "regulator-fixed"; 179 regulator-name = "vsys_3v3"; 180 regulator-min-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>; 182 vin-supply = <&vusb_main>; 183 regulator-always-on; 184 regulator-boot-on; 185 }; 186 187 vdd_mmc1: fixedregulator-sd { 188 compatible = "regulator-fixed"; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 191 regulator-name = "vdd_mmc1"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 regulator-boot-on; 195 enable-active-high; 196 vin-supply = <&vsys_3v3>; 197 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 198 }; 199 200 vdd_sd_dv_alt: gpio-regulator-tps659411 { 201 compatible = "regulator-gpio"; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 204 regulator-name = "tps659411"; 205 regulator-min-microvolt = <1800000>; 206 regulator-max-microvolt = <3300000>; 207 regulator-boot-on; 208 vin-supply = <&vsys_3v3>; 209 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 210 states = <1800000 0x0>, 211 <3300000 0x1>; 212 }; 213 214 transceiver1: can-phy1 { 215 compatible = "ti,tcan1042"; 216 #phy-cells = <0>; 217 max-bitrate = <5000000>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 220 standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>; 221 }; 222 223 transceiver2: can-phy2 { 224 compatible = "ti,tcan1042"; 225 #phy-cells = <0>; 226 max-bitrate = <5000000>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&main_mcan0_gpio_pins_default>; 229 standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>; 230 }; 231 232 transceiver3: can-phy3 { 233 compatible = "ti,tcan1042"; 234 #phy-cells = <0>; 235 max-bitrate = <5000000>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&main_mcan5_gpio_pins_default>; 238 standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>; 239 }; 240 241 transceiver4: can-phy4 { 242 compatible = "ti,tcan1042"; 243 #phy-cells = <0>; 244 max-bitrate = <5000000>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&main_mcan9_gpio_pins_default>; 247 standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>; 248 }; 249 250 dp_pwr_3v3: fixedregulator-dp-prw { 251 compatible = "regulator-fixed"; 252 regulator-name = "dp-pwr"; 253 regulator-min-microvolt = <3300000>; 254 regulator-max-microvolt = <3300000>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&dp_pwr_en_pins_default>; 257 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 258 enable-active-high; 259 }; 260 261 dp0: connector { 262 compatible = "dp-connector"; 263 label = "DP0"; 264 type = "full-size"; 265 dp-pwr-supply = <&dp_pwr_3v3>; 266 267 port { 268 dp_connector_in: endpoint { 269 remote-endpoint = <&dp0_out>; 270 }; 271 }; 272 }; 273 274 hdmi-connector { 275 compatible = "hdmi-connector"; 276 label = "hdmi"; 277 type = "a"; 278 279 pinctrl-names = "default"; 280 pinctrl-0 = <&hdmi_hpd_pins_default>; 281 282 ddc-i2c-bus = <&main_i2c1>; 283 284 /* HDMI_HPD */ 285 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; 286 287 port { 288 hdmi_connector_in: endpoint { 289 remote-endpoint = <&tfp410_out>; 290 }; 291 }; 292 }; 293 294 dvi-bridge { 295 compatible = "ti,tfp410"; 296 297 pinctrl-names = "default"; 298 pinctrl-0 = <&hdmi_pdn_pins_default>; 299 300 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; 301 ti,deskew = <0>; 302 303 ports { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 port@0 { 308 reg = <0>; 309 310 tfp410_in: endpoint { 311 remote-endpoint = <&dpi1_out>; 312 pclk-sample = <1>; 313 }; 314 }; 315 316 port@1 { 317 reg = <1>; 318 319 tfp410_out: endpoint { 320 remote-endpoint = 321 <&hdmi_connector_in>; 322 }; 323 }; 324 }; 325 }; 326 327 csi_mux: mux-controller { 328 compatible = "gpio-mux"; 329 #mux-state-cells = <1>; 330 mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; 331 idle-state = <0>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&main_csi_mux_sel_pins_default>; 334 }; 335}; 336 337&main_pmx0 { 338 main_mmc1_pins_default: main-mmc1-default-pins { 339 pinctrl-single,pins = < 340 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 341 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 342 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 343 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 344 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 345 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 346 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 347 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 348 >; 349 }; 350 351 main_uart0_pins_default: main-uart0-default-pins { 352 pinctrl-single,pins = < 353 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 354 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 355 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 356 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 357 >; 358 }; 359 360 main_uart1_pins_default: main-uart1-default-pins { 361 pinctrl-single,pins = < 362 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 363 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 364 >; 365 }; 366 367 main_i2c0_pins_default: main-i2c0-default-pins { 368 pinctrl-single,pins = < 369 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 370 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 371 >; 372 }; 373 374 main_i2c1_pins_default: main-i2c1-default-pins { 375 pinctrl-single,pins = < 376 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 377 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 378 >; 379 }; 380 381 main_i2c3_pins_default: main-i2c3-default-pins { 382 pinctrl-single,pins = < 383 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 384 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 385 >; 386 }; 387 388 main_usbss0_pins_default: main-usbss0-default-pins { 389 pinctrl-single,pins = < 390 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 391 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 392 >; 393 }; 394 395 main_usbss1_pins_default: main-usbss1-default-pins { 396 pinctrl-single,pins = < 397 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 398 >; 399 }; 400 401 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { 402 pinctrl-single,pins = < 403 J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ 404 >; 405 }; 406 407 main_mcan0_pins_default: main-mcan0-default-pins { 408 pinctrl-single,pins = < 409 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 410 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 411 >; 412 }; 413 414 main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins { 415 pinctrl-single,pins = < 416 J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */ 417 >; 418 }; 419 420 main_mcan5_pins_default: main-mcan5-default-pins { 421 pinctrl-single,pins = < 422 J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */ 423 J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */ 424 >; 425 }; 426 427 main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins { 428 pinctrl-single,pins = < 429 J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */ 430 >; 431 }; 432 433 main_mcan9_pins_default: main-mcan9-default-pins { 434 pinctrl-single,pins = < 435 J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */ 436 J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */ 437 >; 438 }; 439 440 main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins { 441 pinctrl-single,pins = < 442 J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */ 443 >; 444 }; 445 446 dp0_pins_default: dp0-default-pins { 447 pinctrl-single,pins = < 448 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 449 >; 450 }; 451 452 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 453 pinctrl-single,pins = < 454 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 455 >; 456 }; 457 458 dss_vout0_pins_default: dss-vout0-default-pins { 459 pinctrl-single,pins = < 460 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 461 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 462 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 463 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 464 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 465 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 466 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 467 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 468 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 469 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 470 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 471 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 472 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 473 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 474 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 475 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 476 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 477 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 478 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 479 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 480 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 481 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 482 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 483 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 484 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 485 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 486 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 487 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 488 >; 489 }; 490 491 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 492 pinctrl-single,pins = < 493 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ 494 >; 495 }; 496 497 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 498 pinctrl-single,pins = < 499 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 500 >; 501 }; 502 503 /* Reset for M.2 E Key slot on PCIe0 */ 504 ekey_reset_pins_default: ekey-reset-pns-default-pins { 505 pinctrl-single,pins = < 506 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 507 >; 508 }; 509 510 main_i2c5_pins_default: main-i2c5-default-pins { 511 pinctrl-single,pins = < 512 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 513 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 514 >; 515 }; 516 517 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 518 pinctrl-single,pins = < 519 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ 520 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ 521 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 522 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ 523 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 524 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 525 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 526 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ 527 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ 528 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ 529 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ 530 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ 531 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ 532 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ 533 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 534 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ 535 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 536 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ 537 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ 538 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ 539 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ 540 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ 541 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ 542 >; 543 }; 544 545 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { 546 pinctrl-single,pins = < 547 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ 548 >; 549 }; 550}; 551 552&wkup_pmx0 { 553 pmic_irq_pins_default: pmic-irq-default-pins { 554 pinctrl-single,pins = < 555 J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 556 >; 557 }; 558 559 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 560 pinctrl-single,pins = < 561 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 562 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 563 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 564 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 565 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 566 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 567 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 568 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 569 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 570 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 571 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 572 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 573 >; 574 }; 575 576 mcu_mdio_pins_default: mcu-mdio1-default-pins { 577 pinctrl-single,pins = < 578 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 579 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 580 >; 581 }; 582 583 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 584 pinctrl-single,pins = < 585 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 586 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 587 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 588 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 589 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 590 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 591 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 592 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 593 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 594 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 595 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 596 >; 597 }; 598 599 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { 600 pinctrl-single,pins = < 601 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 602 >; 603 }; 604 605 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 606 pinctrl-single,pins = < 607 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 608 >; 609 }; 610 611 wkup_uart0_pins_default: wkup-uart0-default-pins { 612 pinctrl-single,pins = < 613 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 614 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 615 >; 616 }; 617 618 mcu_uart0_pins_default: mcu-uart0-default-pins { 619 pinctrl-single,pins = < 620 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ 621 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ 622 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 623 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 624 >; 625 }; 626 627 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 628 pinctrl-single,pins = < 629 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 630 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 631 >; 632 }; 633 634 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 635 pinctrl-single,pins = < 636 J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 637 J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 638 >; 639 }; 640 641 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 642 pinctrl-single,pins = < 643 J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */ 644 >; 645 }; 646 647 /* Reset for M.2 M Key slot on PCIe1 */ 648 mkey_reset_pins_default: mkey-reset-pns-default-pins { 649 pinctrl-single,pins = < 650 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 651 >; 652 }; 653}; 654 655&wkup_uart0 { 656 /* Wakeup UART is used by System firmware */ 657 status = "reserved"; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&wkup_uart0_pins_default>; 660}; 661 662&wkup_i2c0 { 663 status = "okay"; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&wkup_i2c0_pins_default>; 666 clock-frequency = <400000>; 667 668 eeprom@51 { 669 /* AT24C512C-MAHM-T */ 670 compatible = "atmel,24c512"; 671 reg = <0x51>; 672 }; 673 674 tps659413: pmic@48 { 675 compatible = "ti,tps6594-q1"; 676 reg = <0x48>; 677 system-power-controller; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pmic_irq_pins_default>; 680 interrupt-parent = <&wkup_gpio0>; 681 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 682 gpio-controller; 683 #gpio-cells = <2>; 684 ti,primary-pmic; 685 buck123-supply = <&vsys_3v3>; 686 buck4-supply = <&vsys_3v3>; 687 buck5-supply = <&vsys_3v3>; 688 ldo1-supply = <&vsys_3v3>; 689 ldo2-supply = <&vsys_3v3>; 690 ldo3-supply = <&vsys_3v3>; 691 ldo4-supply = <&vsys_3v3>; 692 693 regulators { 694 bucka123: buck123 { 695 regulator-name = "vdd_cpu_avs"; 696 regulator-min-microvolt = <600000>; 697 regulator-max-microvolt = <900000>; 698 regulator-boot-on; 699 regulator-always-on; 700 bootph-pre-ram; 701 }; 702 703 bucka4: buck4 { 704 regulator-name = "vdd_mcu_0v85"; 705 regulator-min-microvolt = <850000>; 706 regulator-max-microvolt = <850000>; 707 regulator-boot-on; 708 regulator-always-on; 709 }; 710 711 bucka5: buck5 { 712 regulator-name = "vdd_phyio_1v8"; 713 regulator-min-microvolt = <1800000>; 714 regulator-max-microvolt = <1800000>; 715 regulator-boot-on; 716 regulator-always-on; 717 }; 718 719 ldoa1: ldo1 { 720 regulator-name = "vdd1_lpddr4_1v8"; 721 regulator-min-microvolt = <1800000>; 722 regulator-max-microvolt = <1800000>; 723 regulator-boot-on; 724 regulator-always-on; 725 }; 726 727 ldoa2: ldo2 { 728 regulator-name = "vdd_mcuio_1v8"; 729 regulator-min-microvolt = <1800000>; 730 regulator-max-microvolt = <1800000>; 731 regulator-boot-on; 732 regulator-always-on; 733 }; 734 735 ldoa3: ldo3 { 736 regulator-name = "vdda_dll_0v8"; 737 regulator-min-microvolt = <800000>; 738 regulator-max-microvolt = <800000>; 739 regulator-boot-on; 740 regulator-always-on; 741 }; 742 743 ldoa4: ldo4 { 744 regulator-name = "vda_mcu_1v8"; 745 regulator-min-microvolt = <1800000>; 746 regulator-max-microvolt = <1800000>; 747 regulator-boot-on; 748 regulator-always-on; 749 }; 750 }; 751 }; 752 753 tps659411: pmic@4c { 754 compatible = "ti,tps6594-q1"; 755 reg = <0x4c>; 756 system-power-controller; 757 interrupt-parent = <&wkup_gpio0>; 758 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 759 gpio-controller; 760 #gpio-cells = <2>; 761 buck1234-supply = <&vsys_3v3>; 762 buck5-supply = <&vsys_3v3>; 763 ldo1-supply = <&vsys_3v3>; 764 ldo2-supply = <&vsys_3v3>; 765 ldo3-supply = <&vsys_3v3>; 766 ldo4-supply = <&vsys_3v3>; 767 768 regulators { 769 buckb1234: buck1234 { 770 regulator-name = "vdd_core_0v8"; 771 regulator-min-microvolt = <800000>; 772 regulator-max-microvolt = <800000>; 773 regulator-boot-on; 774 regulator-always-on; 775 }; 776 777 buckb5: buck5 { 778 regulator-name = "vdd_ram_0v85"; 779 regulator-min-microvolt = <850000>; 780 regulator-max-microvolt = <850000>; 781 regulator-boot-on; 782 regulator-always-on; 783 }; 784 785 ldob1: ldo1 { 786 regulator-name = "vdd_sd_dv"; 787 regulator-min-microvolt = <1800000>; 788 regulator-max-microvolt = <3300000>; 789 regulator-boot-on; 790 regulator-always-on; 791 }; 792 793 ldob2: ldo2 { 794 regulator-name = "vdd_usb_3v3"; 795 regulator-min-microvolt = <3300000>; 796 regulator-max-microvolt = <3300000>; 797 regulator-boot-on; 798 regulator-always-on; 799 }; 800 801 ldob3: ldo3 { 802 regulator-name = "vdd_io_1v8"; 803 regulator-min-microvolt = <1800000>; 804 regulator-max-microvolt = <1800000>; 805 regulator-boot-on; 806 regulator-always-on; 807 }; 808 809 ldob4: ldo4 { 810 regulator-name = "vda_pll_1v8"; 811 regulator-min-microvolt = <1800000>; 812 regulator-max-microvolt = <1800000>; 813 regulator-boot-on; 814 regulator-always-on; 815 }; 816 }; 817 }; 818}; 819 820&mcu_uart0 { 821 status = "okay"; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&mcu_uart0_pins_default>; 824}; 825 826&main_uart0 { 827 status = "okay"; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&main_uart0_pins_default>; 830 /* Shared with ATF on this platform */ 831 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 832}; 833 834&main_uart1 { 835 status = "okay"; 836 pinctrl-names = "default"; 837 pinctrl-0 = <&main_uart1_pins_default>; 838}; 839 840&main_sdhci1 { 841 /* SD Card */ 842 status = "okay"; 843 vmmc-supply = <&vdd_mmc1>; 844 vqmmc-supply = <&vdd_sd_dv_alt>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&main_mmc1_pins_default>; 847 ti,driver-strength-ohm = <50>; 848 disable-wp; 849}; 850 851&ospi0 { 852 status = "okay"; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 855 856 flash@0 { 857 compatible = "jedec,spi-nor"; 858 reg = <0x0>; 859 spi-tx-bus-width = <8>; 860 spi-rx-bus-width = <8>; 861 spi-max-frequency = <25000000>; 862 cdns,tshsl-ns = <60>; 863 cdns,tsd2d-ns = <60>; 864 cdns,tchsh-ns = <60>; 865 cdns,tslch-ns = <60>; 866 cdns,read-delay = <4>; 867 868 partitions { 869 compatible = "fixed-partitions"; 870 #address-cells = <1>; 871 #size-cells = <1>; 872 873 partition@0 { 874 label = "ospi.tiboot3"; 875 reg = <0x0 0x80000>; 876 }; 877 878 partition@80000 { 879 label = "ospi.tispl"; 880 reg = <0x80000 0x200000>; 881 }; 882 883 partition@280000 { 884 label = "ospi.u-boot"; 885 reg = <0x280000 0x400000>; 886 }; 887 888 partition@680000 { 889 label = "ospi.env"; 890 reg = <0x680000 0x40000>; 891 }; 892 893 partition@6c0000 { 894 label = "ospi.sysfw"; 895 reg = <0x6c0000 0x100000>; 896 }; 897 898 partition@7c0000 { 899 label = "ospi.env.backup"; 900 reg = <0x7c0000 0x40000>; 901 }; 902 903 partition@800000 { 904 label = "ospi.rootfs"; 905 reg = <0x800000 0x37c0000>; 906 }; 907 908 partition@3fc0000 { 909 label = "ospi.phypattern"; 910 reg = <0x3fc0000 0x40000>; 911 }; 912 }; 913 }; 914}; 915 916&main_i2c0 { 917 status = "okay"; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&main_i2c0_pins_default>; 920 clock-frequency = <400000>; 921 922 i2c-mux@71 { 923 compatible = "nxp,pca9543"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 reg = <0x71>; 927 928 /* PCIe1 M.2 M Key I2C */ 929 i2c@0 { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 reg = <0>; 933 }; 934 935 /* PCIe0 M.2 E Key I2C */ 936 i2c@1 { 937 #address-cells = <1>; 938 #size-cells = <0>; 939 reg = <1>; 940 }; 941 }; 942}; 943 944&main_i2c1 { 945 status = "okay"; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&main_i2c1_pins_default>; 948 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 949 clock-frequency = <100000>; 950}; 951 952&main_i2c3 { 953 status = "okay"; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&main_i2c3_pins_default>; 956 clock-frequency = <400000>; 957 958 i2c-mux@70 { 959 compatible = "nxp,pca9543"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 reg = <0x70>; 963 964 /* CSI0 I2C */ 965 cam0_i2c: i2c@0 { 966 #address-cells = <1>; 967 #size-cells = <0>; 968 reg = <0>; 969 }; 970 971 /* CSI1 I2C */ 972 cam1_i2c: i2c@1 { 973 #address-cells = <1>; 974 #size-cells = <0>; 975 reg = <1>; 976 }; 977 }; 978}; 979 980&main_i2c5 { 981 /* Brought out on RPi Header */ 982 status = "okay"; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&main_i2c5_pins_default>; 985 clock-frequency = <400000>; 986}; 987 988&main_gpio0 { 989 status = "okay"; 990 pinctrl-names = "default"; 991 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 992}; 993 994&main_gpio1 { 995 status = "okay"; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&rpi_header_gpio1_pins_default>; 998}; 999 1000&wkup_gpio0 { 1001 status = "okay"; 1002}; 1003 1004&usb_serdes_mux { 1005 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 1006}; 1007 1008&serdes_ln_ctrl { 1009 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 1010 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 1011 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 1012 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 1013 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 1014 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 1015}; 1016 1017&serdes_wiz3 { 1018 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 1019 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 1020}; 1021 1022&serdes3 { 1023 serdes3_usb_link: phy@0 { 1024 reg = <0>; 1025 cdns,num-lanes = <2>; 1026 #phy-cells = <0>; 1027 cdns,phy-type = <PHY_TYPE_USB3>; 1028 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 1029 }; 1030}; 1031 1032&serdes4 { 1033 torrent_phy_dp: phy@0 { 1034 reg = <0>; 1035 resets = <&serdes_wiz4 1>; 1036 cdns,phy-type = <PHY_TYPE_DP>; 1037 cdns,num-lanes = <4>; 1038 cdns,max-bit-rate = <5400>; 1039 #phy-cells = <0>; 1040 }; 1041}; 1042 1043&mhdp { 1044 phys = <&torrent_phy_dp>; 1045 phy-names = "dpphy"; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&dp0_pins_default>; 1048}; 1049 1050&usbss0 { 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&main_usbss0_pins_default>; 1053 ti,vbus-divider; 1054}; 1055 1056&usb0 { 1057 dr_mode = "otg"; 1058 maximum-speed = "super-speed"; 1059 phys = <&serdes3_usb_link>; 1060 phy-names = "cdns3,usb3-phy"; 1061}; 1062 1063&serdes2 { 1064 serdes2_usb_link: phy@1 { 1065 reg = <1>; 1066 cdns,num-lanes = <1>; 1067 #phy-cells = <0>; 1068 cdns,phy-type = <PHY_TYPE_USB3>; 1069 resets = <&serdes_wiz2 2>; 1070 }; 1071}; 1072 1073&usbss1 { 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&main_usbss1_pins_default>; 1076 ti,vbus-divider; 1077}; 1078 1079&usb1 { 1080 dr_mode = "host"; 1081 maximum-speed = "super-speed"; 1082 phys = <&serdes2_usb_link>; 1083 phy-names = "cdns3,usb3-phy"; 1084}; 1085 1086&mcu_cpsw { 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 1089}; 1090 1091&davinci_mdio { 1092 phy0: ethernet-phy@0 { 1093 reg = <0>; 1094 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1095 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1096 }; 1097}; 1098 1099&cpsw_port1 { 1100 phy-mode = "rgmii-rxid"; 1101 phy-handle = <&phy0>; 1102}; 1103 1104&dss { 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&dss_vout0_pins_default>; 1107 1108 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 1109 <&k3_clks 152 4>, /* VP 2 pixel clock */ 1110 <&k3_clks 152 9>, /* VP 3 pixel clock */ 1111 <&k3_clks 152 13>; /* VP 4 pixel clock */ 1112 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 1113 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 1114 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 1115 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 1116}; 1117 1118&dss_ports { 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 1122 port@0 { 1123 reg = <0>; 1124 1125 dpi0_out: endpoint { 1126 remote-endpoint = <&dp0_in>; 1127 }; 1128 }; 1129 1130 port@1 { 1131 reg = <1>; 1132 1133 dpi1_out: endpoint { 1134 remote-endpoint = <&tfp410_in>; 1135 }; 1136 }; 1137}; 1138 1139&dp0_ports { 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 1143 port@0 { 1144 reg = <0>; 1145 dp0_in: endpoint { 1146 remote-endpoint = <&dpi0_out>; 1147 }; 1148 }; 1149 1150 port@4 { 1151 reg = <4>; 1152 dp0_out: endpoint { 1153 remote-endpoint = <&dp_connector_in>; 1154 }; 1155 }; 1156}; 1157 1158&serdes0 { 1159 serdes0_pcie_link: phy@0 { 1160 reg = <0>; 1161 cdns,num-lanes = <1>; 1162 #phy-cells = <0>; 1163 cdns,phy-type = <PHY_TYPE_PCIE>; 1164 resets = <&serdes_wiz0 1>; 1165 }; 1166}; 1167 1168&serdes1 { 1169 serdes1_pcie_link: phy@0 { 1170 reg = <0>; 1171 cdns,num-lanes = <2>; 1172 #phy-cells = <0>; 1173 cdns,phy-type = <PHY_TYPE_PCIE>; 1174 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 1175 }; 1176}; 1177 1178&pcie0_rc { 1179 status = "okay"; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&ekey_reset_pins_default>; 1182 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 1183 1184 phys = <&serdes0_pcie_link>; 1185 phy-names = "pcie-phy"; 1186 num-lanes = <1>; 1187}; 1188 1189&pcie1_rc { 1190 status = "okay"; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&mkey_reset_pins_default>; 1193 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 1194 1195 phys = <&serdes1_pcie_link>; 1196 phy-names = "pcie-phy"; 1197 num-lanes = <2>; 1198}; 1199 1200&mcu_mcan0 { 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&mcu_mcan0_pins_default>; 1203 phys = <&transceiver1>; 1204 status = "okay"; 1205}; 1206 1207&main_mcan0 { 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&main_mcan0_pins_default>; 1210 phys = <&transceiver2>; 1211 status = "okay"; 1212}; 1213 1214&main_mcan5 { 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&main_mcan5_pins_default>; 1217 phys = <&transceiver3>; 1218 status = "okay"; 1219}; 1220 1221&main_mcan9 { 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&main_mcan9_pins_default>; 1224 phys = <&transceiver4>; 1225 status = "okay"; 1226}; 1227 1228&ufs_wrapper { 1229 status = "disabled"; 1230}; 1231 1232&mailbox0_cluster0 { 1233 status = "okay"; 1234 interrupts = <436>; 1235 1236 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1237 ti,mbox-rx = <0 0 0>; 1238 ti,mbox-tx = <1 0 0>; 1239 }; 1240 1241 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1242 ti,mbox-rx = <2 0 0>; 1243 ti,mbox-tx = <3 0 0>; 1244 }; 1245}; 1246 1247&mailbox0_cluster1 { 1248 status = "okay"; 1249 interrupts = <432>; 1250 1251 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1252 ti,mbox-rx = <0 0 0>; 1253 ti,mbox-tx = <1 0 0>; 1254 }; 1255 1256 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1257 ti,mbox-rx = <2 0 0>; 1258 ti,mbox-tx = <3 0 0>; 1259 }; 1260}; 1261 1262&mailbox0_cluster2 { 1263 status = "okay"; 1264 interrupts = <428>; 1265 1266 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1267 ti,mbox-rx = <0 0 0>; 1268 ti,mbox-tx = <1 0 0>; 1269 }; 1270 1271 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1272 ti,mbox-rx = <2 0 0>; 1273 ti,mbox-tx = <3 0 0>; 1274 }; 1275}; 1276 1277&mailbox0_cluster3 { 1278 status = "okay"; 1279 interrupts = <424>; 1280 1281 mbox_c66_0: mbox-c66-0 { 1282 ti,mbox-rx = <0 0 0>; 1283 ti,mbox-tx = <1 0 0>; 1284 }; 1285 1286 mbox_c66_1: mbox-c66-1 { 1287 ti,mbox-rx = <2 0 0>; 1288 ti,mbox-tx = <3 0 0>; 1289 }; 1290}; 1291 1292&mailbox0_cluster4 { 1293 status = "okay"; 1294 interrupts = <420>; 1295 1296 mbox_c71_0: mbox-c71-0 { 1297 ti,mbox-rx = <0 0 0>; 1298 ti,mbox-tx = <1 0 0>; 1299 }; 1300}; 1301 1302&mcu_r5fss0_core0 { 1303 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1304 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1305 <&mcu_r5fss0_core0_memory_region>; 1306}; 1307 1308&mcu_r5fss0_core1 { 1309 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1310 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1311 <&mcu_r5fss0_core1_memory_region>; 1312}; 1313 1314&main_r5fss0_core0 { 1315 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1316 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1317 <&main_r5fss0_core0_memory_region>; 1318}; 1319 1320&main_r5fss0_core1 { 1321 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1322 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1323 <&main_r5fss0_core1_memory_region>; 1324}; 1325 1326&main_r5fss1_core0 { 1327 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1328 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1329 <&main_r5fss1_core0_memory_region>; 1330}; 1331 1332&main_r5fss1_core1 { 1333 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1334 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1335 <&main_r5fss1_core1_memory_region>; 1336}; 1337 1338&c66_0 { 1339 status = "okay"; 1340 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1341 memory-region = <&c66_0_dma_memory_region>, 1342 <&c66_0_memory_region>; 1343}; 1344 1345&c66_1 { 1346 status = "okay"; 1347 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 1348 memory-region = <&c66_1_dma_memory_region>, 1349 <&c66_1_memory_region>; 1350}; 1351 1352&c71_0 { 1353 status = "okay"; 1354 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1355 memory-region = <&c71_0_dma_memory_region>, 1356 <&c71_0_memory_region>; 1357}; 1358