1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 4G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 28 <0x00000008 0x80000000 0x00000000 0x80000000>; 29 }; 30 31 reserved_memory: reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa4000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa4100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 103 compatible = "shared-dma-pool"; 104 reg = <0x00 0xa5000000 0x00 0x100000>; 105 no-map; 106 }; 107 108 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00 0xa5100000 0x00 0xf00000>; 111 no-map; 112 }; 113 114 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 115 compatible = "shared-dma-pool"; 116 reg = <0x00 0xa6000000 0x00 0x100000>; 117 no-map; 118 }; 119 120 c66_0_memory_region: c66-memory@a6100000 { 121 compatible = "shared-dma-pool"; 122 reg = <0x00 0xa6100000 0x00 0xf00000>; 123 no-map; 124 }; 125 126 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 127 compatible = "shared-dma-pool"; 128 reg = <0x00 0xa7000000 0x00 0x100000>; 129 no-map; 130 }; 131 132 c66_1_memory_region: c66-memory@a7100000 { 133 compatible = "shared-dma-pool"; 134 reg = <0x00 0xa7100000 0x00 0xf00000>; 135 no-map; 136 }; 137 138 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 139 compatible = "shared-dma-pool"; 140 reg = <0x00 0xa8000000 0x00 0x100000>; 141 no-map; 142 }; 143 144 c71_0_memory_region: c71-memory@a8100000 { 145 compatible = "shared-dma-pool"; 146 reg = <0x00 0xa8100000 0x00 0xf00000>; 147 no-map; 148 }; 149 150 rtos_ipc_memory_region: ipc-memories@aa000000 { 151 reg = <0x00 0xaa000000 0x00 0x01c00000>; 152 alignment = <0x1000>; 153 no-map; 154 }; 155 }; 156 157 vusb_main: fixedregulator-vusb-main5v0 { 158 /* USB MAIN INPUT 5V DC */ 159 compatible = "regulator-fixed"; 160 regulator-name = "vusb-main5v0"; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 regulator-always-on; 164 regulator-boot-on; 165 }; 166 167 vsys_3v3: fixedregulator-vsys3v3 { 168 /* Output of LM5141 */ 169 compatible = "regulator-fixed"; 170 regulator-name = "vsys_3v3"; 171 regulator-min-microvolt = <3300000>; 172 regulator-max-microvolt = <3300000>; 173 vin-supply = <&vusb_main>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 vdd_mmc1: fixedregulator-sd { 179 compatible = "regulator-fixed"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 182 regulator-name = "vdd_mmc1"; 183 regulator-min-microvolt = <3300000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 enable-active-high; 187 vin-supply = <&vsys_3v3>; 188 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 189 }; 190 191 vdd_sd_dv_alt: gpio-regulator-tps659411 { 192 compatible = "regulator-gpio"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 195 regulator-name = "tps659411"; 196 regulator-min-microvolt = <1800000>; 197 regulator-max-microvolt = <3300000>; 198 regulator-boot-on; 199 vin-supply = <&vsys_3v3>; 200 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 201 states = <1800000 0x0>, 202 <3300000 0x1>; 203 }; 204 205 dp_pwr_3v3: fixedregulator-dp-prw { 206 compatible = "regulator-fixed"; 207 regulator-name = "dp-pwr"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&dp_pwr_en_pins_default>; 212 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 213 enable-active-high; 214 }; 215 216 dp0: connector { 217 compatible = "dp-connector"; 218 label = "DP0"; 219 type = "full-size"; 220 dp-pwr-supply = <&dp_pwr_3v3>; 221 222 port { 223 dp_connector_in: endpoint { 224 remote-endpoint = <&dp0_out>; 225 }; 226 }; 227 }; 228 229 hdmi-connector { 230 compatible = "hdmi-connector"; 231 label = "hdmi"; 232 type = "a"; 233 234 pinctrl-names = "default"; 235 pinctrl-0 = <&hdmi_hpd_pins_default>; 236 237 ddc-i2c-bus = <&main_i2c1>; 238 239 /* HDMI_HPD */ 240 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; 241 242 port { 243 hdmi_connector_in: endpoint { 244 remote-endpoint = <&tfp410_out>; 245 }; 246 }; 247 }; 248 249 dvi-bridge { 250 compatible = "ti,tfp410"; 251 252 pinctrl-names = "default"; 253 pinctrl-0 = <&hdmi_pdn_pins_default>; 254 255 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; 256 ti,deskew = <0>; 257 258 ports { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 262 port@0 { 263 reg = <0>; 264 265 tfp410_in: endpoint { 266 remote-endpoint = <&dpi1_out>; 267 pclk-sample = <1>; 268 }; 269 }; 270 271 port@1 { 272 reg = <1>; 273 274 tfp410_out: endpoint { 275 remote-endpoint = 276 <&hdmi_connector_in>; 277 }; 278 }; 279 }; 280 }; 281}; 282 283&main_pmx0 { 284 main_mmc1_pins_default: main-mmc1-pins-default { 285 pinctrl-single,pins = < 286 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 287 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 288 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 289 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 290 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 291 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 292 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 293 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 294 >; 295 }; 296 297 main_uart0_pins_default: main-uart0-pins-default { 298 pinctrl-single,pins = < 299 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 300 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 301 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 302 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 303 >; 304 }; 305 306 main_i2c0_pins_default: main-i2c0-pins-default { 307 pinctrl-single,pins = < 308 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 309 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 310 >; 311 }; 312 313 main_i2c1_pins_default: main-i2c1-pins-default { 314 pinctrl-single,pins = < 315 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 316 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 317 >; 318 }; 319 320 main_i2c3_pins_default: main-i2c3-pins-default { 321 pinctrl-single,pins = < 322 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 323 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 324 >; 325 }; 326 327 main_usbss0_pins_default: main-usbss0-pins-default { 328 pinctrl-single,pins = < 329 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 330 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 331 >; 332 }; 333 334 main_usbss1_pins_default: main-usbss1-pins-default { 335 pinctrl-single,pins = < 336 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 337 >; 338 }; 339 340 dp0_pins_default: dp0-pins-default { 341 pinctrl-single,pins = < 342 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 343 >; 344 }; 345 346 dp_pwr_en_pins_default: dp-pwr-en-pins-default { 347 pinctrl-single,pins = < 348 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 349 >; 350 }; 351 352 dss_vout0_pins_default: dss-vout0-pins-default { 353 pinctrl-single,pins = < 354 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 355 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 356 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 357 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 358 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 359 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 360 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 361 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 362 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 363 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 364 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 365 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 366 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 367 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 368 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 369 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 370 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 371 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 372 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 373 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 374 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 375 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 376 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 377 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 378 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 379 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 380 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 381 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 382 >; 383 }; 384 385 hdmi_hpd_pins_default: hdmi-hpd-pins-default { 386 pinctrl-single,pins = < 387 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ 388 >; 389 }; 390 391 hdmi_pdn_pins_default: hdmi-pdn-pins-default { 392 pinctrl-single,pins = < 393 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 394 >; 395 }; 396 397 /* Reset for M.2 E Key slot on PCIe0 */ 398 ekey_reset_pins_default: ekey-reset-pns-pins-default { 399 pinctrl-single,pins = < 400 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 401 >; 402 }; 403 404 main_i2c5_pins_default: main-i2c5-pins-default { 405 pinctrl-single,pins = < 406 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 407 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 408 >; 409 }; 410 411 rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { 412 pinctrl-single,pins = < 413 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ 414 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ 415 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 416 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ 417 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 418 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 419 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 420 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ 421 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ 422 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ 423 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ 424 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ 425 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ 426 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ 427 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 428 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ 429 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 430 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ 431 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ 432 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ 433 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ 434 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ 435 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ 436 >; 437 }; 438 439 rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { 440 pinctrl-single,pins = < 441 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ 442 >; 443 }; 444}; 445 446&wkup_pmx0 { 447 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 448 pinctrl-single,pins = < 449 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 450 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 451 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 452 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 453 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 454 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 455 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 456 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 457 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 458 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 459 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 460 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 461 >; 462 }; 463 464 mcu_mdio_pins_default: mcu-mdio1-pins-default { 465 pinctrl-single,pins = < 466 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 467 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 468 >; 469 }; 470 471 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 472 pinctrl-single,pins = < 473 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 474 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 475 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 476 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 477 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 478 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 479 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 480 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 481 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 482 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 483 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 484 >; 485 }; 486 487 vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { 488 pinctrl-single,pins = < 489 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 490 >; 491 }; 492 493 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 494 pinctrl-single,pins = < 495 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 496 >; 497 }; 498 499 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 500 pinctrl-single,pins = < 501 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 502 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 503 >; 504 }; 505 506 /* Reset for M.2 M Key slot on PCIe1 */ 507 mkey_reset_pins_default: mkey-reset-pns-pins-default { 508 pinctrl-single,pins = < 509 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 510 >; 511 }; 512}; 513 514&wkup_uart0 { 515 /* Wakeup UART is used by System firmware */ 516 status = "reserved"; 517}; 518 519&mcu_uart0 { 520 status = "okay"; 521 /* Default pinmux */ 522}; 523 524&main_uart0 { 525 status = "okay"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&main_uart0_pins_default>; 528 /* Shared with ATF on this platform */ 529 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 530}; 531 532&main_uart1 { 533 status = "okay"; 534 /* Default pinmux */ 535}; 536 537&main_sdhci0 { 538 /* Unused */ 539 status = "disabled"; 540}; 541 542&main_sdhci1 { 543 /* SD Card */ 544 vmmc-supply = <&vdd_mmc1>; 545 vqmmc-supply = <&vdd_sd_dv_alt>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&main_mmc1_pins_default>; 548 ti,driver-strength-ohm = <50>; 549 disable-wp; 550}; 551 552&main_sdhci2 { 553 /* Unused */ 554 status = "disabled"; 555}; 556 557&ospi0 { 558 pinctrl-names = "default"; 559 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 560 561 flash@0 { 562 compatible = "jedec,spi-nor"; 563 reg = <0x0>; 564 spi-tx-bus-width = <8>; 565 spi-rx-bus-width = <8>; 566 spi-max-frequency = <25000000>; 567 cdns,tshsl-ns = <60>; 568 cdns,tsd2d-ns = <60>; 569 cdns,tchsh-ns = <60>; 570 cdns,tslch-ns = <60>; 571 cdns,read-delay = <4>; 572 }; 573}; 574 575&ospi1 { 576 /* Unused */ 577 status = "disabled"; 578}; 579 580&main_i2c0 { 581 status = "okay"; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&main_i2c0_pins_default>; 584 clock-frequency = <400000>; 585 586 i2c-mux@71 { 587 compatible = "nxp,pca9543"; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 reg = <0x71>; 591 592 /* PCIe1 M.2 M Key I2C */ 593 i2c@0 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 reg = <0>; 597 }; 598 599 /* PCIe0 M.2 E Key I2C */ 600 i2c@1 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <1>; 604 }; 605 }; 606}; 607 608&main_i2c1 { 609 status = "okay"; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&main_i2c1_pins_default>; 612 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 613 clock-frequency = <100000>; 614}; 615 616&main_i2c3 { 617 status = "okay"; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&main_i2c3_pins_default>; 620 clock-frequency = <400000>; 621 622 i2c-mux@70 { 623 compatible = "nxp,pca9543"; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 reg = <0x70>; 627 628 /* CSI0 I2C */ 629 i2c@0 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 reg = <0>; 633 }; 634 635 /* CSI1 I2C */ 636 i2c@1 { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 reg = <1>; 640 }; 641 }; 642}; 643 644&main_i2c5 { 645 /* Brought out on RPi Header */ 646 status = "okay"; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&main_i2c5_pins_default>; 649 clock-frequency = <400000>; 650}; 651 652&main_gpio0 { 653 pinctrl-names = "default"; 654 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 655}; 656 657&main_gpio1 { 658 pinctrl-names = "default"; 659 pinctrl-0 = <&rpi_header_gpio1_pins_default>; 660}; 661 662&main_gpio2 { 663 status = "disabled"; 664}; 665 666&main_gpio3 { 667 status = "disabled"; 668}; 669 670&main_gpio4 { 671 status = "disabled"; 672}; 673 674&main_gpio5 { 675 status = "disabled"; 676}; 677 678&main_gpio6 { 679 status = "disabled"; 680}; 681 682&main_gpio7 { 683 status = "disabled"; 684}; 685 686&wkup_gpio1 { 687 status = "disabled"; 688}; 689 690&main_r5fss0_core0{ 691 firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f"; 692}; 693 694&usb_serdes_mux { 695 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 696}; 697 698&serdes_ln_ctrl { 699 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 700 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 701 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 702 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 703 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 704 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 705}; 706 707&serdes_wiz3 { 708 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 709 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 710}; 711 712&serdes3 { 713 serdes3_usb_link: phy@0 { 714 reg = <0>; 715 cdns,num-lanes = <2>; 716 #phy-cells = <0>; 717 cdns,phy-type = <PHY_TYPE_USB3>; 718 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 719 }; 720}; 721 722&serdes4 { 723 torrent_phy_dp: phy@0 { 724 reg = <0>; 725 resets = <&serdes_wiz4 1>; 726 cdns,phy-type = <PHY_TYPE_DP>; 727 cdns,num-lanes = <4>; 728 cdns,max-bit-rate = <5400>; 729 #phy-cells = <0>; 730 }; 731}; 732 733&mhdp { 734 phys = <&torrent_phy_dp>; 735 phy-names = "dpphy"; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&dp0_pins_default>; 738}; 739 740&usbss0 { 741 pinctrl-names = "default"; 742 pinctrl-0 = <&main_usbss0_pins_default>; 743 ti,vbus-divider; 744}; 745 746&usb0 { 747 dr_mode = "otg"; 748 maximum-speed = "super-speed"; 749 phys = <&serdes3_usb_link>; 750 phy-names = "cdns3,usb3-phy"; 751}; 752 753&serdes2 { 754 serdes2_usb_link: phy@1 { 755 reg = <1>; 756 cdns,num-lanes = <1>; 757 #phy-cells = <0>; 758 cdns,phy-type = <PHY_TYPE_USB3>; 759 resets = <&serdes_wiz2 2>; 760 }; 761}; 762 763&usbss1 { 764 pinctrl-names = "default"; 765 pinctrl-0 = <&main_usbss1_pins_default>; 766 ti,vbus-divider; 767}; 768 769&usb1 { 770 dr_mode = "host"; 771 maximum-speed = "super-speed"; 772 phys = <&serdes2_usb_link>; 773 phy-names = "cdns3,usb3-phy"; 774}; 775 776&tscadc0 { 777 /* Unused */ 778 status = "disabled"; 779}; 780 781&tscadc1 { 782 /* Unused */ 783 status = "disabled"; 784}; 785 786&mcu_cpsw { 787 pinctrl-names = "default"; 788 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 789}; 790 791&davinci_mdio { 792 phy0: ethernet-phy@0 { 793 reg = <0>; 794 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 795 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 796 }; 797}; 798 799&cpsw_port1 { 800 phy-mode = "rgmii-rxid"; 801 phy-handle = <&phy0>; 802}; 803 804&dss { 805 pinctrl-names = "default"; 806 pinctrl-0 = <&dss_vout0_pins_default>; 807 808 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 809 <&k3_clks 152 4>, /* VP 2 pixel clock */ 810 <&k3_clks 152 9>, /* VP 3 pixel clock */ 811 <&k3_clks 152 13>; /* VP 4 pixel clock */ 812 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 813 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 814 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 815 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 816}; 817 818&dss_ports { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 822 port@0 { 823 reg = <0>; 824 825 dpi0_out: endpoint { 826 remote-endpoint = <&dp0_in>; 827 }; 828 }; 829 830 port@1 { 831 reg = <1>; 832 833 dpi1_out: endpoint { 834 remote-endpoint = <&tfp410_in>; 835 }; 836 }; 837}; 838 839&dp0_ports { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 843 port@0 { 844 reg = <0>; 845 dp0_in: endpoint { 846 remote-endpoint = <&dpi0_out>; 847 }; 848 }; 849 850 port@4 { 851 reg = <4>; 852 dp0_out: endpoint { 853 remote-endpoint = <&dp_connector_in>; 854 }; 855 }; 856}; 857 858&serdes0 { 859 serdes0_pcie_link: phy@0 { 860 reg = <0>; 861 cdns,num-lanes = <1>; 862 #phy-cells = <0>; 863 cdns,phy-type = <PHY_TYPE_PCIE>; 864 resets = <&serdes_wiz0 1>; 865 }; 866}; 867 868&serdes1 { 869 serdes1_pcie_link: phy@0 { 870 reg = <0>; 871 cdns,num-lanes = <2>; 872 #phy-cells = <0>; 873 cdns,phy-type = <PHY_TYPE_PCIE>; 874 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 875 }; 876}; 877 878&pcie0_rc { 879 pinctrl-names = "default"; 880 pinctrl-0 = <&ekey_reset_pins_default>; 881 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 882 883 phys = <&serdes0_pcie_link>; 884 phy-names = "pcie-phy"; 885 num-lanes = <1>; 886}; 887 888&pcie1_rc { 889 pinctrl-names = "default"; 890 pinctrl-0 = <&mkey_reset_pins_default>; 891 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 892 893 phys = <&serdes1_pcie_link>; 894 phy-names = "pcie-phy"; 895 num-lanes = <2>; 896}; 897 898&pcie2_rc { 899 /* Unused */ 900 status = "disabled"; 901}; 902 903&pcie0_ep { 904 status = "disabled"; 905 phys = <&serdes0_pcie_link>; 906 phy-names = "pcie-phy"; 907 num-lanes = <1>; 908}; 909 910&pcie1_ep { 911 status = "disabled"; 912 phys = <&serdes1_pcie_link>; 913 phy-names = "pcie-phy"; 914 num-lanes = <2>; 915}; 916 917&pcie2_ep { 918 /* Unused */ 919 status = "disabled"; 920}; 921 922&pcie3_rc { 923 /* Unused */ 924 status = "disabled"; 925}; 926 927&pcie3_ep { 928 /* Unused */ 929 status = "disabled"; 930}; 931 932&icssg0_mdio { 933 status = "disabled"; 934}; 935 936&icssg1_mdio { 937 status = "disabled"; 938}; 939 940&ufs_wrapper { 941 status = "disabled"; 942}; 943 944&mailbox0_cluster0 { 945 status = "okay"; 946 interrupts = <436>; 947 948 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 949 ti,mbox-rx = <0 0 0>; 950 ti,mbox-tx = <1 0 0>; 951 }; 952 953 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 954 ti,mbox-rx = <2 0 0>; 955 ti,mbox-tx = <3 0 0>; 956 }; 957}; 958 959&mailbox0_cluster1 { 960 status = "okay"; 961 interrupts = <432>; 962 963 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 964 ti,mbox-rx = <0 0 0>; 965 ti,mbox-tx = <1 0 0>; 966 }; 967 968 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 969 ti,mbox-rx = <2 0 0>; 970 ti,mbox-tx = <3 0 0>; 971 }; 972}; 973 974&mailbox0_cluster2 { 975 status = "okay"; 976 interrupts = <428>; 977 978 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 979 ti,mbox-rx = <0 0 0>; 980 ti,mbox-tx = <1 0 0>; 981 }; 982 983 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 984 ti,mbox-rx = <2 0 0>; 985 ti,mbox-tx = <3 0 0>; 986 }; 987}; 988 989&mailbox0_cluster3 { 990 status = "okay"; 991 interrupts = <424>; 992 993 mbox_c66_0: mbox-c66-0 { 994 ti,mbox-rx = <0 0 0>; 995 ti,mbox-tx = <1 0 0>; 996 }; 997 998 mbox_c66_1: mbox-c66-1 { 999 ti,mbox-rx = <2 0 0>; 1000 ti,mbox-tx = <3 0 0>; 1001 }; 1002}; 1003 1004&mailbox0_cluster4 { 1005 status = "okay"; 1006 interrupts = <420>; 1007 1008 mbox_c71_0: mbox-c71-0 { 1009 ti,mbox-rx = <0 0 0>; 1010 ti,mbox-tx = <1 0 0>; 1011 }; 1012}; 1013 1014&mcu_r5fss0_core0 { 1015 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1016 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1017 <&mcu_r5fss0_core0_memory_region>; 1018}; 1019 1020&mcu_r5fss0_core1 { 1021 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1022 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1023 <&mcu_r5fss0_core1_memory_region>; 1024}; 1025 1026&main_r5fss0_core0 { 1027 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1028 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1029 <&main_r5fss0_core0_memory_region>; 1030}; 1031 1032&main_r5fss0_core1 { 1033 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1034 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1035 <&main_r5fss0_core1_memory_region>; 1036}; 1037 1038&main_r5fss1_core0 { 1039 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1040 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1041 <&main_r5fss1_core0_memory_region>; 1042}; 1043 1044&main_r5fss1_core1 { 1045 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1046 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1047 <&main_r5fss1_core1_memory_region>; 1048}; 1049 1050&c66_0 { 1051 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1052 memory-region = <&c66_0_dma_memory_region>, 1053 <&c66_0_memory_region>; 1054}; 1055 1056&c66_1 { 1057 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 1058 memory-region = <&c66_1_dma_memory_region>, 1059 <&c66_1_memory_region>; 1060}; 1061 1062&c71_0 { 1063 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1064 memory-region = <&c71_0_dma_memory_region>, 1065 <&c71_0_memory_region>; 1066}; 1067