1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 ethernet0 = &cpsw_port1; 25 mmc1 = &main_sdhci1; 26 }; 27 28 chosen { 29 stdout-path = "serial2:115200n8"; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 bootph-all; 35 /* 4G RAM */ 36 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 37 <0x00000008 0x80000000 0x00000000 0x80000000>; 38 }; 39 40 reserved_memory: reserved-memory { 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges; 44 45 secure_ddr: optee@9e800000 { 46 reg = <0x00 0x9e800000 0x00 0x01800000>; 47 alignment = <0x1000>; 48 no-map; 49 }; 50 51 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x00 0xa0000000 0x00 0x100000>; 54 no-map; 55 }; 56 57 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 58 compatible = "shared-dma-pool"; 59 reg = <0x00 0xa0100000 0x00 0xf00000>; 60 no-map; 61 }; 62 63 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 64 compatible = "shared-dma-pool"; 65 reg = <0x00 0xa1000000 0x00 0x100000>; 66 no-map; 67 }; 68 69 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 70 compatible = "shared-dma-pool"; 71 reg = <0x00 0xa1100000 0x00 0xf00000>; 72 no-map; 73 }; 74 75 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 76 compatible = "shared-dma-pool"; 77 reg = <0x00 0xa2000000 0x00 0x100000>; 78 no-map; 79 }; 80 81 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 82 compatible = "shared-dma-pool"; 83 reg = <0x00 0xa2100000 0x00 0xf00000>; 84 no-map; 85 }; 86 87 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 88 compatible = "shared-dma-pool"; 89 reg = <0x00 0xa3000000 0x00 0x100000>; 90 no-map; 91 }; 92 93 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 94 compatible = "shared-dma-pool"; 95 reg = <0x00 0xa3100000 0x00 0xf00000>; 96 no-map; 97 }; 98 99 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 100 compatible = "shared-dma-pool"; 101 reg = <0x00 0xa4000000 0x00 0x100000>; 102 no-map; 103 }; 104 105 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 106 compatible = "shared-dma-pool"; 107 reg = <0x00 0xa4100000 0x00 0xf00000>; 108 no-map; 109 }; 110 111 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 112 compatible = "shared-dma-pool"; 113 reg = <0x00 0xa5000000 0x00 0x100000>; 114 no-map; 115 }; 116 117 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 118 compatible = "shared-dma-pool"; 119 reg = <0x00 0xa5100000 0x00 0xf00000>; 120 no-map; 121 }; 122 123 c66_0_dma_memory_region: c66-dma-memory@a6000000 { 124 compatible = "shared-dma-pool"; 125 reg = <0x00 0xa6000000 0x00 0x100000>; 126 no-map; 127 }; 128 129 c66_0_memory_region: c66-memory@a6100000 { 130 compatible = "shared-dma-pool"; 131 reg = <0x00 0xa6100000 0x00 0xf00000>; 132 no-map; 133 }; 134 135 c66_1_dma_memory_region: c66-dma-memory@a7000000 { 136 compatible = "shared-dma-pool"; 137 reg = <0x00 0xa7000000 0x00 0x100000>; 138 no-map; 139 }; 140 141 c66_1_memory_region: c66-memory@a7100000 { 142 compatible = "shared-dma-pool"; 143 reg = <0x00 0xa7100000 0x00 0xf00000>; 144 no-map; 145 }; 146 147 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 148 compatible = "shared-dma-pool"; 149 reg = <0x00 0xa8000000 0x00 0x100000>; 150 no-map; 151 }; 152 153 c71_0_memory_region: c71-memory@a8100000 { 154 compatible = "shared-dma-pool"; 155 reg = <0x00 0xa8100000 0x00 0xf00000>; 156 no-map; 157 }; 158 159 rtos_ipc_memory_region: ipc-memories@aa000000 { 160 reg = <0x00 0xaa000000 0x00 0x01c00000>; 161 alignment = <0x1000>; 162 no-map; 163 }; 164 }; 165 166 vusb_main: fixedregulator-vusb-main5v0 { 167 /* USB MAIN INPUT 5V DC */ 168 compatible = "regulator-fixed"; 169 regulator-name = "vusb-main5v0"; 170 regulator-min-microvolt = <5000000>; 171 regulator-max-microvolt = <5000000>; 172 regulator-always-on; 173 regulator-boot-on; 174 }; 175 176 vsys_3v3: fixedregulator-vsys3v3 { 177 /* Output of LM5141 */ 178 compatible = "regulator-fixed"; 179 regulator-name = "vsys_3v3"; 180 regulator-min-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>; 182 vin-supply = <&vusb_main>; 183 regulator-always-on; 184 regulator-boot-on; 185 }; 186 187 vdd_mmc1: fixedregulator-sd { 188 compatible = "regulator-fixed"; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 191 regulator-name = "vdd_mmc1"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 regulator-boot-on; 195 enable-active-high; 196 vin-supply = <&vsys_3v3>; 197 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 198 }; 199 200 vdd_sd_dv_alt: gpio-regulator-tps659411 { 201 compatible = "regulator-gpio"; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 204 regulator-name = "tps659411"; 205 regulator-min-microvolt = <1800000>; 206 regulator-max-microvolt = <3300000>; 207 regulator-boot-on; 208 vin-supply = <&vsys_3v3>; 209 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 210 states = <1800000 0x0>, 211 <3300000 0x1>; 212 }; 213 214 transceiver1: can-phy1 { 215 compatible = "ti,tcan1042"; 216 #phy-cells = <0>; 217 max-bitrate = <5000000>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 220 standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>; 221 }; 222 223 transceiver2: can-phy2 { 224 compatible = "ti,tcan1042"; 225 #phy-cells = <0>; 226 max-bitrate = <5000000>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&main_mcan0_gpio_pins_default>; 229 standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>; 230 }; 231 232 transceiver3: can-phy3 { 233 compatible = "ti,tcan1042"; 234 #phy-cells = <0>; 235 max-bitrate = <5000000>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&main_mcan5_gpio_pins_default>; 238 standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>; 239 }; 240 241 transceiver4: can-phy4 { 242 compatible = "ti,tcan1042"; 243 #phy-cells = <0>; 244 max-bitrate = <5000000>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&main_mcan9_gpio_pins_default>; 247 standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>; 248 }; 249 250 dp_pwr_3v3: fixedregulator-dp-prw { 251 compatible = "regulator-fixed"; 252 regulator-name = "dp-pwr"; 253 regulator-min-microvolt = <3300000>; 254 regulator-max-microvolt = <3300000>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&dp_pwr_en_pins_default>; 257 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 258 enable-active-high; 259 }; 260 261 dp0: connector { 262 compatible = "dp-connector"; 263 label = "DP0"; 264 type = "full-size"; 265 dp-pwr-supply = <&dp_pwr_3v3>; 266 267 port { 268 dp_connector_in: endpoint { 269 remote-endpoint = <&dp0_out>; 270 }; 271 }; 272 }; 273 274 hdmi-connector { 275 compatible = "hdmi-connector"; 276 label = "hdmi"; 277 type = "a"; 278 279 pinctrl-names = "default"; 280 pinctrl-0 = <&hdmi_hpd_pins_default>; 281 282 ddc-i2c-bus = <&main_i2c1>; 283 284 /* HDMI_HPD */ 285 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; 286 287 port { 288 hdmi_connector_in: endpoint { 289 remote-endpoint = <&tfp410_out>; 290 }; 291 }; 292 }; 293 294 dvi-bridge { 295 compatible = "ti,tfp410"; 296 297 pinctrl-names = "default"; 298 pinctrl-0 = <&hdmi_pdn_pins_default>; 299 300 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; 301 ti,deskew = <0>; 302 303 ports { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 port@0 { 308 reg = <0>; 309 310 tfp410_in: endpoint { 311 remote-endpoint = <&dpi1_out>; 312 pclk-sample = <1>; 313 }; 314 }; 315 316 port@1 { 317 reg = <1>; 318 319 tfp410_out: endpoint { 320 remote-endpoint = 321 <&hdmi_connector_in>; 322 }; 323 }; 324 }; 325 }; 326 327 csi_mux: mux-controller { 328 compatible = "gpio-mux"; 329 #mux-state-cells = <1>; 330 mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; 331 idle-state = <0>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&main_csi_mux_sel_pins_default>; 334 }; 335}; 336 337&main_pmx0 { 338 main_mmc1_pins_default: main-mmc1-default-pins { 339 pinctrl-single,pins = < 340 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 341 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 342 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 343 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 344 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 345 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 346 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 347 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 348 >; 349 bootph-all; 350 }; 351 352 main_uart0_pins_default: main-uart0-default-pins { 353 pinctrl-single,pins = < 354 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 355 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 356 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 357 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 358 >; 359 bootph-all; 360 }; 361 362 main_uart1_pins_default: main-uart1-default-pins { 363 pinctrl-single,pins = < 364 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 365 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 366 >; 367 }; 368 369 main_i2c0_pins_default: main-i2c0-default-pins { 370 pinctrl-single,pins = < 371 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 372 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 373 >; 374 }; 375 376 main_i2c1_pins_default: main-i2c1-default-pins { 377 pinctrl-single,pins = < 378 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 379 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 380 >; 381 }; 382 383 main_i2c3_pins_default: main-i2c3-default-pins { 384 pinctrl-single,pins = < 385 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 386 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 387 >; 388 }; 389 390 main_usbss0_pins_default: main-usbss0-default-pins { 391 pinctrl-single,pins = < 392 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 393 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 394 >; 395 bootph-all; 396 }; 397 398 main_usbss1_pins_default: main-usbss1-default-pins { 399 pinctrl-single,pins = < 400 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 401 >; 402 bootph-all; 403 }; 404 405 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { 406 pinctrl-single,pins = < 407 J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ 408 >; 409 }; 410 411 main_mcan0_pins_default: main-mcan0-default-pins { 412 pinctrl-single,pins = < 413 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 414 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 415 >; 416 }; 417 418 main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins { 419 pinctrl-single,pins = < 420 J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */ 421 >; 422 }; 423 424 main_mcan5_pins_default: main-mcan5-default-pins { 425 pinctrl-single,pins = < 426 J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */ 427 J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */ 428 >; 429 }; 430 431 main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins { 432 pinctrl-single,pins = < 433 J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */ 434 >; 435 }; 436 437 main_mcan9_pins_default: main-mcan9-default-pins { 438 pinctrl-single,pins = < 439 J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */ 440 J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */ 441 >; 442 }; 443 444 main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins { 445 pinctrl-single,pins = < 446 J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */ 447 >; 448 }; 449 450 dp0_pins_default: dp0-default-pins { 451 pinctrl-single,pins = < 452 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 453 >; 454 }; 455 456 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 457 pinctrl-single,pins = < 458 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 459 >; 460 }; 461 462 dss_vout0_pins_default: dss-vout0-default-pins { 463 pinctrl-single,pins = < 464 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 465 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 466 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 467 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 468 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 469 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 470 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 471 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 472 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 473 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 474 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 475 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 476 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 477 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 478 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 479 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 480 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 481 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 482 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 483 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 484 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 485 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 486 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 487 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 488 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 489 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 490 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 491 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 492 >; 493 }; 494 495 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 496 pinctrl-single,pins = < 497 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ 498 >; 499 }; 500 501 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 502 pinctrl-single,pins = < 503 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 504 >; 505 }; 506 507 /* Reset for M.2 E Key slot on PCIe0 */ 508 ekey_reset_pins_default: ekey-reset-pns-default-pins { 509 pinctrl-single,pins = < 510 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 511 >; 512 }; 513 514 main_i2c5_pins_default: main-i2c5-default-pins { 515 pinctrl-single,pins = < 516 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 517 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 518 >; 519 }; 520 521 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 522 pinctrl-single,pins = < 523 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ 524 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ 525 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 526 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ 527 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 528 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 529 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 530 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ 531 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ 532 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ 533 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ 534 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ 535 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ 536 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ 537 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 538 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ 539 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 540 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ 541 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ 542 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ 543 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ 544 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ 545 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ 546 >; 547 }; 548 549 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { 550 pinctrl-single,pins = < 551 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ 552 >; 553 }; 554}; 555 556&wkup_pmx0 { 557 pmic_irq_pins_default: pmic-irq-default-pins { 558 pinctrl-single,pins = < 559 J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 560 >; 561 }; 562 563 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 564 pinctrl-single,pins = < 565 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 566 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 567 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 568 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 569 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 570 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 571 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 572 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 573 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 574 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 575 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 576 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 577 >; 578 }; 579 580 mcu_mdio_pins_default: mcu-mdio1-default-pins { 581 pinctrl-single,pins = < 582 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 583 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 584 >; 585 }; 586 587 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 588 pinctrl-single,pins = < 589 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 590 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 591 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 592 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 593 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 594 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 595 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 596 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 597 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 598 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 599 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 600 >; 601 bootph-all; 602 }; 603 604 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { 605 pinctrl-single,pins = < 606 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 607 >; 608 }; 609 610 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 611 pinctrl-single,pins = < 612 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 613 >; 614 }; 615 616 wkup_uart0_pins_default: wkup-uart0-default-pins { 617 pinctrl-single,pins = < 618 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 619 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 620 >; 621 }; 622 623 mcu_uart0_pins_default: mcu-uart0-default-pins { 624 pinctrl-single,pins = < 625 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ 626 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ 627 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 628 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 629 >; 630 bootph-all; 631 }; 632 633 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 634 pinctrl-single,pins = < 635 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 636 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 637 >; 638 bootph-all; 639 }; 640 641 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 642 pinctrl-single,pins = < 643 J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 644 J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 645 >; 646 }; 647 648 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 649 pinctrl-single,pins = < 650 J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */ 651 >; 652 }; 653 654 /* Reset for M.2 M Key slot on PCIe1 */ 655 mkey_reset_pins_default: mkey-reset-pns-default-pins { 656 pinctrl-single,pins = < 657 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 658 >; 659 }; 660}; 661 662&wkup_uart0 { 663 /* Wakeup UART is used by System firmware */ 664 status = "reserved"; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&wkup_uart0_pins_default>; 667 bootph-all; 668}; 669 670&wkup_i2c0 { 671 status = "okay"; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&wkup_i2c0_pins_default>; 674 clock-frequency = <400000>; 675 676 eeprom@51 { 677 /* AT24C512C-MAHM-T */ 678 compatible = "atmel,24c512"; 679 reg = <0x51>; 680 }; 681 682 tps659413: pmic@48 { 683 compatible = "ti,tps6594-q1"; 684 reg = <0x48>; 685 system-power-controller; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&pmic_irq_pins_default>; 688 interrupt-parent = <&wkup_gpio0>; 689 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 690 gpio-controller; 691 #gpio-cells = <2>; 692 ti,primary-pmic; 693 buck123-supply = <&vsys_3v3>; 694 buck4-supply = <&vsys_3v3>; 695 buck5-supply = <&vsys_3v3>; 696 ldo1-supply = <&vsys_3v3>; 697 ldo2-supply = <&vsys_3v3>; 698 ldo3-supply = <&vsys_3v3>; 699 ldo4-supply = <&vsys_3v3>; 700 701 regulators { 702 bucka123: buck123 { 703 regulator-name = "vdd_cpu_avs"; 704 regulator-min-microvolt = <600000>; 705 regulator-max-microvolt = <900000>; 706 regulator-boot-on; 707 regulator-always-on; 708 bootph-pre-ram; 709 }; 710 711 bucka4: buck4 { 712 regulator-name = "vdd_mcu_0v85"; 713 regulator-min-microvolt = <850000>; 714 regulator-max-microvolt = <850000>; 715 regulator-boot-on; 716 regulator-always-on; 717 }; 718 719 bucka5: buck5 { 720 regulator-name = "vdd_phyio_1v8"; 721 regulator-min-microvolt = <1800000>; 722 regulator-max-microvolt = <1800000>; 723 regulator-boot-on; 724 regulator-always-on; 725 }; 726 727 ldoa1: ldo1 { 728 regulator-name = "vdd1_lpddr4_1v8"; 729 regulator-min-microvolt = <1800000>; 730 regulator-max-microvolt = <1800000>; 731 regulator-boot-on; 732 regulator-always-on; 733 }; 734 735 ldoa2: ldo2 { 736 regulator-name = "vdd_mcuio_1v8"; 737 regulator-min-microvolt = <1800000>; 738 regulator-max-microvolt = <1800000>; 739 regulator-boot-on; 740 regulator-always-on; 741 }; 742 743 ldoa3: ldo3 { 744 regulator-name = "vdda_dll_0v8"; 745 regulator-min-microvolt = <800000>; 746 regulator-max-microvolt = <800000>; 747 regulator-boot-on; 748 regulator-always-on; 749 }; 750 751 ldoa4: ldo4 { 752 regulator-name = "vda_mcu_1v8"; 753 regulator-min-microvolt = <1800000>; 754 regulator-max-microvolt = <1800000>; 755 regulator-boot-on; 756 regulator-always-on; 757 }; 758 }; 759 }; 760 761 tps659411: pmic@4c { 762 compatible = "ti,tps6594-q1"; 763 reg = <0x4c>; 764 system-power-controller; 765 interrupt-parent = <&wkup_gpio0>; 766 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 767 gpio-controller; 768 #gpio-cells = <2>; 769 buck1234-supply = <&vsys_3v3>; 770 buck5-supply = <&vsys_3v3>; 771 ldo1-supply = <&vsys_3v3>; 772 ldo2-supply = <&vsys_3v3>; 773 ldo3-supply = <&vsys_3v3>; 774 ldo4-supply = <&vsys_3v3>; 775 776 regulators { 777 buckb1234: buck1234 { 778 regulator-name = "vdd_core_0v8"; 779 regulator-min-microvolt = <800000>; 780 regulator-max-microvolt = <800000>; 781 regulator-boot-on; 782 regulator-always-on; 783 }; 784 785 buckb5: buck5 { 786 regulator-name = "vdd_ram_0v85"; 787 regulator-min-microvolt = <850000>; 788 regulator-max-microvolt = <850000>; 789 regulator-boot-on; 790 regulator-always-on; 791 }; 792 793 ldob1: ldo1 { 794 regulator-name = "vdd_sd_dv"; 795 regulator-min-microvolt = <1800000>; 796 regulator-max-microvolt = <3300000>; 797 regulator-boot-on; 798 regulator-always-on; 799 }; 800 801 ldob2: ldo2 { 802 regulator-name = "vdd_usb_3v3"; 803 regulator-min-microvolt = <3300000>; 804 regulator-max-microvolt = <3300000>; 805 regulator-boot-on; 806 regulator-always-on; 807 }; 808 809 ldob3: ldo3 { 810 regulator-name = "vdd_io_1v8"; 811 regulator-min-microvolt = <1800000>; 812 regulator-max-microvolt = <1800000>; 813 regulator-boot-on; 814 regulator-always-on; 815 }; 816 817 ldob4: ldo4 { 818 regulator-name = "vda_pll_1v8"; 819 regulator-min-microvolt = <1800000>; 820 regulator-max-microvolt = <1800000>; 821 regulator-boot-on; 822 regulator-always-on; 823 }; 824 }; 825 }; 826}; 827 828&mcu_uart0 { 829 status = "okay"; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&mcu_uart0_pins_default>; 832 bootph-all; 833}; 834 835&main_uart0 { 836 status = "okay"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&main_uart0_pins_default>; 839 /* Shared with ATF on this platform */ 840 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 841 bootph-all; 842}; 843 844&main_uart1 { 845 status = "okay"; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&main_uart1_pins_default>; 848}; 849 850&main_sdhci1 { 851 /* SD Card */ 852 status = "okay"; 853 vmmc-supply = <&vdd_mmc1>; 854 vqmmc-supply = <&vdd_sd_dv_alt>; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&main_mmc1_pins_default>; 857 bootph-all; 858 ti,driver-strength-ohm = <50>; 859 disable-wp; 860}; 861 862&ospi0 { 863 status = "okay"; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 866 867 flash@0 { 868 compatible = "jedec,spi-nor"; 869 reg = <0x0>; 870 spi-tx-bus-width = <8>; 871 spi-rx-bus-width = <8>; 872 spi-max-frequency = <25000000>; 873 cdns,tshsl-ns = <60>; 874 cdns,tsd2d-ns = <60>; 875 cdns,tchsh-ns = <60>; 876 cdns,tslch-ns = <60>; 877 cdns,read-delay = <4>; 878 879 partitions { 880 compatible = "fixed-partitions"; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 884 partition@0 { 885 label = "ospi.tiboot3"; 886 reg = <0x0 0x80000>; 887 }; 888 889 partition@80000 { 890 label = "ospi.tispl"; 891 reg = <0x80000 0x200000>; 892 }; 893 894 partition@280000 { 895 label = "ospi.u-boot"; 896 reg = <0x280000 0x400000>; 897 }; 898 899 partition@680000 { 900 label = "ospi.env"; 901 reg = <0x680000 0x40000>; 902 }; 903 904 partition@6c0000 { 905 label = "ospi.sysfw"; 906 reg = <0x6c0000 0x100000>; 907 }; 908 909 partition@7c0000 { 910 label = "ospi.env.backup"; 911 reg = <0x7c0000 0x40000>; 912 }; 913 914 partition@800000 { 915 label = "ospi.rootfs"; 916 reg = <0x800000 0x37c0000>; 917 }; 918 919 partition@3fc0000 { 920 label = "ospi.phypattern"; 921 reg = <0x3fc0000 0x40000>; 922 bootph-all; 923 }; 924 }; 925 }; 926}; 927 928&main_i2c0 { 929 status = "okay"; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&main_i2c0_pins_default>; 932 clock-frequency = <400000>; 933 934 i2c-mux@71 { 935 compatible = "nxp,pca9543"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 reg = <0x71>; 939 940 /* PCIe1 M.2 M Key I2C */ 941 i2c@0 { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 reg = <0>; 945 }; 946 947 /* PCIe0 M.2 E Key I2C */ 948 i2c@1 { 949 #address-cells = <1>; 950 #size-cells = <0>; 951 reg = <1>; 952 }; 953 }; 954}; 955 956&main_i2c1 { 957 status = "okay"; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&main_i2c1_pins_default>; 960 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 961 clock-frequency = <100000>; 962}; 963 964&main_i2c3 { 965 status = "okay"; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&main_i2c3_pins_default>; 968 clock-frequency = <400000>; 969 970 i2c-mux@70 { 971 compatible = "nxp,pca9543"; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 reg = <0x70>; 975 976 /* CSI0 I2C */ 977 cam0_i2c: i2c@0 { 978 #address-cells = <1>; 979 #size-cells = <0>; 980 reg = <0>; 981 }; 982 983 /* CSI1 I2C */ 984 cam1_i2c: i2c@1 { 985 #address-cells = <1>; 986 #size-cells = <0>; 987 reg = <1>; 988 }; 989 }; 990}; 991 992&main_i2c5 { 993 /* Brought out on RPi Header */ 994 status = "okay"; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&main_i2c5_pins_default>; 997 clock-frequency = <400000>; 998}; 999 1000&main_gpio0 { 1001 status = "okay"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 1004}; 1005 1006&main_gpio1 { 1007 status = "okay"; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&rpi_header_gpio1_pins_default>; 1010}; 1011 1012&wkup_gpio0 { 1013 status = "okay"; 1014}; 1015 1016&usb_serdes_mux { 1017 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 1018 bootph-all; 1019}; 1020 1021&serdes_ln_ctrl { 1022 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 1023 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 1024 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 1025 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 1026 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 1027 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 1028 bootph-all; 1029}; 1030 1031&serdes_wiz3 { 1032 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 1033 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 1034}; 1035 1036&serdes3 { 1037 serdes3_usb_link: phy@0 { 1038 reg = <0>; 1039 cdns,num-lanes = <2>; 1040 #phy-cells = <0>; 1041 cdns,phy-type = <PHY_TYPE_USB3>; 1042 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 1043 }; 1044}; 1045 1046&serdes4 { 1047 torrent_phy_dp: phy@0 { 1048 reg = <0>; 1049 resets = <&serdes_wiz4 1>; 1050 cdns,phy-type = <PHY_TYPE_DP>; 1051 cdns,num-lanes = <4>; 1052 cdns,max-bit-rate = <5400>; 1053 #phy-cells = <0>; 1054 }; 1055}; 1056 1057&mhdp { 1058 phys = <&torrent_phy_dp>; 1059 phy-names = "dpphy"; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&dp0_pins_default>; 1062}; 1063 1064&usbss0 { 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&main_usbss0_pins_default>; 1067 bootph-all; 1068 ti,vbus-divider; 1069}; 1070 1071&usb0 { 1072 dr_mode = "otg"; 1073 maximum-speed = "super-speed"; 1074 phys = <&serdes3_usb_link>; 1075 phy-names = "cdns3,usb3-phy"; 1076 bootph-all; 1077}; 1078 1079&serdes2 { 1080 serdes2_usb_link: phy@1 { 1081 reg = <1>; 1082 cdns,num-lanes = <1>; 1083 #phy-cells = <0>; 1084 cdns,phy-type = <PHY_TYPE_USB3>; 1085 resets = <&serdes_wiz2 2>; 1086 }; 1087}; 1088 1089&usbss1 { 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&main_usbss1_pins_default>; 1092 bootph-all; 1093 ti,vbus-divider; 1094}; 1095 1096&usb1 { 1097 dr_mode = "host"; 1098 maximum-speed = "super-speed"; 1099 phys = <&serdes2_usb_link>; 1100 phy-names = "cdns3,usb3-phy"; 1101 bootph-all; 1102}; 1103 1104&mcu_cpsw { 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 1107}; 1108 1109&davinci_mdio { 1110 phy0: ethernet-phy@0 { 1111 reg = <0>; 1112 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1113 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1114 }; 1115}; 1116 1117&cpsw_port1 { 1118 phy-mode = "rgmii-rxid"; 1119 phy-handle = <&phy0>; 1120}; 1121 1122&dss { 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&dss_vout0_pins_default>; 1125 1126 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 1127 <&k3_clks 152 4>, /* VP 2 pixel clock */ 1128 <&k3_clks 152 9>, /* VP 3 pixel clock */ 1129 <&k3_clks 152 13>; /* VP 4 pixel clock */ 1130 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 1131 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 1132 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 1133 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 1134}; 1135 1136&dss_ports { 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 1140 port@0 { 1141 reg = <0>; 1142 1143 dpi0_out: endpoint { 1144 remote-endpoint = <&dp0_in>; 1145 }; 1146 }; 1147 1148 port@1 { 1149 reg = <1>; 1150 1151 dpi1_out: endpoint { 1152 remote-endpoint = <&tfp410_in>; 1153 }; 1154 }; 1155}; 1156 1157&dp0_ports { 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 1161 port@0 { 1162 reg = <0>; 1163 dp0_in: endpoint { 1164 remote-endpoint = <&dpi0_out>; 1165 }; 1166 }; 1167 1168 port@4 { 1169 reg = <4>; 1170 dp0_out: endpoint { 1171 remote-endpoint = <&dp_connector_in>; 1172 }; 1173 }; 1174}; 1175 1176&serdes0 { 1177 serdes0_pcie_link: phy@0 { 1178 reg = <0>; 1179 cdns,num-lanes = <1>; 1180 #phy-cells = <0>; 1181 cdns,phy-type = <PHY_TYPE_PCIE>; 1182 resets = <&serdes_wiz0 1>; 1183 }; 1184}; 1185 1186&serdes1 { 1187 serdes1_pcie_link: phy@0 { 1188 reg = <0>; 1189 cdns,num-lanes = <2>; 1190 #phy-cells = <0>; 1191 cdns,phy-type = <PHY_TYPE_PCIE>; 1192 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 1193 }; 1194}; 1195 1196&pcie0_rc { 1197 status = "okay"; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&ekey_reset_pins_default>; 1200 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 1201 1202 phys = <&serdes0_pcie_link>; 1203 phy-names = "pcie-phy"; 1204 num-lanes = <1>; 1205}; 1206 1207&pcie1_rc { 1208 status = "okay"; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&mkey_reset_pins_default>; 1211 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 1212 1213 phys = <&serdes1_pcie_link>; 1214 phy-names = "pcie-phy"; 1215 num-lanes = <2>; 1216}; 1217 1218&mcu_mcan0 { 1219 pinctrl-names = "default"; 1220 pinctrl-0 = <&mcu_mcan0_pins_default>; 1221 phys = <&transceiver1>; 1222 status = "okay"; 1223}; 1224 1225&main_mcan0 { 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&main_mcan0_pins_default>; 1228 phys = <&transceiver2>; 1229 status = "okay"; 1230}; 1231 1232&main_mcan5 { 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&main_mcan5_pins_default>; 1235 phys = <&transceiver3>; 1236 status = "okay"; 1237}; 1238 1239&main_mcan9 { 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&main_mcan9_pins_default>; 1242 phys = <&transceiver4>; 1243 status = "okay"; 1244}; 1245 1246&ufs_wrapper { 1247 status = "disabled"; 1248}; 1249 1250&mailbox0_cluster0 { 1251 status = "okay"; 1252 interrupts = <436>; 1253 1254 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1255 ti,mbox-rx = <0 0 0>; 1256 ti,mbox-tx = <1 0 0>; 1257 }; 1258 1259 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1260 ti,mbox-rx = <2 0 0>; 1261 ti,mbox-tx = <3 0 0>; 1262 }; 1263}; 1264 1265&mailbox0_cluster1 { 1266 status = "okay"; 1267 interrupts = <432>; 1268 1269 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1270 ti,mbox-rx = <0 0 0>; 1271 ti,mbox-tx = <1 0 0>; 1272 }; 1273 1274 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1275 ti,mbox-rx = <2 0 0>; 1276 ti,mbox-tx = <3 0 0>; 1277 }; 1278}; 1279 1280&mailbox0_cluster2 { 1281 status = "okay"; 1282 interrupts = <428>; 1283 1284 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1285 ti,mbox-rx = <0 0 0>; 1286 ti,mbox-tx = <1 0 0>; 1287 }; 1288 1289 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1290 ti,mbox-rx = <2 0 0>; 1291 ti,mbox-tx = <3 0 0>; 1292 }; 1293}; 1294 1295&mailbox0_cluster3 { 1296 status = "okay"; 1297 interrupts = <424>; 1298 1299 mbox_c66_0: mbox-c66-0 { 1300 ti,mbox-rx = <0 0 0>; 1301 ti,mbox-tx = <1 0 0>; 1302 }; 1303 1304 mbox_c66_1: mbox-c66-1 { 1305 ti,mbox-rx = <2 0 0>; 1306 ti,mbox-tx = <3 0 0>; 1307 }; 1308}; 1309 1310&mailbox0_cluster4 { 1311 status = "okay"; 1312 interrupts = <420>; 1313 1314 mbox_c71_0: mbox-c71-0 { 1315 ti,mbox-rx = <0 0 0>; 1316 ti,mbox-tx = <1 0 0>; 1317 }; 1318}; 1319 1320&mcu_r5fss0_core0 { 1321 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1322 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1323 <&mcu_r5fss0_core0_memory_region>; 1324}; 1325 1326&mcu_r5fss0_core1 { 1327 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1328 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1329 <&mcu_r5fss0_core1_memory_region>; 1330}; 1331 1332&main_r5fss0 { 1333 ti,cluster-mode = <0>; 1334}; 1335 1336&main_r5fss1 { 1337 ti,cluster-mode = <0>; 1338}; 1339 1340/* Timers are used by Remoteproc firmware */ 1341&main_timer0 { 1342 status = "reserved"; 1343}; 1344 1345&main_timer1 { 1346 status = "reserved"; 1347}; 1348 1349&main_timer2 { 1350 status = "reserved"; 1351}; 1352 1353&main_timer12 { 1354 status = "reserved"; 1355}; 1356 1357&main_timer13 { 1358 status = "reserved"; 1359}; 1360 1361&main_timer14 { 1362 status = "reserved"; 1363}; 1364 1365&main_timer15 { 1366 status = "reserved"; 1367}; 1368 1369&main_r5fss0_core0 { 1370 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1371 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1372 <&main_r5fss0_core0_memory_region>; 1373}; 1374 1375&main_r5fss0_core1 { 1376 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1377 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1378 <&main_r5fss0_core1_memory_region>; 1379}; 1380 1381&main_r5fss1_core0 { 1382 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1383 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1384 <&main_r5fss1_core0_memory_region>; 1385}; 1386 1387&main_r5fss1_core1 { 1388 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1389 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1390 <&main_r5fss1_core1_memory_region>; 1391}; 1392 1393&c66_0 { 1394 status = "okay"; 1395 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1396 memory-region = <&c66_0_dma_memory_region>, 1397 <&c66_0_memory_region>; 1398}; 1399 1400&c66_1 { 1401 status = "okay"; 1402 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 1403 memory-region = <&c66_1_dma_memory_region>, 1404 <&c66_1_memory_region>; 1405}; 1406 1407&c71_0 { 1408 status = "okay"; 1409 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1410 memory-region = <&c71_0_dma_memory_region>, 1411 <&c71_0_memory_region>; 1412}; 1413