1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: bus@40f00000 { 38 compatible = "simple-bus"; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 ranges = <0x0 0x0 0x40f00000 0x20000>; 42 43 cpsw_mac_syscon: ethernet-mac-syscon@200 { 44 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 45 reg = <0x200 0x8>; 46 }; 47 48 phy_gmii_sel: phy@4040 { 49 compatible = "ti,am654-phy-gmii-sel"; 50 reg = <0x4040 0x4>; 51 #phy-cells = <1>; 52 }; 53 }; 54 55 wkup_conf: bus@43000000 { 56 compatible = "simple-bus"; 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges = <0x0 0x00 0x43000000 0x20000>; 60 61 chipid: chipid@14 { 62 compatible = "ti,am654-chipid"; 63 reg = <0x14 0x4>; 64 }; 65 }; 66 67 wkup_pmx0: pinctrl@4301c000 { 68 compatible = "pinctrl-single"; 69 /* Proxy 0 addressing */ 70 reg = <0x00 0x4301c000 0x00 0x178>; 71 #pinctrl-cells = <1>; 72 pinctrl-single,register-width = <32>; 73 pinctrl-single,function-mask = <0xffffffff>; 74 }; 75 76 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 77 mcu_timerio_input: pinctrl@40f04200 { 78 compatible = "pinctrl-single"; 79 reg = <0x00 0x40f04200 0x00 0x28>; 80 #pinctrl-cells = <1>; 81 pinctrl-single,register-width = <32>; 82 pinctrl-single,function-mask = <0x0000000f>; 83 /* Non-MPU Firmware usage */ 84 status = "reserved"; 85 }; 86 87 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 88 mcu_timerio_output: pinctrl@40f04280 { 89 compatible = "pinctrl-single"; 90 reg = <0x00 0x40f04280 0x00 0x28>; 91 #pinctrl-cells = <1>; 92 pinctrl-single,register-width = <32>; 93 pinctrl-single,function-mask = <0x0000000f>; 94 /* Non-MPU Firmware usage */ 95 status = "reserved"; 96 }; 97 98 mcu_ram: sram@41c00000 { 99 compatible = "mmio-sram"; 100 reg = <0x00 0x41c00000 0x00 0x100000>; 101 ranges = <0x0 0x00 0x41c00000 0x100000>; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 }; 105 106 mcu_timer0: timer@40400000 { 107 compatible = "ti,am654-timer"; 108 reg = <0x00 0x40400000 0x00 0x400>; 109 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&k3_clks 35 1>; 111 clock-names = "fck"; 112 assigned-clocks = <&k3_clks 35 1>; 113 assigned-clock-parents = <&k3_clks 35 2>; 114 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 115 ti,timer-pwm; 116 /* Non-MPU Firmware usage */ 117 status = "reserved"; 118 }; 119 120 mcu_timer1: timer@40410000 { 121 compatible = "ti,am654-timer"; 122 reg = <0x00 0x40410000 0x00 0x400>; 123 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&k3_clks 71 1>; 125 clock-names = "fck"; 126 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; 127 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; 128 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 129 ti,timer-pwm; 130 /* Non-MPU Firmware usage */ 131 status = "reserved"; 132 }; 133 134 mcu_timer2: timer@40420000 { 135 compatible = "ti,am654-timer"; 136 reg = <0x00 0x40420000 0x00 0x400>; 137 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&k3_clks 72 1>; 139 clock-names = "fck"; 140 assigned-clocks = <&k3_clks 72 1>; 141 assigned-clock-parents = <&k3_clks 72 2>; 142 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 143 ti,timer-pwm; 144 /* Non-MPU Firmware usage */ 145 status = "reserved"; 146 }; 147 148 mcu_timer3: timer@40430000 { 149 compatible = "ti,am654-timer"; 150 reg = <0x00 0x40430000 0x00 0x400>; 151 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&k3_clks 73 1>; 153 clock-names = "fck"; 154 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; 155 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; 156 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 157 ti,timer-pwm; 158 /* Non-MPU Firmware usage */ 159 status = "reserved"; 160 }; 161 162 mcu_timer4: timer@40440000 { 163 compatible = "ti,am654-timer"; 164 reg = <0x00 0x40440000 0x00 0x400>; 165 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&k3_clks 74 1>; 167 clock-names = "fck"; 168 assigned-clocks = <&k3_clks 74 1>; 169 assigned-clock-parents = <&k3_clks 74 2>; 170 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 171 ti,timer-pwm; 172 /* Non-MPU Firmware usage */ 173 status = "reserved"; 174 }; 175 176 mcu_timer5: timer@40450000 { 177 compatible = "ti,am654-timer"; 178 reg = <0x00 0x40450000 0x00 0x400>; 179 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&k3_clks 75 1>; 181 clock-names = "fck"; 182 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; 183 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; 184 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 185 ti,timer-pwm; 186 /* Non-MPU Firmware usage */ 187 status = "reserved"; 188 }; 189 190 mcu_timer6: timer@40460000 { 191 compatible = "ti,am654-timer"; 192 reg = <0x00 0x40460000 0x00 0x400>; 193 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&k3_clks 76 1>; 195 clock-names = "fck"; 196 assigned-clocks = <&k3_clks 76 1>; 197 assigned-clock-parents = <&k3_clks 76 2>; 198 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 199 ti,timer-pwm; 200 /* Non-MPU Firmware usage */ 201 status = "reserved"; 202 }; 203 204 mcu_timer7: timer@40470000 { 205 compatible = "ti,am654-timer"; 206 reg = <0x00 0x40470000 0x00 0x400>; 207 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&k3_clks 77 1>; 209 clock-names = "fck"; 210 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; 211 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; 212 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 213 ti,timer-pwm; 214 /* Non-MPU Firmware usage */ 215 status = "reserved"; 216 }; 217 218 mcu_timer8: timer@40480000 { 219 compatible = "ti,am654-timer"; 220 reg = <0x00 0x40480000 0x00 0x400>; 221 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&k3_clks 78 1>; 223 clock-names = "fck"; 224 assigned-clocks = <&k3_clks 78 1>; 225 assigned-clock-parents = <&k3_clks 78 2>; 226 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 227 ti,timer-pwm; 228 /* Non-MPU Firmware usage */ 229 status = "reserved"; 230 }; 231 232 mcu_timer9: timer@40490000 { 233 compatible = "ti,am654-timer"; 234 reg = <0x00 0x40490000 0x00 0x400>; 235 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&k3_clks 79 1>; 237 clock-names = "fck"; 238 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; 239 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; 240 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 241 ti,timer-pwm; 242 /* Non-MPU Firmware usage */ 243 status = "reserved"; 244 }; 245 wkup_uart0: serial@42300000 { 246 compatible = "ti,j721e-uart", "ti,am654-uart"; 247 reg = <0x00 0x42300000 0x00 0x100>; 248 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 249 clock-frequency = <48000000>; 250 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 251 clocks = <&k3_clks 287 0>; 252 clock-names = "fclk"; 253 status = "disabled"; 254 }; 255 256 mcu_uart0: serial@40a00000 { 257 compatible = "ti,j721e-uart", "ti,am654-uart"; 258 reg = <0x00 0x40a00000 0x00 0x100>; 259 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <96000000>; 261 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 262 clocks = <&k3_clks 149 0>; 263 clock-names = "fclk"; 264 status = "disabled"; 265 }; 266 267 wkup_gpio_intr: interrupt-controller@42200000 { 268 compatible = "ti,sci-intr"; 269 reg = <0x00 0x42200000 0x00 0x400>; 270 ti,intr-trigger-type = <1>; 271 interrupt-controller; 272 interrupt-parent = <&gic500>; 273 #interrupt-cells = <1>; 274 ti,sci = <&dmsc>; 275 ti,sci-dev-id = <137>; 276 ti,interrupt-ranges = <16 960 16>; 277 }; 278 279 wkup_gpio0: gpio@42110000 { 280 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 281 reg = <0x0 0x42110000 0x0 0x100>; 282 gpio-controller; 283 #gpio-cells = <2>; 284 interrupt-parent = <&wkup_gpio_intr>; 285 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 286 interrupt-controller; 287 #interrupt-cells = <2>; 288 ti,ngpio = <84>; 289 ti,davinci-gpio-unbanked = <0>; 290 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 291 clocks = <&k3_clks 113 0>; 292 clock-names = "gpio"; 293 status = "disabled"; 294 }; 295 296 wkup_gpio1: gpio@42100000 { 297 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 298 reg = <0x0 0x42100000 0x0 0x100>; 299 gpio-controller; 300 #gpio-cells = <2>; 301 interrupt-parent = <&wkup_gpio_intr>; 302 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 ti,ngpio = <84>; 306 ti,davinci-gpio-unbanked = <0>; 307 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 308 clocks = <&k3_clks 114 0>; 309 clock-names = "gpio"; 310 status = "disabled"; 311 }; 312 313 mcu_i2c0: i2c@40b00000 { 314 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 315 reg = <0x0 0x40b00000 0x0 0x100>; 316 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 clock-names = "fck"; 320 clocks = <&k3_clks 194 0>; 321 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 322 status = "disabled"; 323 }; 324 325 mcu_i2c1: i2c@40b10000 { 326 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 327 reg = <0x0 0x40b10000 0x0 0x100>; 328 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 clock-names = "fck"; 332 clocks = <&k3_clks 195 0>; 333 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 334 status = "disabled"; 335 }; 336 337 wkup_i2c0: i2c@42120000 { 338 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 339 reg = <0x0 0x42120000 0x0 0x100>; 340 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 clock-names = "fck"; 344 clocks = <&k3_clks 197 0>; 345 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 346 status = "disabled"; 347 }; 348 349 fss: bus@47000000 { 350 compatible = "simple-bus"; 351 #address-cells = <2>; 352 #size-cells = <2>; 353 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 354 <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */ 355 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 356 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ 357 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* HBMC/OSPI0 Memory */ 358 <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ 359 360 hbmc_mux: mux-controller@47000004 { 361 compatible = "reg-mux"; 362 reg = <0x00 0x47000004 0x00 0x4>; 363 #mux-control-cells = <1>; 364 mux-reg-masks = <0x0 0x2>; /* HBMC select */ 365 }; 366 367 hbmc: hyperbus@47034000 { 368 compatible = "ti,am654-hbmc"; 369 reg = <0x00 0x47034000 0x00 0x100>, 370 <0x05 0x00000000 0x01 0x0000000>; 371 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 372 clocks = <&k3_clks 102 0>; 373 assigned-clocks = <&k3_clks 102 5>; 374 assigned-clock-rates = <333333333>; 375 #address-cells = <2>; 376 #size-cells = <1>; 377 mux-controls = <&hbmc_mux 0>; 378 status = "disabled"; 379 }; 380 381 ospi0: spi@47040000 { 382 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 383 reg = <0x0 0x47040000 0x0 0x100>, 384 <0x5 0x00000000 0x1 0x0000000>; 385 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 386 cdns,fifo-depth = <256>; 387 cdns,fifo-width = <4>; 388 cdns,trigger-address = <0x0>; 389 clocks = <&k3_clks 103 0>; 390 assigned-clocks = <&k3_clks 103 0>; 391 assigned-clock-parents = <&k3_clks 103 2>; 392 assigned-clock-rates = <166666666>; 393 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 status = "disabled"; 397 }; 398 399 ospi1: spi@47050000 { 400 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 401 reg = <0x0 0x47050000 0x0 0x100>, 402 <0x7 0x00000000 0x1 0x00000000>; 403 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 404 cdns,fifo-depth = <256>; 405 cdns,fifo-width = <4>; 406 cdns,trigger-address = <0x0>; 407 clocks = <&k3_clks 104 0>; 408 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 }; 414 415 tscadc0: tscadc@40200000 { 416 compatible = "ti,am3359-tscadc"; 417 reg = <0x0 0x40200000 0x0 0x1000>; 418 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 419 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 0 1>; 421 assigned-clocks = <&k3_clks 0 3>; 422 assigned-clock-rates = <60000000>; 423 clock-names = "fck"; 424 dmas = <&main_udmap 0x7400>, 425 <&main_udmap 0x7401>; 426 dma-names = "fifo0", "fifo1"; 427 status = "disabled"; 428 429 adc { 430 #io-channel-cells = <1>; 431 compatible = "ti,am3359-adc"; 432 }; 433 }; 434 435 tscadc1: tscadc@40210000 { 436 compatible = "ti,am3359-tscadc"; 437 reg = <0x0 0x40210000 0x0 0x1000>; 438 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 439 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 440 clocks = <&k3_clks 1 1>; 441 assigned-clocks = <&k3_clks 1 3>; 442 assigned-clock-rates = <60000000>; 443 clock-names = "fck"; 444 dmas = <&main_udmap 0x7402>, 445 <&main_udmap 0x7403>; 446 dma-names = "fifo0", "fifo1"; 447 status = "disabled"; 448 449 adc { 450 #io-channel-cells = <1>; 451 compatible = "ti,am3359-adc"; 452 }; 453 }; 454 455 mcu_navss: bus@28380000 { 456 compatible = "simple-bus"; 457 #address-cells = <2>; 458 #size-cells = <2>; 459 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 460 dma-coherent; 461 dma-ranges; 462 463 ti,sci-dev-id = <232>; 464 465 mcu_ringacc: ringacc@2b800000 { 466 compatible = "ti,am654-navss-ringacc"; 467 reg = <0x0 0x2b800000 0x0 0x400000>, 468 <0x0 0x2b000000 0x0 0x400000>, 469 <0x0 0x28590000 0x0 0x100>, 470 <0x0 0x2a500000 0x0 0x40000>, 471 <0x0 0x28440000 0x0 0x40000>; 472 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 473 ti,num-rings = <286>; 474 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 475 ti,sci = <&dmsc>; 476 ti,sci-dev-id = <235>; 477 msi-parent = <&main_udmass_inta>; 478 }; 479 480 mcu_udmap: dma-controller@285c0000 { 481 compatible = "ti,j721e-navss-mcu-udmap"; 482 reg = <0x0 0x285c0000 0x0 0x100>, 483 <0x0 0x2a800000 0x0 0x40000>, 484 <0x0 0x2aa00000 0x0 0x40000>, 485 <0x0 0x284a0000 0x0 0x4000>, 486 <0x0 0x284c0000 0x0 0x4000>, 487 <0x0 0x28400000 0x0 0x2000>; 488 reg-names = "gcfg", "rchanrt", "tchanrt", 489 "tchan", "rchan", "rflow"; 490 msi-parent = <&main_udmass_inta>; 491 #dma-cells = <1>; 492 493 ti,sci = <&dmsc>; 494 ti,sci-dev-id = <236>; 495 ti,ringacc = <&mcu_ringacc>; 496 497 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 498 <0x0f>; /* TX_HCHAN */ 499 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 500 <0x0b>; /* RX_HCHAN */ 501 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 502 }; 503 }; 504 505 secure_proxy_mcu: mailbox@2a480000 { 506 compatible = "ti,am654-secure-proxy"; 507 #mbox-cells = <1>; 508 reg-names = "target_data", "rt", "scfg"; 509 reg = <0x0 0x2a480000 0x0 0x80000>, 510 <0x0 0x2a380000 0x0 0x80000>, 511 <0x0 0x2a400000 0x0 0x80000>; 512 /* 513 * Marked Disabled: 514 * Node is incomplete as it is meant for bootloaders and 515 * firmware on non-MPU processors 516 */ 517 status = "disabled"; 518 }; 519 520 mcu_cpsw: ethernet@46000000 { 521 compatible = "ti,j721e-cpsw-nuss"; 522 #address-cells = <2>; 523 #size-cells = <2>; 524 reg = <0x0 0x46000000 0x0 0x200000>; 525 reg-names = "cpsw_nuss"; 526 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 527 dma-coherent; 528 clocks = <&k3_clks 18 22>; 529 clock-names = "fck"; 530 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 531 532 dmas = <&mcu_udmap 0xf000>, 533 <&mcu_udmap 0xf001>, 534 <&mcu_udmap 0xf002>, 535 <&mcu_udmap 0xf003>, 536 <&mcu_udmap 0xf004>, 537 <&mcu_udmap 0xf005>, 538 <&mcu_udmap 0xf006>, 539 <&mcu_udmap 0xf007>, 540 <&mcu_udmap 0x7000>; 541 dma-names = "tx0", "tx1", "tx2", "tx3", 542 "tx4", "tx5", "tx6", "tx7", 543 "rx"; 544 545 ethernet-ports { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 cpsw_port1: port@1 { 550 reg = <1>; 551 ti,mac-only; 552 label = "port1"; 553 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 554 phys = <&phy_gmii_sel 1>; 555 }; 556 }; 557 558 davinci_mdio: mdio@f00 { 559 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 560 reg = <0x0 0xf00 0x0 0x100>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 clocks = <&k3_clks 18 22>; 564 clock-names = "fck"; 565 bus_freq = <1000000>; 566 }; 567 568 cpts@3d000 { 569 compatible = "ti,am65-cpts"; 570 reg = <0x0 0x3d000 0x0 0x400>; 571 clocks = <&k3_clks 18 2>; 572 clock-names = "cpts"; 573 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "cpts"; 575 ti,cpts-ext-ts-inputs = <4>; 576 ti,cpts-periodic-outputs = <2>; 577 }; 578 }; 579 580 mcu_r5fss0: r5fss@41000000 { 581 compatible = "ti,j721e-r5fss"; 582 ti,cluster-mode = <1>; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 ranges = <0x41000000 0x00 0x41000000 0x20000>, 586 <0x41400000 0x00 0x41400000 0x20000>; 587 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 588 589 mcu_r5fss0_core0: r5f@41000000 { 590 compatible = "ti,j721e-r5f"; 591 reg = <0x41000000 0x00008000>, 592 <0x41010000 0x00008000>; 593 reg-names = "atcm", "btcm"; 594 ti,sci = <&dmsc>; 595 ti,sci-dev-id = <250>; 596 ti,sci-proc-ids = <0x01 0xff>; 597 resets = <&k3_reset 250 1>; 598 firmware-name = "j7-mcu-r5f0_0-fw"; 599 ti,atcm-enable = <1>; 600 ti,btcm-enable = <1>; 601 ti,loczrama = <1>; 602 }; 603 604 mcu_r5fss0_core1: r5f@41400000 { 605 compatible = "ti,j721e-r5f"; 606 reg = <0x41400000 0x00008000>, 607 <0x41410000 0x00008000>; 608 reg-names = "atcm", "btcm"; 609 ti,sci = <&dmsc>; 610 ti,sci-dev-id = <251>; 611 ti,sci-proc-ids = <0x02 0xff>; 612 resets = <&k3_reset 251 1>; 613 firmware-name = "j7-mcu-r5f0_1-fw"; 614 ti,atcm-enable = <1>; 615 ti,btcm-enable = <1>; 616 ti,loczrama = <1>; 617 }; 618 }; 619 620 mcu_mcan0: can@40528000 { 621 compatible = "bosch,m_can"; 622 reg = <0x00 0x40528000 0x00 0x200>, 623 <0x00 0x40500000 0x00 0x8000>; 624 reg-names = "m_can", "message_ram"; 625 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 626 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; 627 clock-names = "hclk", "cclk"; 628 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 630 interrupt-names = "int0", "int1"; 631 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 632 status = "disabled"; 633 }; 634 635 mcu_mcan1: can@40568000 { 636 compatible = "bosch,m_can"; 637 reg = <0x00 0x40568000 0x00 0x200>, 638 <0x00 0x40540000 0x00 0x8000>; 639 reg-names = "m_can", "message_ram"; 640 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 641 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; 642 clock-names = "hclk", "cclk"; 643 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "int0", "int1"; 646 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 647 status = "disabled"; 648 }; 649 650 mcu_spi0: spi@40300000 { 651 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 652 reg = <0x00 0x040300000 0x00 0x400>; 653 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 657 clocks = <&k3_clks 274 0>; 658 status = "disabled"; 659 }; 660 661 mcu_spi1: spi@40310000 { 662 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 663 reg = <0x00 0x040310000 0x00 0x400>; 664 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 668 clocks = <&k3_clks 275 0>; 669 status = "disabled"; 670 }; 671 672 mcu_spi2: spi@40320000 { 673 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 674 reg = <0x00 0x040320000 0x00 0x400>; 675 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 679 clocks = <&k3_clks 276 0>; 680 status = "disabled"; 681 }; 682 683 wkup_vtm0: temperature-sensor@42040000 { 684 compatible = "ti,j721e-vtm"; 685 reg = <0x00 0x42040000 0x00 0x350>, 686 <0x00 0x42050000 0x00 0x350>, 687 <0x00 0x43000300 0x00 0x10>; 688 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 689 #thermal-sensor-cells = <1>; 690 }; 691 692 mcu_esm: esm@40800000 { 693 compatible = "ti,j721e-esm"; 694 reg = <0x00 0x40800000 0x00 0x1000>; 695 ti,esm-pins = <95>; 696 bootph-pre-ram; 697 }; 698}; 699