1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x0 0x40f00000 0x0 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 wkup_conf: bus@43000000 { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges = <0x0 0x00 0x43000000 0x20000>; 56 57 chipid: chipid@14 { 58 compatible = "ti,am654-chipid"; 59 reg = <0x14 0x4>; 60 }; 61 }; 62 63 wkup_pmx0: pinctrl@4301c000 { 64 compatible = "pinctrl-single"; 65 /* Proxy 0 addressing */ 66 reg = <0x00 0x4301c000 0x00 0x178>; 67 #pinctrl-cells = <1>; 68 pinctrl-single,register-width = <32>; 69 pinctrl-single,function-mask = <0xffffffff>; 70 }; 71 72 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 73 mcu_timerio_input: pinctrl@40f04200 { 74 compatible = "pinctrl-single"; 75 reg = <0x00 0x40f04200 0x00 0x28>; 76 #pinctrl-cells = <1>; 77 pinctrl-single,register-width = <32>; 78 pinctrl-single,function-mask = <0x0000000f>; 79 /* Non-MPU Firmware usage */ 80 status = "reserved"; 81 }; 82 83 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 84 mcu_timerio_output: pinctrl@40f04280 { 85 compatible = "pinctrl-single"; 86 reg = <0x00 0x40f04280 0x00 0x28>; 87 #pinctrl-cells = <1>; 88 pinctrl-single,register-width = <32>; 89 pinctrl-single,function-mask = <0x0000000f>; 90 /* Non-MPU Firmware usage */ 91 status = "reserved"; 92 }; 93 94 mcu_ram: sram@41c00000 { 95 compatible = "mmio-sram"; 96 reg = <0x00 0x41c00000 0x00 0x100000>; 97 ranges = <0x0 0x00 0x41c00000 0x100000>; 98 #address-cells = <1>; 99 #size-cells = <1>; 100 }; 101 102 mcu_timer0: timer@40400000 { 103 compatible = "ti,am654-timer"; 104 reg = <0x00 0x40400000 0x00 0x400>; 105 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&k3_clks 35 1>; 107 clock-names = "fck"; 108 assigned-clocks = <&k3_clks 35 1>; 109 assigned-clock-parents = <&k3_clks 35 2>; 110 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 111 ti,timer-pwm; 112 /* Non-MPU Firmware usage */ 113 status = "reserved"; 114 }; 115 116 mcu_timer1: timer@40410000 { 117 compatible = "ti,am654-timer"; 118 reg = <0x00 0x40410000 0x00 0x400>; 119 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&k3_clks 71 1>; 121 clock-names = "fck"; 122 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; 123 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; 124 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 125 ti,timer-pwm; 126 /* Non-MPU Firmware usage */ 127 status = "reserved"; 128 }; 129 130 mcu_timer2: timer@40420000 { 131 compatible = "ti,am654-timer"; 132 reg = <0x00 0x40420000 0x00 0x400>; 133 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&k3_clks 72 1>; 135 clock-names = "fck"; 136 assigned-clocks = <&k3_clks 72 1>; 137 assigned-clock-parents = <&k3_clks 72 2>; 138 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 139 ti,timer-pwm; 140 /* Non-MPU Firmware usage */ 141 status = "reserved"; 142 }; 143 144 mcu_timer3: timer@40430000 { 145 compatible = "ti,am654-timer"; 146 reg = <0x00 0x40430000 0x00 0x400>; 147 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&k3_clks 73 1>; 149 clock-names = "fck"; 150 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; 151 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; 152 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 153 ti,timer-pwm; 154 /* Non-MPU Firmware usage */ 155 status = "reserved"; 156 }; 157 158 mcu_timer4: timer@40440000 { 159 compatible = "ti,am654-timer"; 160 reg = <0x00 0x40440000 0x00 0x400>; 161 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&k3_clks 74 1>; 163 clock-names = "fck"; 164 assigned-clocks = <&k3_clks 74 1>; 165 assigned-clock-parents = <&k3_clks 74 2>; 166 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 167 ti,timer-pwm; 168 /* Non-MPU Firmware usage */ 169 status = "reserved"; 170 }; 171 172 mcu_timer5: timer@40450000 { 173 compatible = "ti,am654-timer"; 174 reg = <0x00 0x40450000 0x00 0x400>; 175 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&k3_clks 75 1>; 177 clock-names = "fck"; 178 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; 179 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; 180 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 181 ti,timer-pwm; 182 /* Non-MPU Firmware usage */ 183 status = "reserved"; 184 }; 185 186 mcu_timer6: timer@40460000 { 187 compatible = "ti,am654-timer"; 188 reg = <0x00 0x40460000 0x00 0x400>; 189 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&k3_clks 76 1>; 191 clock-names = "fck"; 192 assigned-clocks = <&k3_clks 76 1>; 193 assigned-clock-parents = <&k3_clks 76 2>; 194 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 195 ti,timer-pwm; 196 /* Non-MPU Firmware usage */ 197 status = "reserved"; 198 }; 199 200 mcu_timer7: timer@40470000 { 201 compatible = "ti,am654-timer"; 202 reg = <0x00 0x40470000 0x00 0x400>; 203 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&k3_clks 77 1>; 205 clock-names = "fck"; 206 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; 207 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; 208 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 209 ti,timer-pwm; 210 /* Non-MPU Firmware usage */ 211 status = "reserved"; 212 }; 213 214 mcu_timer8: timer@40480000 { 215 compatible = "ti,am654-timer"; 216 reg = <0x00 0x40480000 0x00 0x400>; 217 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&k3_clks 78 1>; 219 clock-names = "fck"; 220 assigned-clocks = <&k3_clks 78 1>; 221 assigned-clock-parents = <&k3_clks 78 2>; 222 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 223 ti,timer-pwm; 224 /* Non-MPU Firmware usage */ 225 status = "reserved"; 226 }; 227 228 mcu_timer9: timer@40490000 { 229 compatible = "ti,am654-timer"; 230 reg = <0x00 0x40490000 0x00 0x400>; 231 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&k3_clks 79 1>; 233 clock-names = "fck"; 234 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; 235 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; 236 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 237 ti,timer-pwm; 238 /* Non-MPU Firmware usage */ 239 status = "reserved"; 240 }; 241 wkup_uart0: serial@42300000 { 242 compatible = "ti,j721e-uart", "ti,am654-uart"; 243 reg = <0x00 0x42300000 0x00 0x100>; 244 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 245 clock-frequency = <48000000>; 246 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 247 clocks = <&k3_clks 287 0>; 248 clock-names = "fclk"; 249 status = "disabled"; 250 }; 251 252 mcu_uart0: serial@40a00000 { 253 compatible = "ti,j721e-uart", "ti,am654-uart"; 254 reg = <0x00 0x40a00000 0x00 0x100>; 255 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 256 clock-frequency = <96000000>; 257 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 258 clocks = <&k3_clks 149 0>; 259 clock-names = "fclk"; 260 status = "disabled"; 261 }; 262 263 wkup_gpio_intr: interrupt-controller@42200000 { 264 compatible = "ti,sci-intr"; 265 reg = <0x00 0x42200000 0x00 0x400>; 266 ti,intr-trigger-type = <1>; 267 interrupt-controller; 268 interrupt-parent = <&gic500>; 269 #interrupt-cells = <1>; 270 ti,sci = <&dmsc>; 271 ti,sci-dev-id = <137>; 272 ti,interrupt-ranges = <16 960 16>; 273 }; 274 275 wkup_gpio0: gpio@42110000 { 276 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 277 reg = <0x0 0x42110000 0x0 0x100>; 278 gpio-controller; 279 #gpio-cells = <2>; 280 interrupt-parent = <&wkup_gpio_intr>; 281 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 ti,ngpio = <84>; 285 ti,davinci-gpio-unbanked = <0>; 286 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 287 clocks = <&k3_clks 113 0>; 288 clock-names = "gpio"; 289 status = "disabled"; 290 }; 291 292 wkup_gpio1: gpio@42100000 { 293 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 294 reg = <0x0 0x42100000 0x0 0x100>; 295 gpio-controller; 296 #gpio-cells = <2>; 297 interrupt-parent = <&wkup_gpio_intr>; 298 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 299 interrupt-controller; 300 #interrupt-cells = <2>; 301 ti,ngpio = <84>; 302 ti,davinci-gpio-unbanked = <0>; 303 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 304 clocks = <&k3_clks 114 0>; 305 clock-names = "gpio"; 306 status = "disabled"; 307 }; 308 309 mcu_i2c0: i2c@40b00000 { 310 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 311 reg = <0x0 0x40b00000 0x0 0x100>; 312 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 clock-names = "fck"; 316 clocks = <&k3_clks 194 0>; 317 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 318 status = "disabled"; 319 }; 320 321 mcu_i2c1: i2c@40b10000 { 322 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 323 reg = <0x0 0x40b10000 0x0 0x100>; 324 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 clock-names = "fck"; 328 clocks = <&k3_clks 195 0>; 329 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 330 status = "disabled"; 331 }; 332 333 wkup_i2c0: i2c@42120000 { 334 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 335 reg = <0x0 0x42120000 0x0 0x100>; 336 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 clock-names = "fck"; 340 clocks = <&k3_clks 197 0>; 341 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 342 status = "disabled"; 343 }; 344 345 fss: bus@47000000 { 346 compatible = "simple-bus"; 347 #address-cells = <2>; 348 #size-cells = <2>; 349 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 350 <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */ 351 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 352 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ 353 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* HBMC/OSPI0 Memory */ 354 <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ 355 356 hbmc_mux: mux-controller@47000004 { 357 compatible = "reg-mux"; 358 reg = <0x00 0x47000004 0x00 0x4>; 359 #mux-control-cells = <1>; 360 mux-reg-masks = <0x0 0x2>; /* HBMC select */ 361 }; 362 363 hbmc: hyperbus@47034000 { 364 compatible = "ti,am654-hbmc"; 365 reg = <0x00 0x47034000 0x00 0x100>, 366 <0x05 0x00000000 0x01 0x0000000>; 367 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 368 clocks = <&k3_clks 102 0>; 369 assigned-clocks = <&k3_clks 102 5>; 370 assigned-clock-rates = <333333333>; 371 #address-cells = <2>; 372 #size-cells = <1>; 373 mux-controls = <&hbmc_mux 0>; 374 status = "disabled"; 375 }; 376 377 ospi0: spi@47040000 { 378 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 379 reg = <0x0 0x47040000 0x0 0x100>, 380 <0x5 0x00000000 0x1 0x0000000>; 381 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 382 cdns,fifo-depth = <256>; 383 cdns,fifo-width = <4>; 384 cdns,trigger-address = <0x0>; 385 clocks = <&k3_clks 103 0>; 386 assigned-clocks = <&k3_clks 103 0>; 387 assigned-clock-parents = <&k3_clks 103 2>; 388 assigned-clock-rates = <166666666>; 389 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 status = "disabled"; 393 }; 394 395 ospi1: spi@47050000 { 396 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 397 reg = <0x0 0x47050000 0x0 0x100>, 398 <0x7 0x00000000 0x1 0x00000000>; 399 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 400 cdns,fifo-depth = <256>; 401 cdns,fifo-width = <4>; 402 cdns,trigger-address = <0x0>; 403 clocks = <&k3_clks 104 0>; 404 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 }; 410 411 tscadc0: tscadc@40200000 { 412 compatible = "ti,am3359-tscadc"; 413 reg = <0x0 0x40200000 0x0 0x1000>; 414 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 415 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 0 1>; 417 assigned-clocks = <&k3_clks 0 3>; 418 assigned-clock-rates = <60000000>; 419 clock-names = "fck"; 420 dmas = <&main_udmap 0x7400>, 421 <&main_udmap 0x7401>; 422 dma-names = "fifo0", "fifo1"; 423 status = "disabled"; 424 425 adc { 426 #io-channel-cells = <1>; 427 compatible = "ti,am3359-adc"; 428 }; 429 }; 430 431 tscadc1: tscadc@40210000 { 432 compatible = "ti,am3359-tscadc"; 433 reg = <0x0 0x40210000 0x0 0x1000>; 434 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 435 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 436 clocks = <&k3_clks 1 1>; 437 assigned-clocks = <&k3_clks 1 3>; 438 assigned-clock-rates = <60000000>; 439 clock-names = "fck"; 440 dmas = <&main_udmap 0x7402>, 441 <&main_udmap 0x7403>; 442 dma-names = "fifo0", "fifo1"; 443 status = "disabled"; 444 445 adc { 446 #io-channel-cells = <1>; 447 compatible = "ti,am3359-adc"; 448 }; 449 }; 450 451 mcu_navss: bus@28380000 { 452 compatible = "simple-bus"; 453 #address-cells = <2>; 454 #size-cells = <2>; 455 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 456 dma-coherent; 457 dma-ranges; 458 459 ti,sci-dev-id = <232>; 460 461 mcu_ringacc: ringacc@2b800000 { 462 compatible = "ti,am654-navss-ringacc"; 463 reg = <0x0 0x2b800000 0x0 0x400000>, 464 <0x0 0x2b000000 0x0 0x400000>, 465 <0x0 0x28590000 0x0 0x100>, 466 <0x0 0x2a500000 0x0 0x40000>, 467 <0x0 0x28440000 0x0 0x40000>; 468 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 469 ti,num-rings = <286>; 470 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 471 ti,sci = <&dmsc>; 472 ti,sci-dev-id = <235>; 473 msi-parent = <&main_udmass_inta>; 474 }; 475 476 mcu_udmap: dma-controller@285c0000 { 477 compatible = "ti,j721e-navss-mcu-udmap"; 478 reg = <0x0 0x285c0000 0x0 0x100>, 479 <0x0 0x2a800000 0x0 0x40000>, 480 <0x0 0x2aa00000 0x0 0x40000>, 481 <0x0 0x284a0000 0x0 0x4000>, 482 <0x0 0x284c0000 0x0 0x4000>, 483 <0x0 0x28400000 0x0 0x2000>; 484 reg-names = "gcfg", "rchanrt", "tchanrt", 485 "tchan", "rchan", "rflow"; 486 msi-parent = <&main_udmass_inta>; 487 #dma-cells = <1>; 488 489 ti,sci = <&dmsc>; 490 ti,sci-dev-id = <236>; 491 ti,ringacc = <&mcu_ringacc>; 492 493 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 494 <0x0f>; /* TX_HCHAN */ 495 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 496 <0x0b>; /* RX_HCHAN */ 497 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 498 }; 499 }; 500 501 secure_proxy_mcu: mailbox@2a480000 { 502 compatible = "ti,am654-secure-proxy"; 503 #mbox-cells = <1>; 504 reg-names = "target_data", "rt", "scfg"; 505 reg = <0x0 0x2a480000 0x0 0x80000>, 506 <0x0 0x2a380000 0x0 0x80000>, 507 <0x0 0x2a400000 0x0 0x80000>; 508 /* 509 * Marked Disabled: 510 * Node is incomplete as it is meant for bootloaders and 511 * firmware on non-MPU processors 512 */ 513 status = "disabled"; 514 }; 515 516 mcu_cpsw: ethernet@46000000 { 517 compatible = "ti,j721e-cpsw-nuss"; 518 #address-cells = <2>; 519 #size-cells = <2>; 520 reg = <0x0 0x46000000 0x0 0x200000>; 521 reg-names = "cpsw_nuss"; 522 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 523 dma-coherent; 524 clocks = <&k3_clks 18 22>; 525 clock-names = "fck"; 526 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 527 528 dmas = <&mcu_udmap 0xf000>, 529 <&mcu_udmap 0xf001>, 530 <&mcu_udmap 0xf002>, 531 <&mcu_udmap 0xf003>, 532 <&mcu_udmap 0xf004>, 533 <&mcu_udmap 0xf005>, 534 <&mcu_udmap 0xf006>, 535 <&mcu_udmap 0xf007>, 536 <&mcu_udmap 0x7000>; 537 dma-names = "tx0", "tx1", "tx2", "tx3", 538 "tx4", "tx5", "tx6", "tx7", 539 "rx"; 540 541 ethernet-ports { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 545 cpsw_port1: port@1 { 546 reg = <1>; 547 ti,mac-only; 548 label = "port1"; 549 ti,syscon-efuse = <&mcu_conf 0x200>; 550 phys = <&phy_gmii_sel 1>; 551 }; 552 }; 553 554 davinci_mdio: mdio@f00 { 555 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 556 reg = <0x0 0xf00 0x0 0x100>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 clocks = <&k3_clks 18 22>; 560 clock-names = "fck"; 561 bus_freq = <1000000>; 562 }; 563 564 cpts@3d000 { 565 compatible = "ti,am65-cpts"; 566 reg = <0x0 0x3d000 0x0 0x400>; 567 clocks = <&k3_clks 18 2>; 568 clock-names = "cpts"; 569 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 570 interrupt-names = "cpts"; 571 ti,cpts-ext-ts-inputs = <4>; 572 ti,cpts-periodic-outputs = <2>; 573 }; 574 }; 575 576 mcu_r5fss0: r5fss@41000000 { 577 compatible = "ti,j721e-r5fss"; 578 ti,cluster-mode = <1>; 579 #address-cells = <1>; 580 #size-cells = <1>; 581 ranges = <0x41000000 0x00 0x41000000 0x20000>, 582 <0x41400000 0x00 0x41400000 0x20000>; 583 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 584 585 mcu_r5fss0_core0: r5f@41000000 { 586 compatible = "ti,j721e-r5f"; 587 reg = <0x41000000 0x00008000>, 588 <0x41010000 0x00008000>; 589 reg-names = "atcm", "btcm"; 590 ti,sci = <&dmsc>; 591 ti,sci-dev-id = <250>; 592 ti,sci-proc-ids = <0x01 0xff>; 593 resets = <&k3_reset 250 1>; 594 firmware-name = "j7-mcu-r5f0_0-fw"; 595 ti,atcm-enable = <1>; 596 ti,btcm-enable = <1>; 597 ti,loczrama = <1>; 598 }; 599 600 mcu_r5fss0_core1: r5f@41400000 { 601 compatible = "ti,j721e-r5f"; 602 reg = <0x41400000 0x00008000>, 603 <0x41410000 0x00008000>; 604 reg-names = "atcm", "btcm"; 605 ti,sci = <&dmsc>; 606 ti,sci-dev-id = <251>; 607 ti,sci-proc-ids = <0x02 0xff>; 608 resets = <&k3_reset 251 1>; 609 firmware-name = "j7-mcu-r5f0_1-fw"; 610 ti,atcm-enable = <1>; 611 ti,btcm-enable = <1>; 612 ti,loczrama = <1>; 613 }; 614 }; 615 616 mcu_mcan0: can@40528000 { 617 compatible = "bosch,m_can"; 618 reg = <0x00 0x40528000 0x00 0x200>, 619 <0x00 0x40500000 0x00 0x8000>; 620 reg-names = "m_can", "message_ram"; 621 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 622 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; 623 clock-names = "hclk", "cclk"; 624 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "int0", "int1"; 627 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 628 status = "disabled"; 629 }; 630 631 mcu_mcan1: can@40568000 { 632 compatible = "bosch,m_can"; 633 reg = <0x00 0x40568000 0x00 0x200>, 634 <0x00 0x40540000 0x00 0x8000>; 635 reg-names = "m_can", "message_ram"; 636 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 637 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; 638 clock-names = "hclk", "cclk"; 639 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 641 interrupt-names = "int0", "int1"; 642 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 643 status = "disabled"; 644 }; 645 646 mcu_spi0: spi@40300000 { 647 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 648 reg = <0x00 0x040300000 0x00 0x400>; 649 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 653 clocks = <&k3_clks 274 0>; 654 status = "disabled"; 655 }; 656 657 mcu_spi1: spi@40310000 { 658 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 659 reg = <0x00 0x040310000 0x00 0x400>; 660 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 664 clocks = <&k3_clks 275 0>; 665 status = "disabled"; 666 }; 667 668 mcu_spi2: spi@40320000 { 669 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 670 reg = <0x00 0x040320000 0x00 0x400>; 671 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 675 clocks = <&k3_clks 276 0>; 676 status = "disabled"; 677 }; 678 679 wkup_vtm0: temperature-sensor@42040000 { 680 compatible = "ti,j721e-vtm"; 681 reg = <0x00 0x42040000 0x00 0x350>, 682 <0x00 0x42050000 0x00 0x350>, 683 <0x00 0x43000300 0x00 0x10>; 684 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 685 #thermal-sensor-cells = <1>; 686 }; 687 688 mcu_esm: esm@40800000 { 689 compatible = "ti,j721e-esm"; 690 reg = <0x00 0x40800000 0x00 0x1000>; 691 ti,esm-pins = <95>; 692 bootph-pre-ram; 693 }; 694}; 695