1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 bootph-all; 25 }; 26 27 k3_clks: clock-controller { 28 compatible = "ti,k2g-sci-clk"; 29 #clock-cells = <2>; 30 bootph-all; 31 }; 32 33 k3_reset: reset-controller { 34 compatible = "ti,sci-reset"; 35 #reset-cells = <2>; 36 bootph-all; 37 }; 38 }; 39 40 mcu_conf: bus@40f00000 { 41 compatible = "simple-bus"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x0 0x0 0x40f00000 0x20000>; 45 46 cpsw_mac_syscon: ethernet-mac-syscon@200 { 47 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 48 reg = <0x200 0x8>; 49 }; 50 51 phy_gmii_sel: phy@4040 { 52 compatible = "ti,am654-phy-gmii-sel"; 53 reg = <0x4040 0x4>; 54 #phy-cells = <1>; 55 }; 56 }; 57 58 wkup_conf: bus@43000000 { 59 compatible = "simple-bus"; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges = <0x0 0x00 0x43000000 0x20000>; 63 64 chipid: chipid@14 { 65 compatible = "ti,am654-chipid"; 66 reg = <0x14 0x4>; 67 bootph-all; 68 }; 69 }; 70 71 wkup_pmx0: pinctrl@4301c000 { 72 compatible = "pinctrl-single"; 73 /* Proxy 0 addressing */ 74 reg = <0x00 0x4301c000 0x00 0x178>; 75 #pinctrl-cells = <1>; 76 pinctrl-single,register-width = <32>; 77 pinctrl-single,function-mask = <0xffffffff>; 78 }; 79 80 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 81 mcu_timerio_input: pinctrl@40f04200 { 82 compatible = "pinctrl-single"; 83 reg = <0x00 0x40f04200 0x00 0x28>; 84 #pinctrl-cells = <1>; 85 pinctrl-single,register-width = <32>; 86 pinctrl-single,function-mask = <0x0000000f>; 87 /* Non-MPU Firmware usage */ 88 status = "reserved"; 89 }; 90 91 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 92 mcu_timerio_output: pinctrl@40f04280 { 93 compatible = "pinctrl-single"; 94 reg = <0x00 0x40f04280 0x00 0x28>; 95 #pinctrl-cells = <1>; 96 pinctrl-single,register-width = <32>; 97 pinctrl-single,function-mask = <0x0000000f>; 98 /* Non-MPU Firmware usage */ 99 status = "reserved"; 100 }; 101 102 mcu_ram: sram@41c00000 { 103 compatible = "mmio-sram"; 104 reg = <0x00 0x41c00000 0x00 0x100000>; 105 ranges = <0x0 0x00 0x41c00000 0x100000>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 }; 109 110 mcu_timer0: timer@40400000 { 111 compatible = "ti,am654-timer"; 112 reg = <0x00 0x40400000 0x00 0x400>; 113 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&k3_clks 35 1>; 115 clock-names = "fck"; 116 assigned-clocks = <&k3_clks 35 1>; 117 assigned-clock-parents = <&k3_clks 35 2>; 118 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 119 bootph-pre-ram; 120 ti,timer-pwm; 121 /* Non-MPU Firmware usage */ 122 status = "reserved"; 123 }; 124 125 mcu_timer1: timer@40410000 { 126 compatible = "ti,am654-timer"; 127 reg = <0x00 0x40410000 0x00 0x400>; 128 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&k3_clks 71 1>; 130 clock-names = "fck"; 131 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; 132 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; 133 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 134 ti,timer-pwm; 135 /* Non-MPU Firmware usage */ 136 status = "reserved"; 137 }; 138 139 mcu_timer2: timer@40420000 { 140 compatible = "ti,am654-timer"; 141 reg = <0x00 0x40420000 0x00 0x400>; 142 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&k3_clks 72 1>; 144 clock-names = "fck"; 145 assigned-clocks = <&k3_clks 72 1>; 146 assigned-clock-parents = <&k3_clks 72 2>; 147 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 148 ti,timer-pwm; 149 /* Non-MPU Firmware usage */ 150 status = "reserved"; 151 }; 152 153 mcu_timer3: timer@40430000 { 154 compatible = "ti,am654-timer"; 155 reg = <0x00 0x40430000 0x00 0x400>; 156 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&k3_clks 73 1>; 158 clock-names = "fck"; 159 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; 160 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; 161 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 162 ti,timer-pwm; 163 /* Non-MPU Firmware usage */ 164 status = "reserved"; 165 }; 166 167 mcu_timer4: timer@40440000 { 168 compatible = "ti,am654-timer"; 169 reg = <0x00 0x40440000 0x00 0x400>; 170 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&k3_clks 74 1>; 172 clock-names = "fck"; 173 assigned-clocks = <&k3_clks 74 1>; 174 assigned-clock-parents = <&k3_clks 74 2>; 175 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 176 ti,timer-pwm; 177 /* Non-MPU Firmware usage */ 178 status = "reserved"; 179 }; 180 181 mcu_timer5: timer@40450000 { 182 compatible = "ti,am654-timer"; 183 reg = <0x00 0x40450000 0x00 0x400>; 184 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&k3_clks 75 1>; 186 clock-names = "fck"; 187 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; 188 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; 189 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 190 ti,timer-pwm; 191 /* Non-MPU Firmware usage */ 192 status = "reserved"; 193 }; 194 195 mcu_timer6: timer@40460000 { 196 compatible = "ti,am654-timer"; 197 reg = <0x00 0x40460000 0x00 0x400>; 198 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&k3_clks 76 1>; 200 clock-names = "fck"; 201 assigned-clocks = <&k3_clks 76 1>; 202 assigned-clock-parents = <&k3_clks 76 2>; 203 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 204 ti,timer-pwm; 205 /* Non-MPU Firmware usage */ 206 status = "reserved"; 207 }; 208 209 mcu_timer7: timer@40470000 { 210 compatible = "ti,am654-timer"; 211 reg = <0x00 0x40470000 0x00 0x400>; 212 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&k3_clks 77 1>; 214 clock-names = "fck"; 215 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; 216 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; 217 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 218 ti,timer-pwm; 219 /* Non-MPU Firmware usage */ 220 status = "reserved"; 221 }; 222 223 mcu_timer8: timer@40480000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x40480000 0x00 0x400>; 226 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 78 1>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 78 1>; 230 assigned-clock-parents = <&k3_clks 78 2>; 231 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 /* Non-MPU Firmware usage */ 234 status = "reserved"; 235 }; 236 237 mcu_timer9: timer@40490000 { 238 compatible = "ti,am654-timer"; 239 reg = <0x00 0x40490000 0x00 0x400>; 240 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&k3_clks 79 1>; 242 clock-names = "fck"; 243 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; 244 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; 245 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 246 ti,timer-pwm; 247 /* Non-MPU Firmware usage */ 248 status = "reserved"; 249 }; 250 wkup_uart0: serial@42300000 { 251 compatible = "ti,j721e-uart", "ti,am654-uart"; 252 reg = <0x00 0x42300000 0x00 0x100>; 253 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 254 clock-frequency = <48000000>; 255 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 256 clocks = <&k3_clks 287 0>; 257 clock-names = "fclk"; 258 status = "disabled"; 259 }; 260 261 mcu_uart0: serial@40a00000 { 262 compatible = "ti,j721e-uart", "ti,am654-uart"; 263 reg = <0x00 0x40a00000 0x00 0x100>; 264 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 265 clock-frequency = <96000000>; 266 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 267 clocks = <&k3_clks 149 0>; 268 clock-names = "fclk"; 269 status = "disabled"; 270 }; 271 272 wkup_gpio_intr: interrupt-controller@42200000 { 273 compatible = "ti,sci-intr"; 274 reg = <0x00 0x42200000 0x00 0x400>; 275 ti,intr-trigger-type = <1>; 276 interrupt-controller; 277 interrupt-parent = <&gic500>; 278 #interrupt-cells = <1>; 279 ti,sci = <&dmsc>; 280 ti,sci-dev-id = <137>; 281 ti,interrupt-ranges = <16 960 16>; 282 }; 283 284 wkup_gpio0: gpio@42110000 { 285 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 286 reg = <0x0 0x42110000 0x0 0x100>; 287 gpio-controller; 288 #gpio-cells = <2>; 289 interrupt-parent = <&wkup_gpio_intr>; 290 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 ti,ngpio = <84>; 294 ti,davinci-gpio-unbanked = <0>; 295 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 296 clocks = <&k3_clks 113 0>; 297 clock-names = "gpio"; 298 status = "disabled"; 299 }; 300 301 wkup_gpio1: gpio@42100000 { 302 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 303 reg = <0x0 0x42100000 0x0 0x100>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 interrupt-parent = <&wkup_gpio_intr>; 307 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 308 interrupt-controller; 309 #interrupt-cells = <2>; 310 ti,ngpio = <84>; 311 ti,davinci-gpio-unbanked = <0>; 312 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 313 clocks = <&k3_clks 114 0>; 314 clock-names = "gpio"; 315 status = "disabled"; 316 }; 317 318 mcu_i2c0: i2c@40b00000 { 319 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 320 reg = <0x0 0x40b00000 0x0 0x100>; 321 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 clock-names = "fck"; 325 clocks = <&k3_clks 194 0>; 326 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 327 status = "disabled"; 328 }; 329 330 mcu_i2c1: i2c@40b10000 { 331 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 332 reg = <0x0 0x40b10000 0x0 0x100>; 333 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 clock-names = "fck"; 337 clocks = <&k3_clks 195 0>; 338 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 339 status = "disabled"; 340 }; 341 342 wkup_i2c0: i2c@42120000 { 343 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 344 reg = <0x0 0x42120000 0x0 0x100>; 345 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 clock-names = "fck"; 349 clocks = <&k3_clks 197 0>; 350 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 351 status = "disabled"; 352 }; 353 354 fss: bus@47000000 { 355 compatible = "simple-bus"; 356 #address-cells = <2>; 357 #size-cells = <2>; 358 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 359 <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */ 360 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 361 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ 362 <0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, /* FSS data region 1 */ 363 <0x4 0x00000000 0x4 0x00000000 0x4 0x00000000>; /* FSS data region 0/3 */ 364 365 hbmc_mux: mux-controller@47000004 { 366 compatible = "reg-mux"; 367 reg = <0x00 0x47000004 0x00 0x4>; 368 #mux-control-cells = <1>; 369 mux-reg-masks = <0x0 0x2>; /* HBMC select */ 370 bootph-all; 371 }; 372 373 hbmc: hyperbus@47034000 { 374 compatible = "ti,am654-hbmc"; 375 reg = <0x00 0x47034000 0x00 0x100>, 376 <0x05 0x00000000 0x01 0x00000000>; 377 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 378 clocks = <&k3_clks 102 0>; 379 assigned-clocks = <&k3_clks 102 5>; 380 assigned-clock-rates = <333333333>; 381 #address-cells = <2>; 382 #size-cells = <1>; 383 mux-controls = <&hbmc_mux 0>; 384 status = "disabled"; 385 }; 386 387 ospi0: spi@47040000 { 388 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 389 reg = <0x0 0x47040000 0x0 0x100>, 390 <0x5 0x00000000 0x1 0x00000000>; 391 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 392 cdns,fifo-depth = <256>; 393 cdns,fifo-width = <4>; 394 cdns,trigger-address = <0x0>; 395 clocks = <&k3_clks 103 0>; 396 assigned-clocks = <&k3_clks 103 0>; 397 assigned-clock-parents = <&k3_clks 103 2>; 398 assigned-clock-rates = <166666666>; 399 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 ospi1: spi@47050000 { 406 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 407 reg = <0x0 0x47050000 0x0 0x100>, 408 <0x7 0x00000000 0x1 0x00000000>; 409 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 410 cdns,fifo-depth = <256>; 411 cdns,fifo-width = <4>; 412 cdns,trigger-address = <0x0>; 413 clocks = <&k3_clks 104 0>; 414 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 }; 420 421 tscadc0: tscadc@40200000 { 422 compatible = "ti,am3359-tscadc"; 423 reg = <0x0 0x40200000 0x0 0x1000>; 424 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 425 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 0 1>; 427 assigned-clocks = <&k3_clks 0 3>; 428 assigned-clock-rates = <60000000>; 429 clock-names = "fck"; 430 dmas = <&main_udmap 0x7400>, 431 <&main_udmap 0x7401>; 432 dma-names = "fifo0", "fifo1"; 433 status = "disabled"; 434 435 adc { 436 #io-channel-cells = <1>; 437 compatible = "ti,am3359-adc"; 438 }; 439 }; 440 441 tscadc1: tscadc@40210000 { 442 compatible = "ti,am3359-tscadc"; 443 reg = <0x0 0x40210000 0x0 0x1000>; 444 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 445 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 1 1>; 447 assigned-clocks = <&k3_clks 1 3>; 448 assigned-clock-rates = <60000000>; 449 clock-names = "fck"; 450 dmas = <&main_udmap 0x7402>, 451 <&main_udmap 0x7403>; 452 dma-names = "fifo0", "fifo1"; 453 status = "disabled"; 454 455 adc { 456 #io-channel-cells = <1>; 457 compatible = "ti,am3359-adc"; 458 }; 459 }; 460 461 mcu_navss: bus@28380000 { 462 compatible = "simple-bus"; 463 #address-cells = <2>; 464 #size-cells = <2>; 465 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 466 dma-coherent; 467 dma-ranges; 468 469 ti,sci-dev-id = <232>; 470 471 mcu_ringacc: ringacc@2b800000 { 472 compatible = "ti,am654-navss-ringacc"; 473 reg = <0x0 0x2b800000 0x0 0x400000>, 474 <0x0 0x2b000000 0x0 0x400000>, 475 <0x0 0x28590000 0x0 0x100>, 476 <0x0 0x2a500000 0x0 0x40000>, 477 <0x0 0x28440000 0x0 0x40000>; 478 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 479 bootph-all; 480 ti,num-rings = <286>; 481 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 482 ti,sci = <&dmsc>; 483 ti,sci-dev-id = <235>; 484 msi-parent = <&main_udmass_inta>; 485 }; 486 487 mcu_udmap: dma-controller@285c0000 { 488 compatible = "ti,j721e-navss-mcu-udmap"; 489 reg = <0x0 0x285c0000 0x0 0x100>, 490 <0x0 0x2a800000 0x0 0x40000>, 491 <0x0 0x2aa00000 0x0 0x40000>, 492 <0x0 0x284a0000 0x0 0x4000>, 493 <0x0 0x284c0000 0x0 0x4000>, 494 <0x0 0x28400000 0x0 0x2000>; 495 reg-names = "gcfg", "rchanrt", "tchanrt", 496 "tchan", "rchan", "rflow"; 497 msi-parent = <&main_udmass_inta>; 498 #dma-cells = <1>; 499 bootph-all; 500 501 ti,sci = <&dmsc>; 502 ti,sci-dev-id = <236>; 503 ti,ringacc = <&mcu_ringacc>; 504 505 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 506 <0x0f>; /* TX_HCHAN */ 507 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 508 <0x0b>; /* RX_HCHAN */ 509 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 510 }; 511 }; 512 513 secure_proxy_mcu: mailbox@2a480000 { 514 compatible = "ti,am654-secure-proxy"; 515 #mbox-cells = <1>; 516 reg-names = "target_data", "rt", "scfg"; 517 reg = <0x0 0x2a480000 0x0 0x80000>, 518 <0x0 0x2a380000 0x0 0x80000>, 519 <0x0 0x2a400000 0x0 0x80000>; 520 bootph-pre-ram; 521 /* 522 * Marked Disabled: 523 * Node is incomplete as it is meant for bootloaders and 524 * firmware on non-MPU processors 525 */ 526 status = "disabled"; 527 }; 528 529 mcu_cpsw: ethernet@46000000 { 530 compatible = "ti,j721e-cpsw-nuss"; 531 #address-cells = <2>; 532 #size-cells = <2>; 533 reg = <0x0 0x46000000 0x0 0x200000>; 534 reg-names = "cpsw_nuss"; 535 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 536 dma-coherent; 537 clocks = <&k3_clks 18 22>; 538 clock-names = "fck"; 539 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 540 541 dmas = <&mcu_udmap 0xf000>, 542 <&mcu_udmap 0xf001>, 543 <&mcu_udmap 0xf002>, 544 <&mcu_udmap 0xf003>, 545 <&mcu_udmap 0xf004>, 546 <&mcu_udmap 0xf005>, 547 <&mcu_udmap 0xf006>, 548 <&mcu_udmap 0xf007>, 549 <&mcu_udmap 0x7000>; 550 dma-names = "tx0", "tx1", "tx2", "tx3", 551 "tx4", "tx5", "tx6", "tx7", 552 "rx"; 553 554 ethernet-ports { 555 #address-cells = <1>; 556 #size-cells = <0>; 557 558 cpsw_port1: port@1 { 559 reg = <1>; 560 ti,mac-only; 561 label = "port1"; 562 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 563 phys = <&phy_gmii_sel 1>; 564 }; 565 }; 566 567 davinci_mdio: mdio@f00 { 568 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 569 reg = <0x0 0xf00 0x0 0x100>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&k3_clks 18 22>; 573 clock-names = "fck"; 574 bus_freq = <1000000>; 575 }; 576 577 cpts@3d000 { 578 compatible = "ti,am65-cpts"; 579 reg = <0x0 0x3d000 0x0 0x400>; 580 clocks = <&k3_clks 18 2>; 581 clock-names = "cpts"; 582 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 583 interrupt-names = "cpts"; 584 ti,cpts-ext-ts-inputs = <4>; 585 ti,cpts-periodic-outputs = <2>; 586 }; 587 }; 588 589 mcu_r5fss0: r5fss@41000000 { 590 compatible = "ti,j721e-r5fss"; 591 ti,cluster-mode = <1>; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 ranges = <0x41000000 0x00 0x41000000 0x20000>, 595 <0x41400000 0x00 0x41400000 0x20000>; 596 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 597 598 mcu_r5fss0_core0: r5f@41000000 { 599 compatible = "ti,j721e-r5f"; 600 reg = <0x41000000 0x00008000>, 601 <0x41010000 0x00008000>; 602 reg-names = "atcm", "btcm"; 603 ti,sci = <&dmsc>; 604 ti,sci-dev-id = <250>; 605 ti,sci-proc-ids = <0x01 0xff>; 606 resets = <&k3_reset 250 1>; 607 firmware-name = "j7-mcu-r5f0_0-fw"; 608 ti,atcm-enable = <1>; 609 ti,btcm-enable = <1>; 610 ti,loczrama = <1>; 611 }; 612 613 mcu_r5fss0_core1: r5f@41400000 { 614 compatible = "ti,j721e-r5f"; 615 reg = <0x41400000 0x00008000>, 616 <0x41410000 0x00008000>; 617 reg-names = "atcm", "btcm"; 618 ti,sci = <&dmsc>; 619 ti,sci-dev-id = <251>; 620 ti,sci-proc-ids = <0x02 0xff>; 621 resets = <&k3_reset 251 1>; 622 firmware-name = "j7-mcu-r5f0_1-fw"; 623 ti,atcm-enable = <1>; 624 ti,btcm-enable = <1>; 625 ti,loczrama = <1>; 626 }; 627 }; 628 629 mcu_mcan0: can@40528000 { 630 compatible = "bosch,m_can"; 631 reg = <0x00 0x40528000 0x00 0x200>, 632 <0x00 0x40500000 0x00 0x8000>; 633 reg-names = "m_can", "message_ram"; 634 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 635 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; 636 clock-names = "hclk", "cclk"; 637 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 639 interrupt-names = "int0", "int1"; 640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 641 status = "disabled"; 642 }; 643 644 mcu_mcan1: can@40568000 { 645 compatible = "bosch,m_can"; 646 reg = <0x00 0x40568000 0x00 0x200>, 647 <0x00 0x40540000 0x00 0x8000>; 648 reg-names = "m_can", "message_ram"; 649 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 650 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; 651 clock-names = "hclk", "cclk"; 652 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "int0", "int1"; 655 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 656 status = "disabled"; 657 }; 658 659 mcu_spi0: spi@40300000 { 660 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 661 reg = <0x00 0x040300000 0x00 0x400>; 662 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 666 clocks = <&k3_clks 274 1>; 667 status = "disabled"; 668 }; 669 670 mcu_spi1: spi@40310000 { 671 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 672 reg = <0x00 0x040310000 0x00 0x400>; 673 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 677 clocks = <&k3_clks 275 1>; 678 status = "disabled"; 679 }; 680 681 mcu_spi2: spi@40320000 { 682 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 683 reg = <0x00 0x040320000 0x00 0x400>; 684 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 688 clocks = <&k3_clks 276 1>; 689 status = "disabled"; 690 }; 691 692 wkup_vtm0: temperature-sensor@42040000 { 693 compatible = "ti,j721e-vtm"; 694 reg = <0x00 0x42040000 0x00 0x350>, 695 <0x00 0x42050000 0x00 0x350>, 696 <0x00 0x43000300 0x00 0x10>; 697 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 698 #thermal-sensor-cells = <1>; 699 bootph-pre-ram; 700 }; 701 702 mcu_esm: esm@40800000 { 703 compatible = "ti,j721e-esm"; 704 reg = <0x00 0x40800000 0x00 0x1000>; 705 ti,esm-pins = <95>; 706 bootph-pre-ram; 707 }; 708}; 709