1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10 11#include "k3-serdes.h" 12 13/ { 14 cmn_refclk: clock-cmnrefclk { 15 #clock-cells = <0>; 16 compatible = "fixed-clock"; 17 clock-frequency = <0>; 18 }; 19 20 cmn_refclk1: clock-cmnrefclk1 { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <0>; 24 }; 25}; 26 27&cbass_main { 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x0 0x70000000 0x0 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x0 0x0 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x0 0x20000>; 37 }; 38 }; 39 40 scm_conf: scm-conf@100000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x00100000 0x1c000>; 46 47 pcie0_ctrl: pcie-ctrl@4070 { 48 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 49 reg = <0x4070 0x4>; 50 }; 51 52 pcie1_ctrl: pcie-ctrl@4074 { 53 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 54 reg = <0x4074 0x4>; 55 }; 56 57 pcie2_ctrl: pcie-ctrl@4078 { 58 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 59 reg = <0x4078 0x4>; 60 }; 61 62 pcie3_ctrl: pcie-ctrl@407c { 63 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 64 reg = <0x407c 0x4>; 65 }; 66 67 serdes_ln_ctrl: mux-controller@4080 { 68 compatible = "reg-mux"; 69 reg = <0x4080 0x50>; 70 #mux-control-cells = <1>; 71 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 72 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 73 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 74 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ 75 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ 76 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ 77 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 78 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 79 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 80 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 81 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 82 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 83 }; 84 85 cpsw0_phy_gmii_sel: phy@4044 { 86 compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 87 ti,qsgmii-main-ports = <2>, <2>; 88 reg = <0x4044 0x20>; 89 #phy-cells = <1>; 90 }; 91 92 usb_serdes_mux: mux-controller@4000 { 93 compatible = "reg-mux"; 94 reg = <0x4000 0x20>; 95 #mux-control-cells = <1>; 96 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ 97 <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ 98 }; 99 100 ehrpwm_tbclk: clock-controller@4140 { 101 compatible = "ti,am654-ehrpwm-tbclk"; 102 reg = <0x4140 0x18>; 103 #clock-cells = <1>; 104 }; 105 }; 106 107 main_ehrpwm0: pwm@3000000 { 108 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 109 #pwm-cells = <3>; 110 reg = <0x00 0x3000000 0x00 0x100>; 111 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 112 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 113 clock-names = "tbclk", "fck"; 114 status = "disabled"; 115 }; 116 117 main_ehrpwm1: pwm@3010000 { 118 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 119 #pwm-cells = <3>; 120 reg = <0x00 0x3010000 0x00 0x100>; 121 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 123 clock-names = "tbclk", "fck"; 124 status = "disabled"; 125 }; 126 127 main_ehrpwm2: pwm@3020000 { 128 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 129 #pwm-cells = <3>; 130 reg = <0x00 0x3020000 0x00 0x100>; 131 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 132 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 133 clock-names = "tbclk", "fck"; 134 status = "disabled"; 135 }; 136 137 main_ehrpwm3: pwm@3030000 { 138 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 139 #pwm-cells = <3>; 140 reg = <0x00 0x3030000 0x00 0x100>; 141 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 142 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 143 clock-names = "tbclk", "fck"; 144 status = "disabled"; 145 }; 146 147 main_ehrpwm4: pwm@3040000 { 148 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 149 #pwm-cells = <3>; 150 reg = <0x00 0x3040000 0x00 0x100>; 151 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 152 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 153 clock-names = "tbclk", "fck"; 154 status = "disabled"; 155 }; 156 157 main_ehrpwm5: pwm@3050000 { 158 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 159 #pwm-cells = <3>; 160 reg = <0x00 0x3050000 0x00 0x100>; 161 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 162 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 163 clock-names = "tbclk", "fck"; 164 status = "disabled"; 165 }; 166 167 gic500: interrupt-controller@1800000 { 168 compatible = "arm,gic-v3"; 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 #interrupt-cells = <3>; 173 interrupt-controller; 174 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 175 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 176 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 177 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 178 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 179 180 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 181 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 182 183 gic_its: msi-controller@1820000 { 184 compatible = "arm,gic-v3-its"; 185 reg = <0x00 0x01820000 0x00 0x10000>; 186 socionext,synquacer-pre-its = <0x1000000 0x400000>; 187 msi-controller; 188 #msi-cells = <1>; 189 }; 190 }; 191 192 main_gpio_intr: interrupt-controller@a00000 { 193 compatible = "ti,sci-intr"; 194 reg = <0x00 0x00a00000 0x00 0x800>; 195 ti,intr-trigger-type = <1>; 196 interrupt-controller; 197 interrupt-parent = <&gic500>; 198 #interrupt-cells = <1>; 199 ti,sci = <&dmsc>; 200 ti,sci-dev-id = <131>; 201 ti,interrupt-ranges = <8 392 56>; 202 }; 203 204 main_navss: bus@30000000 { 205 compatible = "simple-bus"; 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 209 dma-coherent; 210 dma-ranges; 211 212 ti,sci-dev-id = <199>; 213 214 main_navss_intr: interrupt-controller@310e0000 { 215 compatible = "ti,sci-intr"; 216 reg = <0x0 0x310e0000 0x0 0x4000>; 217 ti,intr-trigger-type = <4>; 218 interrupt-controller; 219 interrupt-parent = <&gic500>; 220 #interrupt-cells = <1>; 221 ti,sci = <&dmsc>; 222 ti,sci-dev-id = <213>; 223 ti,interrupt-ranges = <0 64 64>, 224 <64 448 64>, 225 <128 672 64>; 226 }; 227 228 main_udmass_inta: interrupt-controller@33d00000 { 229 compatible = "ti,sci-inta"; 230 reg = <0x0 0x33d00000 0x0 0x100000>; 231 interrupt-controller; 232 interrupt-parent = <&main_navss_intr>; 233 msi-controller; 234 #interrupt-cells = <0>; 235 ti,sci = <&dmsc>; 236 ti,sci-dev-id = <209>; 237 ti,interrupt-ranges = <0 0 256>; 238 }; 239 240 secure_proxy_main: mailbox@32c00000 { 241 compatible = "ti,am654-secure-proxy"; 242 #mbox-cells = <1>; 243 reg-names = "target_data", "rt", "scfg"; 244 reg = <0x00 0x32c00000 0x00 0x100000>, 245 <0x00 0x32400000 0x00 0x100000>, 246 <0x00 0x32800000 0x00 0x100000>; 247 interrupt-names = "rx_011"; 248 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 249 bootph-all; 250 }; 251 252 smmu0: iommu@36600000 { 253 compatible = "arm,smmu-v3"; 254 reg = <0x0 0x36600000 0x0 0x100000>; 255 interrupt-parent = <&gic500>; 256 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 258 interrupt-names = "eventq", "gerror"; 259 #iommu-cells = <1>; 260 }; 261 262 hwspinlock: spinlock@30e00000 { 263 compatible = "ti,am654-hwspinlock"; 264 reg = <0x00 0x30e00000 0x00 0x1000>; 265 #hwlock-cells = <1>; 266 }; 267 268 mailbox0_cluster0: mailbox@31f80000 { 269 compatible = "ti,am654-mailbox"; 270 reg = <0x00 0x31f80000 0x00 0x200>; 271 #mbox-cells = <1>; 272 ti,mbox-num-users = <4>; 273 ti,mbox-num-fifos = <16>; 274 interrupt-parent = <&main_navss_intr>; 275 status = "disabled"; 276 }; 277 278 mailbox0_cluster1: mailbox@31f81000 { 279 compatible = "ti,am654-mailbox"; 280 reg = <0x00 0x31f81000 0x00 0x200>; 281 #mbox-cells = <1>; 282 ti,mbox-num-users = <4>; 283 ti,mbox-num-fifos = <16>; 284 interrupt-parent = <&main_navss_intr>; 285 status = "disabled"; 286 }; 287 288 mailbox0_cluster2: mailbox@31f82000 { 289 compatible = "ti,am654-mailbox"; 290 reg = <0x00 0x31f82000 0x00 0x200>; 291 #mbox-cells = <1>; 292 ti,mbox-num-users = <4>; 293 ti,mbox-num-fifos = <16>; 294 interrupt-parent = <&main_navss_intr>; 295 status = "disabled"; 296 }; 297 298 mailbox0_cluster3: mailbox@31f83000 { 299 compatible = "ti,am654-mailbox"; 300 reg = <0x00 0x31f83000 0x00 0x200>; 301 #mbox-cells = <1>; 302 ti,mbox-num-users = <4>; 303 ti,mbox-num-fifos = <16>; 304 interrupt-parent = <&main_navss_intr>; 305 status = "disabled"; 306 }; 307 308 mailbox0_cluster4: mailbox@31f84000 { 309 compatible = "ti,am654-mailbox"; 310 reg = <0x00 0x31f84000 0x00 0x200>; 311 #mbox-cells = <1>; 312 ti,mbox-num-users = <4>; 313 ti,mbox-num-fifos = <16>; 314 interrupt-parent = <&main_navss_intr>; 315 status = "disabled"; 316 }; 317 318 mailbox0_cluster5: mailbox@31f85000 { 319 compatible = "ti,am654-mailbox"; 320 reg = <0x00 0x31f85000 0x00 0x200>; 321 #mbox-cells = <1>; 322 ti,mbox-num-users = <4>; 323 ti,mbox-num-fifos = <16>; 324 interrupt-parent = <&main_navss_intr>; 325 status = "disabled"; 326 }; 327 328 mailbox0_cluster6: mailbox@31f86000 { 329 compatible = "ti,am654-mailbox"; 330 reg = <0x00 0x31f86000 0x00 0x200>; 331 #mbox-cells = <1>; 332 ti,mbox-num-users = <4>; 333 ti,mbox-num-fifos = <16>; 334 interrupt-parent = <&main_navss_intr>; 335 status = "disabled"; 336 }; 337 338 mailbox0_cluster7: mailbox@31f87000 { 339 compatible = "ti,am654-mailbox"; 340 reg = <0x00 0x31f87000 0x00 0x200>; 341 #mbox-cells = <1>; 342 ti,mbox-num-users = <4>; 343 ti,mbox-num-fifos = <16>; 344 interrupt-parent = <&main_navss_intr>; 345 status = "disabled"; 346 }; 347 348 mailbox0_cluster8: mailbox@31f88000 { 349 compatible = "ti,am654-mailbox"; 350 reg = <0x00 0x31f88000 0x00 0x200>; 351 #mbox-cells = <1>; 352 ti,mbox-num-users = <4>; 353 ti,mbox-num-fifos = <16>; 354 interrupt-parent = <&main_navss_intr>; 355 status = "disabled"; 356 }; 357 358 mailbox0_cluster9: mailbox@31f89000 { 359 compatible = "ti,am654-mailbox"; 360 reg = <0x00 0x31f89000 0x00 0x200>; 361 #mbox-cells = <1>; 362 ti,mbox-num-users = <4>; 363 ti,mbox-num-fifos = <16>; 364 interrupt-parent = <&main_navss_intr>; 365 status = "disabled"; 366 }; 367 368 mailbox0_cluster10: mailbox@31f8a000 { 369 compatible = "ti,am654-mailbox"; 370 reg = <0x00 0x31f8a000 0x00 0x200>; 371 #mbox-cells = <1>; 372 ti,mbox-num-users = <4>; 373 ti,mbox-num-fifos = <16>; 374 interrupt-parent = <&main_navss_intr>; 375 status = "disabled"; 376 }; 377 378 mailbox0_cluster11: mailbox@31f8b000 { 379 compatible = "ti,am654-mailbox"; 380 reg = <0x00 0x31f8b000 0x00 0x200>; 381 #mbox-cells = <1>; 382 ti,mbox-num-users = <4>; 383 ti,mbox-num-fifos = <16>; 384 interrupt-parent = <&main_navss_intr>; 385 status = "disabled"; 386 }; 387 388 main_ringacc: ringacc@3c000000 { 389 compatible = "ti,am654-navss-ringacc"; 390 reg = <0x0 0x3c000000 0x0 0x400000>, 391 <0x0 0x38000000 0x0 0x400000>, 392 <0x0 0x31120000 0x0 0x100>, 393 <0x0 0x33000000 0x0 0x40000>, 394 <0x0 0x31080000 0x0 0x40000>; 395 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 396 ti,num-rings = <1024>; 397 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 398 ti,sci = <&dmsc>; 399 ti,sci-dev-id = <211>; 400 msi-parent = <&main_udmass_inta>; 401 }; 402 403 main_udmap: dma-controller@31150000 { 404 compatible = "ti,j721e-navss-main-udmap"; 405 reg = <0x0 0x31150000 0x0 0x100>, 406 <0x0 0x34000000 0x0 0x100000>, 407 <0x0 0x35000000 0x0 0x100000>, 408 <0x0 0x30b00000 0x0 0x20000>, 409 <0x0 0x30c00000 0x0 0x10000>, 410 <0x0 0x30d00000 0x0 0x8000>; 411 reg-names = "gcfg", "rchanrt", "tchanrt", 412 "tchan", "rchan", "rflow"; 413 msi-parent = <&main_udmass_inta>; 414 #dma-cells = <1>; 415 416 ti,sci = <&dmsc>; 417 ti,sci-dev-id = <212>; 418 ti,ringacc = <&main_ringacc>; 419 420 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 421 <0x0f>, /* TX_HCHAN */ 422 <0x10>; /* TX_UHCHAN */ 423 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 424 <0x0b>, /* RX_HCHAN */ 425 <0x0c>; /* RX_UHCHAN */ 426 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 427 }; 428 429 cpts@310d0000 { 430 compatible = "ti,j721e-cpts"; 431 reg = <0x0 0x310d0000 0x0 0x400>; 432 reg-names = "cpts"; 433 clocks = <&k3_clks 201 1>; 434 clock-names = "cpts"; 435 interrupts-extended = <&main_navss_intr 391>; 436 interrupt-names = "cpts"; 437 ti,cpts-periodic-outputs = <6>; 438 ti,cpts-ext-ts-inputs = <8>; 439 }; 440 }; 441 442 cpsw0: ethernet@c000000 { 443 compatible = "ti,j721e-cpswxg-nuss"; 444 #address-cells = <2>; 445 #size-cells = <2>; 446 reg = <0x0 0xc000000 0x0 0x200000>; 447 reg-names = "cpsw_nuss"; 448 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 449 clocks = <&k3_clks 19 89>; 450 clock-names = "fck"; 451 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 452 453 dmas = <&main_udmap 0xca00>, 454 <&main_udmap 0xca01>, 455 <&main_udmap 0xca02>, 456 <&main_udmap 0xca03>, 457 <&main_udmap 0xca04>, 458 <&main_udmap 0xca05>, 459 <&main_udmap 0xca06>, 460 <&main_udmap 0xca07>, 461 <&main_udmap 0x4a00>; 462 dma-names = "tx0", "tx1", "tx2", "tx3", 463 "tx4", "tx5", "tx6", "tx7", 464 "rx"; 465 466 status = "disabled"; 467 468 ethernet-ports { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 cpsw0_port1: port@1 { 472 reg = <1>; 473 ti,mac-only; 474 label = "port1"; 475 status = "disabled"; 476 }; 477 478 cpsw0_port2: port@2 { 479 reg = <2>; 480 ti,mac-only; 481 label = "port2"; 482 status = "disabled"; 483 }; 484 485 cpsw0_port3: port@3 { 486 reg = <3>; 487 ti,mac-only; 488 label = "port3"; 489 status = "disabled"; 490 }; 491 492 cpsw0_port4: port@4 { 493 reg = <4>; 494 ti,mac-only; 495 label = "port4"; 496 status = "disabled"; 497 }; 498 499 cpsw0_port5: port@5 { 500 reg = <5>; 501 ti,mac-only; 502 label = "port5"; 503 status = "disabled"; 504 }; 505 506 cpsw0_port6: port@6 { 507 reg = <6>; 508 ti,mac-only; 509 label = "port6"; 510 status = "disabled"; 511 }; 512 513 cpsw0_port7: port@7 { 514 reg = <7>; 515 ti,mac-only; 516 label = "port7"; 517 status = "disabled"; 518 }; 519 520 cpsw0_port8: port@8 { 521 reg = <8>; 522 ti,mac-only; 523 label = "port8"; 524 status = "disabled"; 525 }; 526 }; 527 528 cpsw9g_mdio: mdio@f00 { 529 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 530 reg = <0x0 0xf00 0x0 0x100>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 clocks = <&k3_clks 19 89>; 534 clock-names = "fck"; 535 bus_freq = <1000000>; 536 status = "disabled"; 537 }; 538 539 cpts@3d000 { 540 compatible = "ti,j721e-cpts"; 541 reg = <0x0 0x3d000 0x0 0x400>; 542 clocks = <&k3_clks 19 16>; 543 clock-names = "cpts"; 544 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "cpts"; 546 ti,cpts-ext-ts-inputs = <4>; 547 ti,cpts-periodic-outputs = <2>; 548 }; 549 }; 550 551 main_crypto: crypto@4e00000 { 552 compatible = "ti,j721e-sa2ul"; 553 reg = <0x0 0x4e00000 0x0 0x1200>; 554 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 555 #address-cells = <2>; 556 #size-cells = <2>; 557 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 558 559 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 560 <&main_udmap 0x4001>; 561 dma-names = "tx", "rx1", "rx2"; 562 563 rng: rng@4e10000 { 564 compatible = "inside-secure,safexcel-eip76"; 565 reg = <0x0 0x4e10000 0x0 0x7d>; 566 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 567 }; 568 }; 569 570 main_pmx0: pinctrl@11c000 { 571 compatible = "pinctrl-single"; 572 /* Proxy 0 addressing */ 573 reg = <0x0 0x11c000 0x0 0x2b4>; 574 #pinctrl-cells = <1>; 575 pinctrl-single,register-width = <32>; 576 pinctrl-single,function-mask = <0xffffffff>; 577 }; 578 579 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 580 main_timerio_input: pinctrl@104200 { 581 compatible = "pinctrl-single"; 582 reg = <0x00 0x104200 0x00 0x50>; 583 #pinctrl-cells = <1>; 584 pinctrl-single,register-width = <32>; 585 pinctrl-single,function-mask = <0x00000007>; 586 }; 587 588 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 589 main_timerio_output: pinctrl@104280 { 590 compatible = "pinctrl-single"; 591 reg = <0x00 0x104280 0x00 0x20>; 592 #pinctrl-cells = <1>; 593 pinctrl-single,register-width = <32>; 594 pinctrl-single,function-mask = <0x0000001f>; 595 }; 596 597 ti_csi2rx0: ticsi2rx@4500000 { 598 compatible = "ti,j721e-csi2rx-shim"; 599 reg = <0x0 0x4500000 0x0 0x1000>; 600 ranges; 601 #address-cells = <2>; 602 #size-cells = <2>; 603 dmas = <&main_udmap 0x4940>; 604 dma-names = "rx0"; 605 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 606 status = "disabled"; 607 608 cdns_csi2rx0: csi-bridge@4504000 { 609 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 610 reg = <0x0 0x4504000 0x0 0x1000>; 611 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "error_irq", "irq"; 614 clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, 615 <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; 616 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 617 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 618 phys = <&dphy0>; 619 phy-names = "dphy"; 620 621 ports { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 625 csi0_port0: port@0 { 626 reg = <0>; 627 status = "disabled"; 628 }; 629 630 csi0_port1: port@1 { 631 reg = <1>; 632 status = "disabled"; 633 }; 634 635 csi0_port2: port@2 { 636 reg = <2>; 637 status = "disabled"; 638 }; 639 640 csi0_port3: port@3 { 641 reg = <3>; 642 status = "disabled"; 643 }; 644 645 csi0_port4: port@4 { 646 reg = <4>; 647 status = "disabled"; 648 }; 649 }; 650 }; 651 }; 652 653 ti_csi2rx1: ticsi2rx@4510000 { 654 compatible = "ti,j721e-csi2rx-shim"; 655 reg = <0x0 0x4510000 0x0 0x1000>; 656 ranges; 657 #address-cells = <2>; 658 #size-cells = <2>; 659 dmas = <&main_udmap 0x4960>; 660 dma-names = "rx0"; 661 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 662 status = "disabled"; 663 664 cdns_csi2rx1: csi-bridge@4514000 { 665 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 666 reg = <0x0 0x4514000 0x0 0x1000>; 667 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 669 interrupt-names = "error_irq", "irq"; 670 clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, 671 <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; 672 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 673 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 674 phys = <&dphy1>; 675 phy-names = "dphy"; 676 677 ports { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 681 csi1_port0: port@0 { 682 reg = <0>; 683 status = "disabled"; 684 }; 685 686 csi1_port1: port@1 { 687 reg = <1>; 688 status = "disabled"; 689 }; 690 691 csi1_port2: port@2 { 692 reg = <2>; 693 status = "disabled"; 694 }; 695 696 csi1_port3: port@3 { 697 reg = <3>; 698 status = "disabled"; 699 }; 700 701 csi1_port4: port@4 { 702 reg = <4>; 703 status = "disabled"; 704 }; 705 }; 706 }; 707 }; 708 709 dphy0: phy@4580000 { 710 compatible = "cdns,dphy-rx"; 711 reg = <0x0 0x4580000 0x0 0x1100>; 712 #phy-cells = <0>; 713 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 714 status = "disabled"; 715 }; 716 717 dphy1: phy@4590000 { 718 compatible = "cdns,dphy-rx"; 719 reg = <0x0 0x4590000 0x0 0x1100>; 720 #phy-cells = <0>; 721 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 722 status = "disabled"; 723 }; 724 725 serdes_wiz0: wiz@5000000 { 726 compatible = "ti,j721e-wiz-16g"; 727 #address-cells = <1>; 728 #size-cells = <1>; 729 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 730 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 731 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 732 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 733 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 734 num-lanes = <2>; 735 #reset-cells = <1>; 736 ranges = <0x5000000 0x0 0x5000000 0x10000>; 737 738 wiz0_pll0_refclk: pll0-refclk { 739 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 740 #clock-cells = <0>; 741 assigned-clocks = <&wiz0_pll0_refclk>; 742 assigned-clock-parents = <&k3_clks 292 11>; 743 }; 744 745 wiz0_pll1_refclk: pll1-refclk { 746 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 747 #clock-cells = <0>; 748 assigned-clocks = <&wiz0_pll1_refclk>; 749 assigned-clock-parents = <&k3_clks 292 0>; 750 }; 751 752 wiz0_refclk_dig: refclk-dig { 753 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 754 #clock-cells = <0>; 755 assigned-clocks = <&wiz0_refclk_dig>; 756 assigned-clock-parents = <&k3_clks 292 11>; 757 }; 758 759 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 760 clocks = <&wiz0_refclk_dig>; 761 #clock-cells = <0>; 762 }; 763 764 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 765 clocks = <&wiz0_pll1_refclk>; 766 #clock-cells = <0>; 767 }; 768 769 serdes0: serdes@5000000 { 770 compatible = "ti,sierra-phy-t0"; 771 reg-names = "serdes"; 772 reg = <0x5000000 0x10000>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 #clock-cells = <1>; 776 resets = <&serdes_wiz0 0>; 777 reset-names = "sierra_reset"; 778 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 779 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 780 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 781 "pll0_refclk", "pll1_refclk"; 782 }; 783 }; 784 785 serdes_wiz1: wiz@5010000 { 786 compatible = "ti,j721e-wiz-16g"; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 790 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 791 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 792 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 793 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 794 num-lanes = <2>; 795 #reset-cells = <1>; 796 ranges = <0x5010000 0x0 0x5010000 0x10000>; 797 798 wiz1_pll0_refclk: pll0-refclk { 799 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 800 #clock-cells = <0>; 801 assigned-clocks = <&wiz1_pll0_refclk>; 802 assigned-clock-parents = <&k3_clks 293 13>; 803 }; 804 805 wiz1_pll1_refclk: pll1-refclk { 806 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 807 #clock-cells = <0>; 808 assigned-clocks = <&wiz1_pll1_refclk>; 809 assigned-clock-parents = <&k3_clks 293 0>; 810 }; 811 812 wiz1_refclk_dig: refclk-dig { 813 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 814 #clock-cells = <0>; 815 assigned-clocks = <&wiz1_refclk_dig>; 816 assigned-clock-parents = <&k3_clks 293 13>; 817 }; 818 819 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { 820 clocks = <&wiz1_refclk_dig>; 821 #clock-cells = <0>; 822 }; 823 824 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 825 clocks = <&wiz1_pll1_refclk>; 826 #clock-cells = <0>; 827 }; 828 829 serdes1: serdes@5010000 { 830 compatible = "ti,sierra-phy-t0"; 831 reg-names = "serdes"; 832 reg = <0x5010000 0x10000>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 #clock-cells = <1>; 836 resets = <&serdes_wiz1 0>; 837 reset-names = "sierra_reset"; 838 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 839 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 840 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 841 "pll0_refclk", "pll1_refclk"; 842 }; 843 }; 844 845 serdes_wiz2: wiz@5020000 { 846 compatible = "ti,j721e-wiz-16g"; 847 #address-cells = <1>; 848 #size-cells = <1>; 849 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 850 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 851 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 852 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 853 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 854 num-lanes = <2>; 855 #reset-cells = <1>; 856 ranges = <0x5020000 0x0 0x5020000 0x10000>; 857 858 wiz2_pll0_refclk: pll0-refclk { 859 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 860 #clock-cells = <0>; 861 assigned-clocks = <&wiz2_pll0_refclk>; 862 assigned-clock-parents = <&k3_clks 294 11>; 863 }; 864 865 wiz2_pll1_refclk: pll1-refclk { 866 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 867 #clock-cells = <0>; 868 assigned-clocks = <&wiz2_pll1_refclk>; 869 assigned-clock-parents = <&k3_clks 294 0>; 870 }; 871 872 wiz2_refclk_dig: refclk-dig { 873 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 874 #clock-cells = <0>; 875 assigned-clocks = <&wiz2_refclk_dig>; 876 assigned-clock-parents = <&k3_clks 294 11>; 877 }; 878 879 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 880 clocks = <&wiz2_refclk_dig>; 881 #clock-cells = <0>; 882 }; 883 884 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 885 clocks = <&wiz2_pll1_refclk>; 886 #clock-cells = <0>; 887 }; 888 889 serdes2: serdes@5020000 { 890 compatible = "ti,sierra-phy-t0"; 891 reg-names = "serdes"; 892 reg = <0x5020000 0x10000>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 #clock-cells = <1>; 896 resets = <&serdes_wiz2 0>; 897 reset-names = "sierra_reset"; 898 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 899 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 900 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 901 "pll0_refclk", "pll1_refclk"; 902 }; 903 }; 904 905 serdes_wiz3: wiz@5030000 { 906 compatible = "ti,j721e-wiz-16g"; 907 #address-cells = <1>; 908 #size-cells = <1>; 909 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 910 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 911 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 912 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 913 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 914 num-lanes = <2>; 915 #reset-cells = <1>; 916 ranges = <0x5030000 0x0 0x5030000 0x10000>; 917 918 wiz3_pll0_refclk: pll0-refclk { 919 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 920 #clock-cells = <0>; 921 assigned-clocks = <&wiz3_pll0_refclk>; 922 assigned-clock-parents = <&k3_clks 295 9>; 923 }; 924 925 wiz3_pll1_refclk: pll1-refclk { 926 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 927 #clock-cells = <0>; 928 assigned-clocks = <&wiz3_pll1_refclk>; 929 assigned-clock-parents = <&k3_clks 295 0>; 930 }; 931 932 wiz3_refclk_dig: refclk-dig { 933 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 934 #clock-cells = <0>; 935 assigned-clocks = <&wiz3_refclk_dig>; 936 assigned-clock-parents = <&k3_clks 295 9>; 937 }; 938 939 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 940 clocks = <&wiz3_refclk_dig>; 941 #clock-cells = <0>; 942 }; 943 944 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 945 clocks = <&wiz3_pll1_refclk>; 946 #clock-cells = <0>; 947 }; 948 949 serdes3: serdes@5030000 { 950 compatible = "ti,sierra-phy-t0"; 951 reg-names = "serdes"; 952 reg = <0x5030000 0x10000>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 #clock-cells = <1>; 956 resets = <&serdes_wiz3 0>; 957 reset-names = "sierra_reset"; 958 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 959 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 960 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 961 "pll0_refclk", "pll1_refclk"; 962 }; 963 }; 964 965 pcie0_rc: pcie@2900000 { 966 compatible = "ti,j721e-pcie-host"; 967 reg = <0x00 0x02900000 0x00 0x1000>, 968 <0x00 0x02907000 0x00 0x400>, 969 <0x00 0x0d000000 0x00 0x00800000>, 970 <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 971 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 972 interrupt-names = "link_state"; 973 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 974 device_type = "pci"; 975 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 976 max-link-speed = <3>; 977 num-lanes = <2>; 978 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 979 clocks = <&k3_clks 239 1>; 980 clock-names = "fck"; 981 #address-cells = <3>; 982 #size-cells = <2>; 983 bus-range = <0x0 0xff>; 984 vendor-id = <0x104c>; 985 device-id = <0xb00d>; 986 msi-map = <0x0 &gic_its 0x0 0x10000>; 987 dma-coherent; 988 ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 989 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 990 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 991 status = "disabled"; 992 }; 993 994 pcie1_rc: pcie@2910000 { 995 compatible = "ti,j721e-pcie-host"; 996 reg = <0x00 0x02910000 0x00 0x1000>, 997 <0x00 0x02917000 0x00 0x400>, 998 <0x00 0x0d800000 0x00 0x00800000>, 999 <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 1000 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1001 interrupt-names = "link_state"; 1002 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1003 device_type = "pci"; 1004 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 1005 max-link-speed = <3>; 1006 num-lanes = <2>; 1007 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 1008 clocks = <&k3_clks 240 1>; 1009 clock-names = "fck"; 1010 #address-cells = <3>; 1011 #size-cells = <2>; 1012 bus-range = <0x0 0xff>; 1013 vendor-id = <0x104c>; 1014 device-id = <0xb00d>; 1015 msi-map = <0x0 &gic_its 0x10000 0x10000>; 1016 dma-coherent; 1017 ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1018 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1019 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1020 status = "disabled"; 1021 }; 1022 1023 pcie2_rc: pcie@2920000 { 1024 compatible = "ti,j721e-pcie-host"; 1025 reg = <0x00 0x02920000 0x00 0x1000>, 1026 <0x00 0x02927000 0x00 0x400>, 1027 <0x00 0x0e000000 0x00 0x00800000>, 1028 <0x44 0x00000000 0x00 0x00001000>; 1029 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1030 interrupt-names = "link_state"; 1031 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 1032 device_type = "pci"; 1033 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; 1034 max-link-speed = <3>; 1035 num-lanes = <2>; 1036 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 1037 clocks = <&k3_clks 241 1>; 1038 clock-names = "fck"; 1039 #address-cells = <3>; 1040 #size-cells = <2>; 1041 bus-range = <0x0 0xff>; 1042 vendor-id = <0x104c>; 1043 device-id = <0xb00d>; 1044 msi-map = <0x0 &gic_its 0x20000 0x10000>; 1045 dma-coherent; 1046 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 1047 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 1048 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1049 status = "disabled"; 1050 }; 1051 1052 pcie3_rc: pcie@2930000 { 1053 compatible = "ti,j721e-pcie-host"; 1054 reg = <0x00 0x02930000 0x00 0x1000>, 1055 <0x00 0x02937000 0x00 0x400>, 1056 <0x00 0x0e800000 0x00 0x00800000>, 1057 <0x44 0x10000000 0x00 0x00001000>; 1058 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1059 interrupt-names = "link_state"; 1060 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 1061 device_type = "pci"; 1062 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; 1063 max-link-speed = <3>; 1064 num-lanes = <2>; 1065 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 1066 clocks = <&k3_clks 242 1>; 1067 clock-names = "fck"; 1068 #address-cells = <3>; 1069 #size-cells = <2>; 1070 bus-range = <0x0 0xff>; 1071 vendor-id = <0x104c>; 1072 device-id = <0xb00d>; 1073 msi-map = <0x0 &gic_its 0x30000 0x10000>; 1074 dma-coherent; 1075 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 1076 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 1077 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1078 status = "disabled"; 1079 }; 1080 1081 serdes_wiz4: wiz@5050000 { 1082 compatible = "ti,am64-wiz-10g"; 1083 #address-cells = <1>; 1084 #size-cells = <1>; 1085 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 1086 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 1087 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1088 assigned-clocks = <&k3_clks 297 9>; 1089 assigned-clock-parents = <&k3_clks 297 10>; 1090 assigned-clock-rates = <19200000>; 1091 num-lanes = <4>; 1092 #reset-cells = <1>; 1093 #clock-cells = <1>; 1094 ranges = <0x05050000 0x00 0x05050000 0x010000>, 1095 <0x0a030a00 0x00 0x0a030a00 0x40>; 1096 1097 serdes4: serdes@5050000 { 1098 /* 1099 * Note: we also map DPTX PHY registers as the Torrent 1100 * needs to manage those. 1101 */ 1102 compatible = "ti,j721e-serdes-10g"; 1103 reg = <0x05050000 0x010000>, 1104 <0x0a030a00 0x40>; /* DPTX PHY */ 1105 reg-names = "torrent_phy", "dptx_phy"; 1106 1107 resets = <&serdes_wiz4 0>; 1108 reset-names = "torrent_reset"; 1109 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 1110 clock-names = "refclk"; 1111 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1112 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1113 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1114 assigned-clock-parents = <&k3_clks 297 9>, 1115 <&k3_clks 297 9>, 1116 <&k3_clks 297 9>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 }; 1120 }; 1121 1122 main_timer0: timer@2400000 { 1123 compatible = "ti,am654-timer"; 1124 reg = <0x00 0x2400000 0x00 0x400>; 1125 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&k3_clks 49 1>; 1127 clock-names = "fck"; 1128 assigned-clocks = <&k3_clks 49 1>; 1129 assigned-clock-parents = <&k3_clks 49 2>; 1130 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1131 ti,timer-pwm; 1132 }; 1133 1134 main_timer1: timer@2410000 { 1135 compatible = "ti,am654-timer"; 1136 reg = <0x00 0x2410000 0x00 0x400>; 1137 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&k3_clks 50 1>; 1139 clock-names = "fck"; 1140 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; 1141 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; 1142 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1143 ti,timer-pwm; 1144 }; 1145 1146 main_timer2: timer@2420000 { 1147 compatible = "ti,am654-timer"; 1148 reg = <0x00 0x2420000 0x00 0x400>; 1149 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&k3_clks 51 1>; 1151 clock-names = "fck"; 1152 assigned-clocks = <&k3_clks 51 1>; 1153 assigned-clock-parents = <&k3_clks 51 2>; 1154 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1155 ti,timer-pwm; 1156 }; 1157 1158 main_timer3: timer@2430000 { 1159 compatible = "ti,am654-timer"; 1160 reg = <0x00 0x2430000 0x00 0x400>; 1161 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&k3_clks 52 1>; 1163 clock-names = "fck"; 1164 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; 1165 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; 1166 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1167 ti,timer-pwm; 1168 }; 1169 1170 main_timer4: timer@2440000 { 1171 compatible = "ti,am654-timer"; 1172 reg = <0x00 0x2440000 0x00 0x400>; 1173 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&k3_clks 53 1>; 1175 clock-names = "fck"; 1176 assigned-clocks = <&k3_clks 53 1>; 1177 assigned-clock-parents = <&k3_clks 53 2>; 1178 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1179 ti,timer-pwm; 1180 }; 1181 1182 main_timer5: timer@2450000 { 1183 compatible = "ti,am654-timer"; 1184 reg = <0x00 0x2450000 0x00 0x400>; 1185 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&k3_clks 54 1>; 1187 clock-names = "fck"; 1188 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; 1189 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; 1190 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1191 ti,timer-pwm; 1192 }; 1193 1194 main_timer6: timer@2460000 { 1195 compatible = "ti,am654-timer"; 1196 reg = <0x00 0x2460000 0x00 0x400>; 1197 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&k3_clks 55 1>; 1199 clock-names = "fck"; 1200 assigned-clocks = <&k3_clks 55 1>; 1201 assigned-clock-parents = <&k3_clks 55 2>; 1202 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1203 ti,timer-pwm; 1204 }; 1205 1206 main_timer7: timer@2470000 { 1207 compatible = "ti,am654-timer"; 1208 reg = <0x00 0x2470000 0x00 0x400>; 1209 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1210 clocks = <&k3_clks 57 1>; 1211 clock-names = "fck"; 1212 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; 1213 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; 1214 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1215 ti,timer-pwm; 1216 }; 1217 1218 main_timer8: timer@2480000 { 1219 compatible = "ti,am654-timer"; 1220 reg = <0x00 0x2480000 0x00 0x400>; 1221 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&k3_clks 58 1>; 1223 clock-names = "fck"; 1224 assigned-clocks = <&k3_clks 58 1>; 1225 assigned-clock-parents = <&k3_clks 58 2>; 1226 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1227 ti,timer-pwm; 1228 }; 1229 1230 main_timer9: timer@2490000 { 1231 compatible = "ti,am654-timer"; 1232 reg = <0x00 0x2490000 0x00 0x400>; 1233 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&k3_clks 59 1>; 1235 clock-names = "fck"; 1236 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; 1237 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; 1238 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1239 ti,timer-pwm; 1240 }; 1241 1242 main_timer10: timer@24a0000 { 1243 compatible = "ti,am654-timer"; 1244 reg = <0x00 0x24a0000 0x00 0x400>; 1245 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&k3_clks 60 1>; 1247 clock-names = "fck"; 1248 assigned-clocks = <&k3_clks 60 1>; 1249 assigned-clock-parents = <&k3_clks 60 2>; 1250 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1251 ti,timer-pwm; 1252 }; 1253 1254 main_timer11: timer@24b0000 { 1255 compatible = "ti,am654-timer"; 1256 reg = <0x00 0x24b0000 0x00 0x400>; 1257 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&k3_clks 62 1>; 1259 clock-names = "fck"; 1260 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; 1261 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; 1262 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1263 ti,timer-pwm; 1264 }; 1265 1266 main_timer12: timer@24c0000 { 1267 compatible = "ti,am654-timer"; 1268 reg = <0x00 0x24c0000 0x00 0x400>; 1269 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&k3_clks 63 1>; 1271 clock-names = "fck"; 1272 assigned-clocks = <&k3_clks 63 1>; 1273 assigned-clock-parents = <&k3_clks 63 2>; 1274 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1275 ti,timer-pwm; 1276 }; 1277 1278 main_timer13: timer@24d0000 { 1279 compatible = "ti,am654-timer"; 1280 reg = <0x00 0x24d0000 0x00 0x400>; 1281 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&k3_clks 64 1>; 1283 clock-names = "fck"; 1284 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; 1285 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; 1286 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1287 ti,timer-pwm; 1288 }; 1289 1290 main_timer14: timer@24e0000 { 1291 compatible = "ti,am654-timer"; 1292 reg = <0x00 0x24e0000 0x00 0x400>; 1293 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&k3_clks 65 1>; 1295 clock-names = "fck"; 1296 assigned-clocks = <&k3_clks 65 1>; 1297 assigned-clock-parents = <&k3_clks 65 2>; 1298 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1299 ti,timer-pwm; 1300 }; 1301 1302 main_timer15: timer@24f0000 { 1303 compatible = "ti,am654-timer"; 1304 reg = <0x00 0x24f0000 0x00 0x400>; 1305 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&k3_clks 66 1>; 1307 clock-names = "fck"; 1308 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; 1309 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; 1310 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1311 ti,timer-pwm; 1312 }; 1313 1314 main_timer16: timer@2500000 { 1315 compatible = "ti,am654-timer"; 1316 reg = <0x00 0x2500000 0x00 0x400>; 1317 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&k3_clks 67 1>; 1319 clock-names = "fck"; 1320 assigned-clocks = <&k3_clks 67 1>; 1321 assigned-clock-parents = <&k3_clks 67 2>; 1322 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1323 ti,timer-pwm; 1324 }; 1325 1326 main_timer17: timer@2510000 { 1327 compatible = "ti,am654-timer"; 1328 reg = <0x00 0x2510000 0x00 0x400>; 1329 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&k3_clks 68 1>; 1331 clock-names = "fck"; 1332 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; 1333 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; 1334 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1335 ti,timer-pwm; 1336 }; 1337 1338 main_timer18: timer@2520000 { 1339 compatible = "ti,am654-timer"; 1340 reg = <0x00 0x2520000 0x00 0x400>; 1341 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&k3_clks 69 1>; 1343 clock-names = "fck"; 1344 assigned-clocks = <&k3_clks 69 1>; 1345 assigned-clock-parents = <&k3_clks 69 2>; 1346 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1347 ti,timer-pwm; 1348 }; 1349 1350 main_timer19: timer@2530000 { 1351 compatible = "ti,am654-timer"; 1352 reg = <0x00 0x2530000 0x00 0x400>; 1353 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&k3_clks 70 1>; 1355 clock-names = "fck"; 1356 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; 1357 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; 1358 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1359 ti,timer-pwm; 1360 }; 1361 1362 main_uart0: serial@2800000 { 1363 compatible = "ti,j721e-uart", "ti,am654-uart"; 1364 reg = <0x00 0x02800000 0x00 0x100>; 1365 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1366 clock-frequency = <48000000>; 1367 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 1368 clocks = <&k3_clks 146 0>; 1369 clock-names = "fclk"; 1370 status = "disabled"; 1371 }; 1372 1373 main_uart1: serial@2810000 { 1374 compatible = "ti,j721e-uart", "ti,am654-uart"; 1375 reg = <0x00 0x02810000 0x00 0x100>; 1376 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1377 clock-frequency = <48000000>; 1378 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1379 clocks = <&k3_clks 278 0>; 1380 clock-names = "fclk"; 1381 status = "disabled"; 1382 }; 1383 1384 main_uart2: serial@2820000 { 1385 compatible = "ti,j721e-uart", "ti,am654-uart"; 1386 reg = <0x00 0x02820000 0x00 0x100>; 1387 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1388 clock-frequency = <48000000>; 1389 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 1390 clocks = <&k3_clks 279 0>; 1391 clock-names = "fclk"; 1392 status = "disabled"; 1393 }; 1394 1395 main_uart3: serial@2830000 { 1396 compatible = "ti,j721e-uart", "ti,am654-uart"; 1397 reg = <0x00 0x02830000 0x00 0x100>; 1398 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1399 clock-frequency = <48000000>; 1400 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 1401 clocks = <&k3_clks 280 0>; 1402 clock-names = "fclk"; 1403 status = "disabled"; 1404 }; 1405 1406 main_uart4: serial@2840000 { 1407 compatible = "ti,j721e-uart", "ti,am654-uart"; 1408 reg = <0x00 0x02840000 0x00 0x100>; 1409 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1410 clock-frequency = <48000000>; 1411 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 1412 clocks = <&k3_clks 281 0>; 1413 clock-names = "fclk"; 1414 status = "disabled"; 1415 }; 1416 1417 main_uart5: serial@2850000 { 1418 compatible = "ti,j721e-uart", "ti,am654-uart"; 1419 reg = <0x00 0x02850000 0x00 0x100>; 1420 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1421 clock-frequency = <48000000>; 1422 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 1423 clocks = <&k3_clks 282 0>; 1424 clock-names = "fclk"; 1425 status = "disabled"; 1426 }; 1427 1428 main_uart6: serial@2860000 { 1429 compatible = "ti,j721e-uart", "ti,am654-uart"; 1430 reg = <0x00 0x02860000 0x00 0x100>; 1431 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1432 clock-frequency = <48000000>; 1433 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 1434 clocks = <&k3_clks 283 0>; 1435 clock-names = "fclk"; 1436 status = "disabled"; 1437 }; 1438 1439 main_uart7: serial@2870000 { 1440 compatible = "ti,j721e-uart", "ti,am654-uart"; 1441 reg = <0x00 0x02870000 0x00 0x100>; 1442 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1443 clock-frequency = <48000000>; 1444 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1445 clocks = <&k3_clks 284 0>; 1446 clock-names = "fclk"; 1447 status = "disabled"; 1448 }; 1449 1450 main_uart8: serial@2880000 { 1451 compatible = "ti,j721e-uart", "ti,am654-uart"; 1452 reg = <0x00 0x02880000 0x00 0x100>; 1453 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1454 clock-frequency = <48000000>; 1455 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1456 clocks = <&k3_clks 285 0>; 1457 clock-names = "fclk"; 1458 status = "disabled"; 1459 }; 1460 1461 main_uart9: serial@2890000 { 1462 compatible = "ti,j721e-uart", "ti,am654-uart"; 1463 reg = <0x00 0x02890000 0x00 0x100>; 1464 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1465 clock-frequency = <48000000>; 1466 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1467 clocks = <&k3_clks 286 0>; 1468 clock-names = "fclk"; 1469 status = "disabled"; 1470 }; 1471 1472 main_gpio0: gpio@600000 { 1473 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1474 reg = <0x0 0x00600000 0x0 0x100>; 1475 gpio-controller; 1476 #gpio-cells = <2>; 1477 interrupt-parent = <&main_gpio_intr>; 1478 interrupts = <256>, <257>, <258>, <259>, 1479 <260>, <261>, <262>, <263>; 1480 interrupt-controller; 1481 #interrupt-cells = <2>; 1482 ti,ngpio = <128>; 1483 ti,davinci-gpio-unbanked = <0>; 1484 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1485 clocks = <&k3_clks 105 0>; 1486 clock-names = "gpio"; 1487 status = "disabled"; 1488 }; 1489 1490 main_gpio1: gpio@601000 { 1491 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1492 reg = <0x0 0x00601000 0x0 0x100>; 1493 gpio-controller; 1494 #gpio-cells = <2>; 1495 interrupt-parent = <&main_gpio_intr>; 1496 interrupts = <288>, <289>, <290>; 1497 interrupt-controller; 1498 #interrupt-cells = <2>; 1499 ti,ngpio = <36>; 1500 ti,davinci-gpio-unbanked = <0>; 1501 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1502 clocks = <&k3_clks 106 0>; 1503 clock-names = "gpio"; 1504 status = "disabled"; 1505 }; 1506 1507 main_gpio2: gpio@610000 { 1508 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1509 reg = <0x0 0x00610000 0x0 0x100>; 1510 gpio-controller; 1511 #gpio-cells = <2>; 1512 interrupt-parent = <&main_gpio_intr>; 1513 interrupts = <264>, <265>, <266>, <267>, 1514 <268>, <269>, <270>, <271>; 1515 interrupt-controller; 1516 #interrupt-cells = <2>; 1517 ti,ngpio = <128>; 1518 ti,davinci-gpio-unbanked = <0>; 1519 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1520 clocks = <&k3_clks 107 0>; 1521 clock-names = "gpio"; 1522 status = "disabled"; 1523 }; 1524 1525 main_gpio3: gpio@611000 { 1526 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1527 reg = <0x0 0x00611000 0x0 0x100>; 1528 gpio-controller; 1529 #gpio-cells = <2>; 1530 interrupt-parent = <&main_gpio_intr>; 1531 interrupts = <292>, <293>, <294>; 1532 interrupt-controller; 1533 #interrupt-cells = <2>; 1534 ti,ngpio = <36>; 1535 ti,davinci-gpio-unbanked = <0>; 1536 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1537 clocks = <&k3_clks 108 0>; 1538 clock-names = "gpio"; 1539 status = "disabled"; 1540 }; 1541 1542 main_gpio4: gpio@620000 { 1543 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1544 reg = <0x0 0x00620000 0x0 0x100>; 1545 gpio-controller; 1546 #gpio-cells = <2>; 1547 interrupt-parent = <&main_gpio_intr>; 1548 interrupts = <272>, <273>, <274>, <275>, 1549 <276>, <277>, <278>, <279>; 1550 interrupt-controller; 1551 #interrupt-cells = <2>; 1552 ti,ngpio = <128>; 1553 ti,davinci-gpio-unbanked = <0>; 1554 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1555 clocks = <&k3_clks 109 0>; 1556 clock-names = "gpio"; 1557 status = "disabled"; 1558 }; 1559 1560 main_gpio5: gpio@621000 { 1561 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1562 reg = <0x0 0x00621000 0x0 0x100>; 1563 gpio-controller; 1564 #gpio-cells = <2>; 1565 interrupt-parent = <&main_gpio_intr>; 1566 interrupts = <296>, <297>, <298>; 1567 interrupt-controller; 1568 #interrupt-cells = <2>; 1569 ti,ngpio = <36>; 1570 ti,davinci-gpio-unbanked = <0>; 1571 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1572 clocks = <&k3_clks 110 0>; 1573 clock-names = "gpio"; 1574 status = "disabled"; 1575 }; 1576 1577 main_gpio6: gpio@630000 { 1578 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1579 reg = <0x0 0x00630000 0x0 0x100>; 1580 gpio-controller; 1581 #gpio-cells = <2>; 1582 interrupt-parent = <&main_gpio_intr>; 1583 interrupts = <280>, <281>, <282>, <283>, 1584 <284>, <285>, <286>, <287>; 1585 interrupt-controller; 1586 #interrupt-cells = <2>; 1587 ti,ngpio = <128>; 1588 ti,davinci-gpio-unbanked = <0>; 1589 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1590 clocks = <&k3_clks 111 0>; 1591 clock-names = "gpio"; 1592 status = "disabled"; 1593 }; 1594 1595 main_gpio7: gpio@631000 { 1596 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1597 reg = <0x0 0x00631000 0x0 0x100>; 1598 gpio-controller; 1599 #gpio-cells = <2>; 1600 interrupt-parent = <&main_gpio_intr>; 1601 interrupts = <300>, <301>, <302>; 1602 interrupt-controller; 1603 #interrupt-cells = <2>; 1604 ti,ngpio = <36>; 1605 ti,davinci-gpio-unbanked = <0>; 1606 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1607 clocks = <&k3_clks 112 0>; 1608 clock-names = "gpio"; 1609 status = "disabled"; 1610 }; 1611 1612 main_sdhci0: mmc@4f80000 { 1613 compatible = "ti,j721e-sdhci-8bit"; 1614 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1615 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1616 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1617 clock-names = "clk_ahb", "clk_xin"; 1618 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1619 assigned-clocks = <&k3_clks 91 1>; 1620 assigned-clock-parents = <&k3_clks 91 2>; 1621 bus-width = <8>; 1622 mmc-hs200-1_8v; 1623 mmc-ddr-1_8v; 1624 ti,otap-del-sel-legacy = <0x0>; 1625 ti,otap-del-sel-mmc-hs = <0x0>; 1626 ti,otap-del-sel-ddr52 = <0x5>; 1627 ti,otap-del-sel-hs200 = <0x6>; 1628 ti,otap-del-sel-hs400 = <0x0>; 1629 ti,itap-del-sel-legacy = <0x10>; 1630 ti,itap-del-sel-mmc-hs = <0xa>; 1631 ti,itap-del-sel-ddr52 = <0x3>; 1632 ti,trm-icp = <0x8>; 1633 dma-coherent; 1634 status = "disabled"; 1635 }; 1636 1637 main_sdhci1: mmc@4fb0000 { 1638 compatible = "ti,j721e-sdhci-4bit"; 1639 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1640 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1641 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1642 clock-names = "clk_ahb", "clk_xin"; 1643 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1644 assigned-clocks = <&k3_clks 92 0>; 1645 assigned-clock-parents = <&k3_clks 92 1>; 1646 ti,otap-del-sel-legacy = <0x0>; 1647 ti,otap-del-sel-sd-hs = <0x0>; 1648 ti,otap-del-sel-sdr12 = <0xf>; 1649 ti,otap-del-sel-sdr25 = <0xf>; 1650 ti,otap-del-sel-sdr50 = <0xc>; 1651 ti,otap-del-sel-ddr50 = <0xc>; 1652 ti,otap-del-sel-sdr104 = <0x5>; 1653 ti,itap-del-sel-legacy = <0x0>; 1654 ti,itap-del-sel-sd-hs = <0x0>; 1655 ti,itap-del-sel-sdr12 = <0x0>; 1656 ti,itap-del-sel-sdr25 = <0x0>; 1657 ti,itap-del-sel-ddr50 = <0x2>; 1658 ti,trm-icp = <0x8>; 1659 ti,clkbuf-sel = <0x7>; 1660 dma-coherent; 1661 sdhci-caps-mask = <0x2 0x0>; 1662 status = "disabled"; 1663 }; 1664 1665 main_sdhci2: mmc@4f98000 { 1666 compatible = "ti,j721e-sdhci-4bit"; 1667 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1668 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1669 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1670 clock-names = "clk_ahb", "clk_xin"; 1671 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1672 assigned-clocks = <&k3_clks 93 0>; 1673 assigned-clock-parents = <&k3_clks 93 1>; 1674 ti,otap-del-sel-legacy = <0x0>; 1675 ti,otap-del-sel-sd-hs = <0x0>; 1676 ti,otap-del-sel-sdr12 = <0xf>; 1677 ti,otap-del-sel-sdr25 = <0xf>; 1678 ti,otap-del-sel-sdr50 = <0xc>; 1679 ti,otap-del-sel-ddr50 = <0xc>; 1680 ti,otap-del-sel-sdr104 = <0x5>; 1681 ti,itap-del-sel-legacy = <0x0>; 1682 ti,itap-del-sel-sd-hs = <0x0>; 1683 ti,itap-del-sel-sdr12 = <0x0>; 1684 ti,itap-del-sel-sdr25 = <0x0>; 1685 ti,itap-del-sel-ddr50 = <0x2>; 1686 ti,trm-icp = <0x8>; 1687 ti,clkbuf-sel = <0x7>; 1688 dma-coherent; 1689 sdhci-caps-mask = <0x2 0x0>; 1690 status = "disabled"; 1691 }; 1692 1693 usbss0: cdns-usb@4104000 { 1694 compatible = "ti,j721e-usb"; 1695 reg = <0x00 0x4104000 0x00 0x100>; 1696 dma-coherent; 1697 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1698 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1699 clock-names = "ref", "lpm"; 1700 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1701 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1702 #address-cells = <2>; 1703 #size-cells = <2>; 1704 ranges; 1705 1706 usb0: usb@6000000 { 1707 compatible = "cdns,usb3"; 1708 reg = <0x00 0x6000000 0x00 0x10000>, 1709 <0x00 0x6010000 0x00 0x10000>, 1710 <0x00 0x6020000 0x00 0x10000>; 1711 reg-names = "otg", "xhci", "dev"; 1712 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1713 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1714 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1715 interrupt-names = "host", 1716 "peripheral", 1717 "otg"; 1718 maximum-speed = "super-speed"; 1719 dr_mode = "otg"; 1720 }; 1721 }; 1722 1723 usbss1: cdns-usb@4114000 { 1724 compatible = "ti,j721e-usb"; 1725 reg = <0x00 0x4114000 0x00 0x100>; 1726 dma-coherent; 1727 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1728 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1729 clock-names = "ref", "lpm"; 1730 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1731 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1732 #address-cells = <2>; 1733 #size-cells = <2>; 1734 ranges; 1735 1736 usb1: usb@6400000 { 1737 compatible = "cdns,usb3"; 1738 reg = <0x00 0x6400000 0x00 0x10000>, 1739 <0x00 0x6410000 0x00 0x10000>, 1740 <0x00 0x6420000 0x00 0x10000>; 1741 reg-names = "otg", "xhci", "dev"; 1742 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1743 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1744 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1745 interrupt-names = "host", 1746 "peripheral", 1747 "otg"; 1748 maximum-speed = "super-speed"; 1749 dr_mode = "otg"; 1750 }; 1751 }; 1752 1753 main_i2c0: i2c@2000000 { 1754 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1755 reg = <0x0 0x2000000 0x0 0x100>; 1756 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 clock-names = "fck"; 1760 clocks = <&k3_clks 187 0>; 1761 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1762 status = "disabled"; 1763 }; 1764 1765 main_i2c1: i2c@2010000 { 1766 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1767 reg = <0x0 0x2010000 0x0 0x100>; 1768 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 clock-names = "fck"; 1772 clocks = <&k3_clks 188 0>; 1773 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1774 status = "disabled"; 1775 }; 1776 1777 main_i2c2: i2c@2020000 { 1778 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1779 reg = <0x0 0x2020000 0x0 0x100>; 1780 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1781 #address-cells = <1>; 1782 #size-cells = <0>; 1783 clock-names = "fck"; 1784 clocks = <&k3_clks 189 0>; 1785 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1786 status = "disabled"; 1787 }; 1788 1789 main_i2c3: i2c@2030000 { 1790 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1791 reg = <0x0 0x2030000 0x0 0x100>; 1792 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 clock-names = "fck"; 1796 clocks = <&k3_clks 190 0>; 1797 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1798 status = "disabled"; 1799 }; 1800 1801 main_i2c4: i2c@2040000 { 1802 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1803 reg = <0x0 0x2040000 0x0 0x100>; 1804 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 clock-names = "fck"; 1808 clocks = <&k3_clks 191 0>; 1809 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1810 status = "disabled"; 1811 }; 1812 1813 main_i2c5: i2c@2050000 { 1814 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1815 reg = <0x0 0x2050000 0x0 0x100>; 1816 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 clock-names = "fck"; 1820 clocks = <&k3_clks 192 0>; 1821 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1822 status = "disabled"; 1823 }; 1824 1825 main_i2c6: i2c@2060000 { 1826 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1827 reg = <0x0 0x2060000 0x0 0x100>; 1828 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 clock-names = "fck"; 1832 clocks = <&k3_clks 193 0>; 1833 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1834 status = "disabled"; 1835 }; 1836 1837 ufs_wrapper: ufs-wrapper@4e80000 { 1838 compatible = "ti,j721e-ufs"; 1839 reg = <0x0 0x4e80000 0x0 0x100>; 1840 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1841 clocks = <&k3_clks 277 1>; 1842 assigned-clocks = <&k3_clks 277 1>; 1843 assigned-clock-parents = <&k3_clks 277 4>; 1844 ranges; 1845 #address-cells = <2>; 1846 #size-cells = <2>; 1847 1848 ufs@4e84000 { 1849 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1850 reg = <0x0 0x4e84000 0x0 0x10000>; 1851 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1852 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1853 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1854 clock-names = "core_clk", "phy_clk", "ref_clk"; 1855 dma-coherent; 1856 }; 1857 }; 1858 1859 mhdp: dp-bridge@a000000 { 1860 compatible = "ti,j721e-mhdp8546"; 1861 /* 1862 * Note: we do not map DPTX PHY area, as that is handled by 1863 * the PHY driver. 1864 */ 1865 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1866 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1867 reg-names = "mhdptx", "j721e-intg"; 1868 1869 clocks = <&k3_clks 151 36>; 1870 1871 interrupt-parent = <&gic500>; 1872 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1873 1874 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1875 1876 dp0_ports: ports { 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 1880 port@0 { 1881 reg = <0>; 1882 }; 1883 1884 port@4 { 1885 reg = <4>; 1886 }; 1887 }; 1888 }; 1889 1890 dphy2: phy@4480000 { 1891 compatible = "ti,j721e-dphy"; 1892 reg = <0x00 0x04480000 0x00 0x1000>; 1893 clocks = <&k3_clks 296 1>, <&k3_clks 296 3>; 1894 clock-names = "psm", "pll_ref"; 1895 #phy-cells = <0>; 1896 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; 1897 assigned-clocks = <&k3_clks 296 3>; 1898 assigned-clock-parents = <&k3_clks 296 4>; 1899 assigned-clock-rates = <19200000>; 1900 status = "disabled"; 1901 }; 1902 1903 dsi0: dsi@4800000 { 1904 compatible = "ti,j721e-dsi"; 1905 reg = <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>; 1906 clocks = <&k3_clks 150 1>, <&k3_clks 150 5>; 1907 clock-names = "dsi_p_clk", "dsi_sys_clk"; 1908 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; 1909 interrupt-parent = <&gic500>; 1910 interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1911 phys = <&dphy2>; 1912 phy-names = "dphy"; 1913 status = "disabled"; 1914 1915 dsi0_ports: ports { 1916 #address-cells = <1>; 1917 #size-cells = <0>; 1918 1919 port@0 { 1920 reg = <0>; 1921 }; 1922 1923 port@1 { 1924 reg = <1>; 1925 }; 1926 }; 1927 }; 1928 1929 dss: dss@4a00000 { 1930 compatible = "ti,j721e-dss"; 1931 reg = 1932 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1933 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1934 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1935 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1936 1937 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1938 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1939 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1940 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1941 1942 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1943 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1944 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1945 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1946 1947 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1948 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1949 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1950 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1951 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1952 1953 reg-names = "common_m", "common_s0", 1954 "common_s1", "common_s2", 1955 "vidl1", "vidl2","vid1","vid2", 1956 "ovr1", "ovr2", "ovr3", "ovr4", 1957 "vp1", "vp2", "vp3", "vp4", 1958 "wb"; 1959 1960 clocks = <&k3_clks 152 0>, 1961 <&k3_clks 152 1>, 1962 <&k3_clks 152 4>, 1963 <&k3_clks 152 9>, 1964 <&k3_clks 152 13>; 1965 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1966 1967 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1968 1969 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "common_m", 1974 "common_s0", 1975 "common_s1", 1976 "common_s2"; 1977 1978 dss_ports: ports { 1979 }; 1980 }; 1981 1982 mcasp0: mcasp@2b00000 { 1983 compatible = "ti,am33xx-mcasp-audio"; 1984 reg = <0x0 0x02b00000 0x0 0x2000>, 1985 <0x0 0x02b08000 0x0 0x1000>; 1986 reg-names = "mpu","dat"; 1987 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1989 interrupt-names = "tx", "rx"; 1990 1991 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1992 dma-names = "tx", "rx"; 1993 1994 clocks = <&k3_clks 174 1>; 1995 clock-names = "fck"; 1996 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1997 status = "disabled"; 1998 }; 1999 2000 mcasp1: mcasp@2b10000 { 2001 compatible = "ti,am33xx-mcasp-audio"; 2002 reg = <0x0 0x02b10000 0x0 0x2000>, 2003 <0x0 0x02b18000 0x0 0x1000>; 2004 reg-names = "mpu","dat"; 2005 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 2007 interrupt-names = "tx", "rx"; 2008 2009 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 2010 dma-names = "tx", "rx"; 2011 2012 clocks = <&k3_clks 175 1>; 2013 clock-names = "fck"; 2014 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 2015 status = "disabled"; 2016 }; 2017 2018 mcasp2: mcasp@2b20000 { 2019 compatible = "ti,am33xx-mcasp-audio"; 2020 reg = <0x0 0x02b20000 0x0 0x2000>, 2021 <0x0 0x02b28000 0x0 0x1000>; 2022 reg-names = "mpu","dat"; 2023 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 2025 interrupt-names = "tx", "rx"; 2026 2027 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 2028 dma-names = "tx", "rx"; 2029 2030 clocks = <&k3_clks 176 1>; 2031 clock-names = "fck"; 2032 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 2033 status = "disabled"; 2034 }; 2035 2036 mcasp3: mcasp@2b30000 { 2037 compatible = "ti,am33xx-mcasp-audio"; 2038 reg = <0x0 0x02b30000 0x0 0x2000>, 2039 <0x0 0x02b38000 0x0 0x1000>; 2040 reg-names = "mpu","dat"; 2041 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 2043 interrupt-names = "tx", "rx"; 2044 2045 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 2046 dma-names = "tx", "rx"; 2047 2048 clocks = <&k3_clks 177 1>; 2049 clock-names = "fck"; 2050 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 2051 status = "disabled"; 2052 }; 2053 2054 mcasp4: mcasp@2b40000 { 2055 compatible = "ti,am33xx-mcasp-audio"; 2056 reg = <0x0 0x02b40000 0x0 0x2000>, 2057 <0x0 0x02b48000 0x0 0x1000>; 2058 reg-names = "mpu","dat"; 2059 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 2061 interrupt-names = "tx", "rx"; 2062 2063 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 2064 dma-names = "tx", "rx"; 2065 2066 clocks = <&k3_clks 178 1>; 2067 clock-names = "fck"; 2068 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 2069 status = "disabled"; 2070 }; 2071 2072 mcasp5: mcasp@2b50000 { 2073 compatible = "ti,am33xx-mcasp-audio"; 2074 reg = <0x0 0x02b50000 0x0 0x2000>, 2075 <0x0 0x02b58000 0x0 0x1000>; 2076 reg-names = "mpu","dat"; 2077 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 2079 interrupt-names = "tx", "rx"; 2080 2081 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 2082 dma-names = "tx", "rx"; 2083 2084 clocks = <&k3_clks 179 1>; 2085 clock-names = "fck"; 2086 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 2087 status = "disabled"; 2088 }; 2089 2090 mcasp6: mcasp@2b60000 { 2091 compatible = "ti,am33xx-mcasp-audio"; 2092 reg = <0x0 0x02b60000 0x0 0x2000>, 2093 <0x0 0x02b68000 0x0 0x1000>; 2094 reg-names = "mpu","dat"; 2095 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 2097 interrupt-names = "tx", "rx"; 2098 2099 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 2100 dma-names = "tx", "rx"; 2101 2102 clocks = <&k3_clks 180 1>; 2103 clock-names = "fck"; 2104 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 2105 status = "disabled"; 2106 }; 2107 2108 mcasp7: mcasp@2b70000 { 2109 compatible = "ti,am33xx-mcasp-audio"; 2110 reg = <0x0 0x02b70000 0x0 0x2000>, 2111 <0x0 0x02b78000 0x0 0x1000>; 2112 reg-names = "mpu","dat"; 2113 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 2115 interrupt-names = "tx", "rx"; 2116 2117 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 2118 dma-names = "tx", "rx"; 2119 2120 clocks = <&k3_clks 181 1>; 2121 clock-names = "fck"; 2122 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 2123 status = "disabled"; 2124 }; 2125 2126 mcasp8: mcasp@2b80000 { 2127 compatible = "ti,am33xx-mcasp-audio"; 2128 reg = <0x0 0x02b80000 0x0 0x2000>, 2129 <0x0 0x02b88000 0x0 0x1000>; 2130 reg-names = "mpu","dat"; 2131 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 2133 interrupt-names = "tx", "rx"; 2134 2135 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 2136 dma-names = "tx", "rx"; 2137 2138 clocks = <&k3_clks 182 1>; 2139 clock-names = "fck"; 2140 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 2141 status = "disabled"; 2142 }; 2143 2144 mcasp9: mcasp@2b90000 { 2145 compatible = "ti,am33xx-mcasp-audio"; 2146 reg = <0x0 0x02b90000 0x0 0x2000>, 2147 <0x0 0x02b98000 0x0 0x1000>; 2148 reg-names = "mpu","dat"; 2149 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 2151 interrupt-names = "tx", "rx"; 2152 2153 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 2154 dma-names = "tx", "rx"; 2155 2156 clocks = <&k3_clks 183 1>; 2157 clock-names = "fck"; 2158 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 2159 status = "disabled"; 2160 }; 2161 2162 mcasp10: mcasp@2ba0000 { 2163 compatible = "ti,am33xx-mcasp-audio"; 2164 reg = <0x0 0x02ba0000 0x0 0x2000>, 2165 <0x0 0x02ba8000 0x0 0x1000>; 2166 reg-names = "mpu","dat"; 2167 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 2169 interrupt-names = "tx", "rx"; 2170 2171 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 2172 dma-names = "tx", "rx"; 2173 2174 clocks = <&k3_clks 184 1>; 2175 clock-names = "fck"; 2176 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 2177 status = "disabled"; 2178 }; 2179 2180 mcasp11: mcasp@2bb0000 { 2181 compatible = "ti,am33xx-mcasp-audio"; 2182 reg = <0x0 0x02bb0000 0x0 0x2000>, 2183 <0x0 0x02bb8000 0x0 0x1000>; 2184 reg-names = "mpu","dat"; 2185 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 2187 interrupt-names = "tx", "rx"; 2188 2189 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 2190 dma-names = "tx", "rx"; 2191 2192 clocks = <&k3_clks 185 1>; 2193 clock-names = "fck"; 2194 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 2195 status = "disabled"; 2196 }; 2197 2198 watchdog0: watchdog@2200000 { 2199 compatible = "ti,j7-rti-wdt"; 2200 reg = <0x0 0x2200000 0x0 0x100>; 2201 clocks = <&k3_clks 252 1>; 2202 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 2203 assigned-clocks = <&k3_clks 252 1>; 2204 assigned-clock-parents = <&k3_clks 252 5>; 2205 }; 2206 2207 watchdog1: watchdog@2210000 { 2208 compatible = "ti,j7-rti-wdt"; 2209 reg = <0x0 0x2210000 0x0 0x100>; 2210 clocks = <&k3_clks 253 1>; 2211 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 2212 assigned-clocks = <&k3_clks 253 1>; 2213 assigned-clock-parents = <&k3_clks 253 5>; 2214 }; 2215 2216 main_r5fss0: r5fss@5c00000 { 2217 compatible = "ti,j721e-r5fss"; 2218 ti,cluster-mode = <1>; 2219 #address-cells = <1>; 2220 #size-cells = <1>; 2221 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2222 <0x5d00000 0x00 0x5d00000 0x20000>; 2223 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 2224 status = "disabled"; 2225 2226 main_r5fss0_core0: r5f@5c00000 { 2227 compatible = "ti,j721e-r5f"; 2228 reg = <0x5c00000 0x00008000>, 2229 <0x5c10000 0x00008000>; 2230 reg-names = "atcm", "btcm"; 2231 ti,sci = <&dmsc>; 2232 ti,sci-dev-id = <245>; 2233 ti,sci-proc-ids = <0x06 0xff>; 2234 resets = <&k3_reset 245 1>; 2235 firmware-name = "j7-main-r5f0_0-fw"; 2236 ti,atcm-enable = <1>; 2237 ti,btcm-enable = <1>; 2238 ti,loczrama = <1>; 2239 status = "disabled"; 2240 }; 2241 2242 main_r5fss0_core1: r5f@5d00000 { 2243 compatible = "ti,j721e-r5f"; 2244 reg = <0x5d00000 0x00008000>, 2245 <0x5d10000 0x00008000>; 2246 reg-names = "atcm", "btcm"; 2247 ti,sci = <&dmsc>; 2248 ti,sci-dev-id = <246>; 2249 ti,sci-proc-ids = <0x07 0xff>; 2250 resets = <&k3_reset 246 1>; 2251 firmware-name = "j7-main-r5f0_1-fw"; 2252 ti,atcm-enable = <1>; 2253 ti,btcm-enable = <1>; 2254 ti,loczrama = <1>; 2255 status = "disabled"; 2256 }; 2257 }; 2258 2259 main_r5fss1: r5fss@5e00000 { 2260 compatible = "ti,j721e-r5fss"; 2261 ti,cluster-mode = <1>; 2262 #address-cells = <1>; 2263 #size-cells = <1>; 2264 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2265 <0x5f00000 0x00 0x5f00000 0x20000>; 2266 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 2267 status = "disabled"; 2268 2269 main_r5fss1_core0: r5f@5e00000 { 2270 compatible = "ti,j721e-r5f"; 2271 reg = <0x5e00000 0x00008000>, 2272 <0x5e10000 0x00008000>; 2273 reg-names = "atcm", "btcm"; 2274 ti,sci = <&dmsc>; 2275 ti,sci-dev-id = <247>; 2276 ti,sci-proc-ids = <0x08 0xff>; 2277 resets = <&k3_reset 247 1>; 2278 firmware-name = "j7-main-r5f1_0-fw"; 2279 ti,atcm-enable = <1>; 2280 ti,btcm-enable = <1>; 2281 ti,loczrama = <1>; 2282 status = "disabled"; 2283 }; 2284 2285 main_r5fss1_core1: r5f@5f00000 { 2286 compatible = "ti,j721e-r5f"; 2287 reg = <0x5f00000 0x00008000>, 2288 <0x5f10000 0x00008000>; 2289 reg-names = "atcm", "btcm"; 2290 ti,sci = <&dmsc>; 2291 ti,sci-dev-id = <248>; 2292 ti,sci-proc-ids = <0x09 0xff>; 2293 resets = <&k3_reset 248 1>; 2294 firmware-name = "j7-main-r5f1_1-fw"; 2295 ti,atcm-enable = <1>; 2296 ti,btcm-enable = <1>; 2297 ti,loczrama = <1>; 2298 status = "disabled"; 2299 }; 2300 }; 2301 2302 c66_0: dsp@4d80800000 { 2303 compatible = "ti,j721e-c66-dsp"; 2304 reg = <0x4d 0x80800000 0x00 0x00048000>, 2305 <0x4d 0x80e00000 0x00 0x00008000>, 2306 <0x4d 0x80f00000 0x00 0x00008000>; 2307 reg-names = "l2sram", "l1pram", "l1dram"; 2308 ti,sci = <&dmsc>; 2309 ti,sci-dev-id = <142>; 2310 ti,sci-proc-ids = <0x03 0xff>; 2311 resets = <&k3_reset 142 1>; 2312 firmware-name = "j7-c66_0-fw"; 2313 status = "disabled"; 2314 }; 2315 2316 c66_1: dsp@4d81800000 { 2317 compatible = "ti,j721e-c66-dsp"; 2318 reg = <0x4d 0x81800000 0x00 0x00048000>, 2319 <0x4d 0x81e00000 0x00 0x00008000>, 2320 <0x4d 0x81f00000 0x00 0x00008000>; 2321 reg-names = "l2sram", "l1pram", "l1dram"; 2322 ti,sci = <&dmsc>; 2323 ti,sci-dev-id = <143>; 2324 ti,sci-proc-ids = <0x04 0xff>; 2325 resets = <&k3_reset 143 1>; 2326 firmware-name = "j7-c66_1-fw"; 2327 status = "disabled"; 2328 }; 2329 2330 c71_0: dsp@64800000 { 2331 compatible = "ti,j721e-c71-dsp"; 2332 reg = <0x00 0x64800000 0x00 0x00080000>, 2333 <0x00 0x64e00000 0x00 0x0000c000>; 2334 reg-names = "l2sram", "l1dram"; 2335 ti,sci = <&dmsc>; 2336 ti,sci-dev-id = <15>; 2337 ti,sci-proc-ids = <0x30 0xff>; 2338 resets = <&k3_reset 15 1>; 2339 firmware-name = "j7-c71_0-fw"; 2340 status = "disabled"; 2341 }; 2342 2343 icssg0: icssg@b000000 { 2344 compatible = "ti,j721e-icssg"; 2345 reg = <0x00 0xb000000 0x00 0x80000>; 2346 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 2347 #address-cells = <1>; 2348 #size-cells = <1>; 2349 ranges = <0x0 0x00 0x0b000000 0x100000>; 2350 2351 icssg0_mem: memories@0 { 2352 reg = <0x0 0x2000>, 2353 <0x2000 0x2000>, 2354 <0x10000 0x10000>; 2355 reg-names = "dram0", "dram1", 2356 "shrdram2"; 2357 }; 2358 2359 icssg0_cfg: cfg@26000 { 2360 compatible = "ti,pruss-cfg", "syscon"; 2361 reg = <0x26000 0x200>; 2362 #address-cells = <1>; 2363 #size-cells = <1>; 2364 ranges = <0x0 0x26000 0x2000>; 2365 2366 clocks { 2367 #address-cells = <1>; 2368 #size-cells = <0>; 2369 2370 icssg0_coreclk_mux: coreclk-mux@3c { 2371 reg = <0x3c>; 2372 #clock-cells = <0>; 2373 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 2374 <&k3_clks 119 1>; /* icssg0_iclk */ 2375 assigned-clocks = <&icssg0_coreclk_mux>; 2376 assigned-clock-parents = <&k3_clks 119 1>; 2377 }; 2378 2379 icssg0_iepclk_mux: iepclk-mux@30 { 2380 reg = <0x30>; 2381 #clock-cells = <0>; 2382 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 2383 <&icssg0_coreclk_mux>; /* core_clk */ 2384 assigned-clocks = <&icssg0_iepclk_mux>; 2385 assigned-clock-parents = <&icssg0_coreclk_mux>; 2386 }; 2387 }; 2388 }; 2389 2390 icssg0_mii_rt: mii-rt@32000 { 2391 compatible = "ti,pruss-mii", "syscon"; 2392 reg = <0x32000 0x100>; 2393 }; 2394 2395 icssg0_mii_g_rt: mii-g-rt@33000 { 2396 compatible = "ti,pruss-mii-g", "syscon"; 2397 reg = <0x33000 0x1000>; 2398 }; 2399 2400 icssg0_intc: interrupt-controller@20000 { 2401 compatible = "ti,icssg-intc"; 2402 reg = <0x20000 0x2000>; 2403 interrupt-controller; 2404 #interrupt-cells = <3>; 2405 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2409 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2410 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 2411 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2412 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 2413 interrupt-names = "host_intr0", "host_intr1", 2414 "host_intr2", "host_intr3", 2415 "host_intr4", "host_intr5", 2416 "host_intr6", "host_intr7"; 2417 }; 2418 2419 pru0_0: pru@34000 { 2420 compatible = "ti,j721e-pru"; 2421 reg = <0x34000 0x3000>, 2422 <0x22000 0x100>, 2423 <0x22400 0x100>; 2424 reg-names = "iram", "control", "debug"; 2425 firmware-name = "j7-pru0_0-fw"; 2426 }; 2427 2428 rtu0_0: rtu@4000 { 2429 compatible = "ti,j721e-rtu"; 2430 reg = <0x4000 0x2000>, 2431 <0x23000 0x100>, 2432 <0x23400 0x100>; 2433 reg-names = "iram", "control", "debug"; 2434 firmware-name = "j7-rtu0_0-fw"; 2435 }; 2436 2437 tx_pru0_0: txpru@a000 { 2438 compatible = "ti,j721e-tx-pru"; 2439 reg = <0xa000 0x1800>, 2440 <0x25000 0x100>, 2441 <0x25400 0x100>; 2442 reg-names = "iram", "control", "debug"; 2443 firmware-name = "j7-txpru0_0-fw"; 2444 }; 2445 2446 pru0_1: pru@38000 { 2447 compatible = "ti,j721e-pru"; 2448 reg = <0x38000 0x3000>, 2449 <0x24000 0x100>, 2450 <0x24400 0x100>; 2451 reg-names = "iram", "control", "debug"; 2452 firmware-name = "j7-pru0_1-fw"; 2453 }; 2454 2455 rtu0_1: rtu@6000 { 2456 compatible = "ti,j721e-rtu"; 2457 reg = <0x6000 0x2000>, 2458 <0x23800 0x100>, 2459 <0x23c00 0x100>; 2460 reg-names = "iram", "control", "debug"; 2461 firmware-name = "j7-rtu0_1-fw"; 2462 }; 2463 2464 tx_pru0_1: txpru@c000 { 2465 compatible = "ti,j721e-tx-pru"; 2466 reg = <0xc000 0x1800>, 2467 <0x25800 0x100>, 2468 <0x25c00 0x100>; 2469 reg-names = "iram", "control", "debug"; 2470 firmware-name = "j7-txpru0_1-fw"; 2471 }; 2472 2473 icssg0_mdio: mdio@32400 { 2474 compatible = "ti,davinci_mdio"; 2475 reg = <0x32400 0x100>; 2476 clocks = <&k3_clks 119 1>; 2477 clock-names = "fck"; 2478 #address-cells = <1>; 2479 #size-cells = <0>; 2480 bus_freq = <1000000>; 2481 status = "disabled"; 2482 }; 2483 }; 2484 2485 icssg1: icssg@b100000 { 2486 compatible = "ti,j721e-icssg"; 2487 reg = <0x00 0xb100000 0x00 0x80000>; 2488 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 2489 #address-cells = <1>; 2490 #size-cells = <1>; 2491 ranges = <0x0 0x00 0x0b100000 0x100000>; 2492 2493 icssg1_mem: memories@b100000 { 2494 reg = <0x0 0x2000>, 2495 <0x2000 0x2000>, 2496 <0x10000 0x10000>; 2497 reg-names = "dram0", "dram1", 2498 "shrdram2"; 2499 }; 2500 2501 icssg1_cfg: cfg@26000 { 2502 compatible = "ti,pruss-cfg", "syscon"; 2503 reg = <0x26000 0x200>; 2504 #address-cells = <1>; 2505 #size-cells = <1>; 2506 ranges = <0x0 0x26000 0x2000>; 2507 2508 clocks { 2509 #address-cells = <1>; 2510 #size-cells = <0>; 2511 2512 icssg1_coreclk_mux: coreclk-mux@3c { 2513 reg = <0x3c>; 2514 #clock-cells = <0>; 2515 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 2516 <&k3_clks 120 4>; /* icssg1_iclk */ 2517 assigned-clocks = <&icssg1_coreclk_mux>; 2518 assigned-clock-parents = <&k3_clks 120 4>; 2519 }; 2520 2521 icssg1_iepclk_mux: iepclk-mux@30 { 2522 reg = <0x30>; 2523 #clock-cells = <0>; 2524 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 2525 <&icssg1_coreclk_mux>; /* core_clk */ 2526 assigned-clocks = <&icssg1_iepclk_mux>; 2527 assigned-clock-parents = <&icssg1_coreclk_mux>; 2528 }; 2529 }; 2530 }; 2531 2532 icssg1_mii_rt: mii-rt@32000 { 2533 compatible = "ti,pruss-mii", "syscon"; 2534 reg = <0x32000 0x100>; 2535 }; 2536 2537 icssg1_mii_g_rt: mii-g-rt@33000 { 2538 compatible = "ti,pruss-mii-g", "syscon"; 2539 reg = <0x33000 0x1000>; 2540 }; 2541 2542 icssg1_intc: interrupt-controller@20000 { 2543 compatible = "ti,icssg-intc"; 2544 reg = <0x20000 0x2000>; 2545 interrupt-controller; 2546 #interrupt-cells = <3>; 2547 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2554 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2555 interrupt-names = "host_intr0", "host_intr1", 2556 "host_intr2", "host_intr3", 2557 "host_intr4", "host_intr5", 2558 "host_intr6", "host_intr7"; 2559 }; 2560 2561 pru1_0: pru@34000 { 2562 compatible = "ti,j721e-pru"; 2563 reg = <0x34000 0x4000>, 2564 <0x22000 0x100>, 2565 <0x22400 0x100>; 2566 reg-names = "iram", "control", "debug"; 2567 firmware-name = "j7-pru1_0-fw"; 2568 }; 2569 2570 rtu1_0: rtu@4000 { 2571 compatible = "ti,j721e-rtu"; 2572 reg = <0x4000 0x2000>, 2573 <0x23000 0x100>, 2574 <0x23400 0x100>; 2575 reg-names = "iram", "control", "debug"; 2576 firmware-name = "j7-rtu1_0-fw"; 2577 }; 2578 2579 tx_pru1_0: txpru@a000 { 2580 compatible = "ti,j721e-tx-pru"; 2581 reg = <0xa000 0x1800>, 2582 <0x25000 0x100>, 2583 <0x25400 0x100>; 2584 reg-names = "iram", "control", "debug"; 2585 firmware-name = "j7-txpru1_0-fw"; 2586 }; 2587 2588 pru1_1: pru@38000 { 2589 compatible = "ti,j721e-pru"; 2590 reg = <0x38000 0x4000>, 2591 <0x24000 0x100>, 2592 <0x24400 0x100>; 2593 reg-names = "iram", "control", "debug"; 2594 firmware-name = "j7-pru1_1-fw"; 2595 }; 2596 2597 rtu1_1: rtu@6000 { 2598 compatible = "ti,j721e-rtu"; 2599 reg = <0x6000 0x2000>, 2600 <0x23800 0x100>, 2601 <0x23c00 0x100>; 2602 reg-names = "iram", "control", "debug"; 2603 firmware-name = "j7-rtu1_1-fw"; 2604 }; 2605 2606 tx_pru1_1: txpru@c000 { 2607 compatible = "ti,j721e-tx-pru"; 2608 reg = <0xc000 0x1800>, 2609 <0x25800 0x100>, 2610 <0x25c00 0x100>; 2611 reg-names = "iram", "control", "debug"; 2612 firmware-name = "j7-txpru1_1-fw"; 2613 }; 2614 2615 icssg1_mdio: mdio@32400 { 2616 compatible = "ti,davinci_mdio"; 2617 reg = <0x32400 0x100>; 2618 clocks = <&k3_clks 120 4>; 2619 clock-names = "fck"; 2620 #address-cells = <1>; 2621 #size-cells = <0>; 2622 bus_freq = <1000000>; 2623 status = "disabled"; 2624 }; 2625 }; 2626 2627 main_mcan0: can@2701000 { 2628 compatible = "bosch,m_can"; 2629 reg = <0x00 0x02701000 0x00 0x200>, 2630 <0x00 0x02708000 0x00 0x8000>; 2631 reg-names = "m_can", "message_ram"; 2632 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2633 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2634 clock-names = "hclk", "cclk"; 2635 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2636 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2637 interrupt-names = "int0", "int1"; 2638 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2639 status = "disabled"; 2640 }; 2641 2642 main_mcan1: can@2711000 { 2643 compatible = "bosch,m_can"; 2644 reg = <0x00 0x02711000 0x00 0x200>, 2645 <0x00 0x02718000 0x00 0x8000>; 2646 reg-names = "m_can", "message_ram"; 2647 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2648 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2649 clock-names = "hclk", "cclk"; 2650 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2651 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2652 interrupt-names = "int0", "int1"; 2653 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2654 status = "disabled"; 2655 }; 2656 2657 main_mcan2: can@2721000 { 2658 compatible = "bosch,m_can"; 2659 reg = <0x00 0x02721000 0x00 0x200>, 2660 <0x00 0x02728000 0x00 0x8000>; 2661 reg-names = "m_can", "message_ram"; 2662 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2663 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2664 clock-names = "hclk", "cclk"; 2665 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2667 interrupt-names = "int0", "int1"; 2668 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2669 status = "disabled"; 2670 }; 2671 2672 main_mcan3: can@2731000 { 2673 compatible = "bosch,m_can"; 2674 reg = <0x00 0x02731000 0x00 0x200>, 2675 <0x00 0x02738000 0x00 0x8000>; 2676 reg-names = "m_can", "message_ram"; 2677 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2678 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2679 clock-names = "hclk", "cclk"; 2680 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2681 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2682 interrupt-names = "int0", "int1"; 2683 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2684 status = "disabled"; 2685 }; 2686 2687 main_mcan4: can@2741000 { 2688 compatible = "bosch,m_can"; 2689 reg = <0x00 0x02741000 0x00 0x200>, 2690 <0x00 0x02748000 0x00 0x8000>; 2691 reg-names = "m_can", "message_ram"; 2692 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2693 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2694 clock-names = "hclk", "cclk"; 2695 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2697 interrupt-names = "int0", "int1"; 2698 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2699 status = "disabled"; 2700 }; 2701 2702 main_mcan5: can@2751000 { 2703 compatible = "bosch,m_can"; 2704 reg = <0x00 0x02751000 0x00 0x200>, 2705 <0x00 0x02758000 0x00 0x8000>; 2706 reg-names = "m_can", "message_ram"; 2707 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2708 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2709 clock-names = "hclk", "cclk"; 2710 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2712 interrupt-names = "int0", "int1"; 2713 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2714 status = "disabled"; 2715 }; 2716 2717 main_mcan6: can@2761000 { 2718 compatible = "bosch,m_can"; 2719 reg = <0x00 0x02761000 0x00 0x200>, 2720 <0x00 0x02768000 0x00 0x8000>; 2721 reg-names = "m_can", "message_ram"; 2722 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2723 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2724 clock-names = "hclk", "cclk"; 2725 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2727 interrupt-names = "int0", "int1"; 2728 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2729 status = "disabled"; 2730 }; 2731 2732 main_mcan7: can@2771000 { 2733 compatible = "bosch,m_can"; 2734 reg = <0x00 0x02771000 0x00 0x200>, 2735 <0x00 0x02778000 0x00 0x8000>; 2736 reg-names = "m_can", "message_ram"; 2737 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2738 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2739 clock-names = "hclk", "cclk"; 2740 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2741 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2742 interrupt-names = "int0", "int1"; 2743 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2744 status = "disabled"; 2745 }; 2746 2747 main_mcan8: can@2781000 { 2748 compatible = "bosch,m_can"; 2749 reg = <0x00 0x02781000 0x00 0x200>, 2750 <0x00 0x02788000 0x00 0x8000>; 2751 reg-names = "m_can", "message_ram"; 2752 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2753 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2754 clock-names = "hclk", "cclk"; 2755 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2757 interrupt-names = "int0", "int1"; 2758 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2759 status = "disabled"; 2760 }; 2761 2762 main_mcan9: can@2791000 { 2763 compatible = "bosch,m_can"; 2764 reg = <0x00 0x02791000 0x00 0x200>, 2765 <0x00 0x02798000 0x00 0x8000>; 2766 reg-names = "m_can", "message_ram"; 2767 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2768 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2769 clock-names = "hclk", "cclk"; 2770 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2772 interrupt-names = "int0", "int1"; 2773 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2774 status = "disabled"; 2775 }; 2776 2777 main_mcan10: can@27a1000 { 2778 compatible = "bosch,m_can"; 2779 reg = <0x00 0x027a1000 0x00 0x200>, 2780 <0x00 0x027a8000 0x00 0x8000>; 2781 reg-names = "m_can", "message_ram"; 2782 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2783 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2784 clock-names = "hclk", "cclk"; 2785 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2787 interrupt-names = "int0", "int1"; 2788 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2789 status = "disabled"; 2790 }; 2791 2792 main_mcan11: can@27b1000 { 2793 compatible = "bosch,m_can"; 2794 reg = <0x00 0x027b1000 0x00 0x200>, 2795 <0x00 0x027b8000 0x00 0x8000>; 2796 reg-names = "m_can", "message_ram"; 2797 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2798 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2799 clock-names = "hclk", "cclk"; 2800 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2802 interrupt-names = "int0", "int1"; 2803 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2804 status = "disabled"; 2805 }; 2806 2807 main_mcan12: can@27c1000 { 2808 compatible = "bosch,m_can"; 2809 reg = <0x00 0x027c1000 0x00 0x200>, 2810 <0x00 0x027c8000 0x00 0x8000>; 2811 reg-names = "m_can", "message_ram"; 2812 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2813 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2814 clock-names = "hclk", "cclk"; 2815 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2817 interrupt-names = "int0", "int1"; 2818 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2819 status = "disabled"; 2820 }; 2821 2822 main_mcan13: can@27d1000 { 2823 compatible = "bosch,m_can"; 2824 reg = <0x00 0x027d1000 0x00 0x200>, 2825 <0x00 0x027d8000 0x00 0x8000>; 2826 reg-names = "m_can", "message_ram"; 2827 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2828 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2829 clock-names = "hclk", "cclk"; 2830 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2831 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2832 interrupt-names = "int0", "int1"; 2833 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2834 status = "disabled"; 2835 }; 2836 2837 main_spi0: spi@2100000 { 2838 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2839 reg = <0x00 0x02100000 0x00 0x400>; 2840 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2841 #address-cells = <1>; 2842 #size-cells = <0>; 2843 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2844 clocks = <&k3_clks 266 1>; 2845 status = "disabled"; 2846 }; 2847 2848 main_spi1: spi@2110000 { 2849 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2850 reg = <0x00 0x02110000 0x00 0x400>; 2851 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2852 #address-cells = <1>; 2853 #size-cells = <0>; 2854 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2855 clocks = <&k3_clks 267 1>; 2856 status = "disabled"; 2857 }; 2858 2859 main_spi2: spi@2120000 { 2860 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2861 reg = <0x00 0x02120000 0x00 0x400>; 2862 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2863 #address-cells = <1>; 2864 #size-cells = <0>; 2865 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2866 clocks = <&k3_clks 268 1>; 2867 status = "disabled"; 2868 }; 2869 2870 main_spi3: spi@2130000 { 2871 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2872 reg = <0x00 0x02130000 0x00 0x400>; 2873 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2874 #address-cells = <1>; 2875 #size-cells = <0>; 2876 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2877 clocks = <&k3_clks 269 1>; 2878 status = "disabled"; 2879 }; 2880 2881 main_spi4: spi@2140000 { 2882 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2883 reg = <0x00 0x02140000 0x00 0x400>; 2884 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2885 #address-cells = <1>; 2886 #size-cells = <0>; 2887 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2888 clocks = <&k3_clks 270 1>; 2889 status = "disabled"; 2890 }; 2891 2892 main_spi5: spi@2150000 { 2893 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2894 reg = <0x00 0x02150000 0x00 0x400>; 2895 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2896 #address-cells = <1>; 2897 #size-cells = <0>; 2898 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2899 clocks = <&k3_clks 271 1>; 2900 status = "disabled"; 2901 }; 2902 2903 main_spi6: spi@2160000 { 2904 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2905 reg = <0x00 0x02160000 0x00 0x400>; 2906 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2907 #address-cells = <1>; 2908 #size-cells = <0>; 2909 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2910 clocks = <&k3_clks 272 1>; 2911 status = "disabled"; 2912 }; 2913 2914 main_spi7: spi@2170000 { 2915 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2916 reg = <0x00 0x02170000 0x00 0x400>; 2917 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2918 #address-cells = <1>; 2919 #size-cells = <0>; 2920 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2921 clocks = <&k3_clks 273 1>; 2922 status = "disabled"; 2923 }; 2924 2925 main_esm: esm@700000 { 2926 compatible = "ti,j721e-esm"; 2927 reg = <0x0 0x700000 0x0 0x1000>; 2928 bootph-pre-ram; 2929 ti,esm-pins = <344>, <345>; 2930 }; 2931}; 2932