1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10 11#include "k3-serdes.h" 12 13/ { 14 cmn_refclk: clock-cmnrefclk { 15 #clock-cells = <0>; 16 compatible = "fixed-clock"; 17 clock-frequency = <0>; 18 }; 19 20 cmn_refclk1: clock-cmnrefclk1 { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <0>; 24 }; 25}; 26 27&cbass_main { 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x0 0x70000000 0x0 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x0 0x0 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x0 0x20000>; 37 }; 38 }; 39 40 scm_conf: scm-conf@100000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x00100000 0x1c000>; 46 47 serdes_ln_ctrl: mux-controller@4080 { 48 compatible = "reg-mux"; 49 reg = <0x4080 0x50>; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 52 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 53 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 54 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ 55 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ 56 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ 57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 58 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 59 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 60 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 61 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 62 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 63 }; 64 65 cpsw0_phy_gmii_sel: phy@4044 { 66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 67 ti,qsgmii-main-ports = <2>, <2>; 68 reg = <0x4044 0x20>; 69 #phy-cells = <1>; 70 }; 71 72 usb_serdes_mux: mux-controller@4000 { 73 compatible = "reg-mux"; 74 reg = <0x4000 0x20>; 75 #mux-control-cells = <1>; 76 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ 77 <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ 78 }; 79 80 ehrpwm_tbclk: clock-controller@4140 { 81 compatible = "ti,am654-ehrpwm-tbclk"; 82 reg = <0x4140 0x18>; 83 #clock-cells = <1>; 84 }; 85 }; 86 87 main_ehrpwm0: pwm@3000000 { 88 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 89 #pwm-cells = <3>; 90 reg = <0x00 0x3000000 0x00 0x100>; 91 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 92 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 93 clock-names = "tbclk", "fck"; 94 status = "disabled"; 95 }; 96 97 main_ehrpwm1: pwm@3010000 { 98 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 99 #pwm-cells = <3>; 100 reg = <0x00 0x3010000 0x00 0x100>; 101 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 102 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 103 clock-names = "tbclk", "fck"; 104 status = "disabled"; 105 }; 106 107 main_ehrpwm2: pwm@3020000 { 108 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 109 #pwm-cells = <3>; 110 reg = <0x00 0x3020000 0x00 0x100>; 111 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 112 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 113 clock-names = "tbclk", "fck"; 114 status = "disabled"; 115 }; 116 117 main_ehrpwm3: pwm@3030000 { 118 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 119 #pwm-cells = <3>; 120 reg = <0x00 0x3030000 0x00 0x100>; 121 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 123 clock-names = "tbclk", "fck"; 124 status = "disabled"; 125 }; 126 127 main_ehrpwm4: pwm@3040000 { 128 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 129 #pwm-cells = <3>; 130 reg = <0x00 0x3040000 0x00 0x100>; 131 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 132 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 133 clock-names = "tbclk", "fck"; 134 status = "disabled"; 135 }; 136 137 main_ehrpwm5: pwm@3050000 { 138 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 139 #pwm-cells = <3>; 140 reg = <0x00 0x3050000 0x00 0x100>; 141 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 142 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 143 clock-names = "tbclk", "fck"; 144 status = "disabled"; 145 }; 146 147 gic500: interrupt-controller@1800000 { 148 compatible = "arm,gic-v3"; 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 #interrupt-cells = <3>; 153 interrupt-controller; 154 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 155 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 156 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 157 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 158 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 159 160 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 161 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 162 163 gic_its: msi-controller@1820000 { 164 compatible = "arm,gic-v3-its"; 165 reg = <0x00 0x01820000 0x00 0x10000>; 166 socionext,synquacer-pre-its = <0x1000000 0x400000>; 167 msi-controller; 168 #msi-cells = <1>; 169 }; 170 }; 171 172 main_gpio_intr: interrupt-controller@a00000 { 173 compatible = "ti,sci-intr"; 174 reg = <0x00 0x00a00000 0x00 0x800>; 175 ti,intr-trigger-type = <1>; 176 interrupt-controller; 177 interrupt-parent = <&gic500>; 178 #interrupt-cells = <1>; 179 ti,sci = <&dmsc>; 180 ti,sci-dev-id = <131>; 181 ti,interrupt-ranges = <8 392 56>; 182 }; 183 184 main_navss: bus@30000000 { 185 compatible = "simple-bus"; 186 #address-cells = <2>; 187 #size-cells = <2>; 188 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 189 dma-coherent; 190 dma-ranges; 191 192 ti,sci-dev-id = <199>; 193 194 main_navss_intr: interrupt-controller@310e0000 { 195 compatible = "ti,sci-intr"; 196 reg = <0x0 0x310e0000 0x0 0x4000>; 197 ti,intr-trigger-type = <4>; 198 interrupt-controller; 199 interrupt-parent = <&gic500>; 200 #interrupt-cells = <1>; 201 ti,sci = <&dmsc>; 202 ti,sci-dev-id = <213>; 203 ti,interrupt-ranges = <0 64 64>, 204 <64 448 64>, 205 <128 672 64>; 206 }; 207 208 main_udmass_inta: interrupt-controller@33d00000 { 209 compatible = "ti,sci-inta"; 210 reg = <0x0 0x33d00000 0x0 0x100000>; 211 interrupt-controller; 212 interrupt-parent = <&main_navss_intr>; 213 msi-controller; 214 #interrupt-cells = <0>; 215 ti,sci = <&dmsc>; 216 ti,sci-dev-id = <209>; 217 ti,interrupt-ranges = <0 0 256>; 218 }; 219 220 secure_proxy_main: mailbox@32c00000 { 221 compatible = "ti,am654-secure-proxy"; 222 #mbox-cells = <1>; 223 reg-names = "target_data", "rt", "scfg"; 224 reg = <0x00 0x32c00000 0x00 0x100000>, 225 <0x00 0x32400000 0x00 0x100000>, 226 <0x00 0x32800000 0x00 0x100000>; 227 interrupt-names = "rx_011"; 228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 229 bootph-all; 230 }; 231 232 smmu0: iommu@36600000 { 233 compatible = "arm,smmu-v3"; 234 reg = <0x0 0x36600000 0x0 0x100000>; 235 interrupt-parent = <&gic500>; 236 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 237 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 238 interrupt-names = "eventq", "gerror"; 239 #iommu-cells = <1>; 240 }; 241 242 hwspinlock: spinlock@30e00000 { 243 compatible = "ti,am654-hwspinlock"; 244 reg = <0x00 0x30e00000 0x00 0x1000>; 245 #hwlock-cells = <1>; 246 }; 247 248 mailbox0_cluster0: mailbox@31f80000 { 249 compatible = "ti,am654-mailbox"; 250 reg = <0x00 0x31f80000 0x00 0x200>; 251 #mbox-cells = <1>; 252 ti,mbox-num-users = <4>; 253 ti,mbox-num-fifos = <16>; 254 interrupt-parent = <&main_navss_intr>; 255 status = "disabled"; 256 }; 257 258 mailbox0_cluster1: mailbox@31f81000 { 259 compatible = "ti,am654-mailbox"; 260 reg = <0x00 0x31f81000 0x00 0x200>; 261 #mbox-cells = <1>; 262 ti,mbox-num-users = <4>; 263 ti,mbox-num-fifos = <16>; 264 interrupt-parent = <&main_navss_intr>; 265 status = "disabled"; 266 }; 267 268 mailbox0_cluster2: mailbox@31f82000 { 269 compatible = "ti,am654-mailbox"; 270 reg = <0x00 0x31f82000 0x00 0x200>; 271 #mbox-cells = <1>; 272 ti,mbox-num-users = <4>; 273 ti,mbox-num-fifos = <16>; 274 interrupt-parent = <&main_navss_intr>; 275 status = "disabled"; 276 }; 277 278 mailbox0_cluster3: mailbox@31f83000 { 279 compatible = "ti,am654-mailbox"; 280 reg = <0x00 0x31f83000 0x00 0x200>; 281 #mbox-cells = <1>; 282 ti,mbox-num-users = <4>; 283 ti,mbox-num-fifos = <16>; 284 interrupt-parent = <&main_navss_intr>; 285 status = "disabled"; 286 }; 287 288 mailbox0_cluster4: mailbox@31f84000 { 289 compatible = "ti,am654-mailbox"; 290 reg = <0x00 0x31f84000 0x00 0x200>; 291 #mbox-cells = <1>; 292 ti,mbox-num-users = <4>; 293 ti,mbox-num-fifos = <16>; 294 interrupt-parent = <&main_navss_intr>; 295 status = "disabled"; 296 }; 297 298 mailbox0_cluster5: mailbox@31f85000 { 299 compatible = "ti,am654-mailbox"; 300 reg = <0x00 0x31f85000 0x00 0x200>; 301 #mbox-cells = <1>; 302 ti,mbox-num-users = <4>; 303 ti,mbox-num-fifos = <16>; 304 interrupt-parent = <&main_navss_intr>; 305 status = "disabled"; 306 }; 307 308 mailbox0_cluster6: mailbox@31f86000 { 309 compatible = "ti,am654-mailbox"; 310 reg = <0x00 0x31f86000 0x00 0x200>; 311 #mbox-cells = <1>; 312 ti,mbox-num-users = <4>; 313 ti,mbox-num-fifos = <16>; 314 interrupt-parent = <&main_navss_intr>; 315 status = "disabled"; 316 }; 317 318 mailbox0_cluster7: mailbox@31f87000 { 319 compatible = "ti,am654-mailbox"; 320 reg = <0x00 0x31f87000 0x00 0x200>; 321 #mbox-cells = <1>; 322 ti,mbox-num-users = <4>; 323 ti,mbox-num-fifos = <16>; 324 interrupt-parent = <&main_navss_intr>; 325 status = "disabled"; 326 }; 327 328 mailbox0_cluster8: mailbox@31f88000 { 329 compatible = "ti,am654-mailbox"; 330 reg = <0x00 0x31f88000 0x00 0x200>; 331 #mbox-cells = <1>; 332 ti,mbox-num-users = <4>; 333 ti,mbox-num-fifos = <16>; 334 interrupt-parent = <&main_navss_intr>; 335 status = "disabled"; 336 }; 337 338 mailbox0_cluster9: mailbox@31f89000 { 339 compatible = "ti,am654-mailbox"; 340 reg = <0x00 0x31f89000 0x00 0x200>; 341 #mbox-cells = <1>; 342 ti,mbox-num-users = <4>; 343 ti,mbox-num-fifos = <16>; 344 interrupt-parent = <&main_navss_intr>; 345 status = "disabled"; 346 }; 347 348 mailbox0_cluster10: mailbox@31f8a000 { 349 compatible = "ti,am654-mailbox"; 350 reg = <0x00 0x31f8a000 0x00 0x200>; 351 #mbox-cells = <1>; 352 ti,mbox-num-users = <4>; 353 ti,mbox-num-fifos = <16>; 354 interrupt-parent = <&main_navss_intr>; 355 status = "disabled"; 356 }; 357 358 mailbox0_cluster11: mailbox@31f8b000 { 359 compatible = "ti,am654-mailbox"; 360 reg = <0x00 0x31f8b000 0x00 0x200>; 361 #mbox-cells = <1>; 362 ti,mbox-num-users = <4>; 363 ti,mbox-num-fifos = <16>; 364 interrupt-parent = <&main_navss_intr>; 365 status = "disabled"; 366 }; 367 368 main_ringacc: ringacc@3c000000 { 369 compatible = "ti,am654-navss-ringacc"; 370 reg = <0x0 0x3c000000 0x0 0x400000>, 371 <0x0 0x38000000 0x0 0x400000>, 372 <0x0 0x31120000 0x0 0x100>, 373 <0x0 0x33000000 0x0 0x40000>, 374 <0x0 0x31080000 0x0 0x40000>; 375 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 376 ti,num-rings = <1024>; 377 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 378 ti,sci = <&dmsc>; 379 ti,sci-dev-id = <211>; 380 msi-parent = <&main_udmass_inta>; 381 }; 382 383 main_udmap: dma-controller@31150000 { 384 compatible = "ti,j721e-navss-main-udmap"; 385 reg = <0x0 0x31150000 0x0 0x100>, 386 <0x0 0x34000000 0x0 0x100000>, 387 <0x0 0x35000000 0x0 0x100000>, 388 <0x0 0x30b00000 0x0 0x20000>, 389 <0x0 0x30c00000 0x0 0x10000>, 390 <0x0 0x30d00000 0x0 0x8000>; 391 reg-names = "gcfg", "rchanrt", "tchanrt", 392 "tchan", "rchan", "rflow"; 393 msi-parent = <&main_udmass_inta>; 394 #dma-cells = <1>; 395 396 ti,sci = <&dmsc>; 397 ti,sci-dev-id = <212>; 398 ti,ringacc = <&main_ringacc>; 399 400 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 401 <0x0f>, /* TX_HCHAN */ 402 <0x10>; /* TX_UHCHAN */ 403 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 404 <0x0b>, /* RX_HCHAN */ 405 <0x0c>; /* RX_UHCHAN */ 406 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 407 }; 408 409 cpts@310d0000 { 410 compatible = "ti,j721e-cpts"; 411 reg = <0x0 0x310d0000 0x0 0x400>; 412 reg-names = "cpts"; 413 clocks = <&k3_clks 201 1>; 414 clock-names = "cpts"; 415 interrupts-extended = <&main_navss_intr 391>; 416 interrupt-names = "cpts"; 417 ti,cpts-periodic-outputs = <6>; 418 ti,cpts-ext-ts-inputs = <8>; 419 }; 420 }; 421 422 cpsw0: ethernet@c000000 { 423 compatible = "ti,j721e-cpswxg-nuss"; 424 #address-cells = <2>; 425 #size-cells = <2>; 426 reg = <0x0 0xc000000 0x0 0x200000>; 427 reg-names = "cpsw_nuss"; 428 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 429 clocks = <&k3_clks 19 89>; 430 clock-names = "fck"; 431 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 432 433 dmas = <&main_udmap 0xca00>, 434 <&main_udmap 0xca01>, 435 <&main_udmap 0xca02>, 436 <&main_udmap 0xca03>, 437 <&main_udmap 0xca04>, 438 <&main_udmap 0xca05>, 439 <&main_udmap 0xca06>, 440 <&main_udmap 0xca07>, 441 <&main_udmap 0x4a00>; 442 dma-names = "tx0", "tx1", "tx2", "tx3", 443 "tx4", "tx5", "tx6", "tx7", 444 "rx"; 445 446 status = "disabled"; 447 448 ethernet-ports { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 cpsw0_port1: port@1 { 452 reg = <1>; 453 ti,mac-only; 454 label = "port1"; 455 status = "disabled"; 456 }; 457 458 cpsw0_port2: port@2 { 459 reg = <2>; 460 ti,mac-only; 461 label = "port2"; 462 status = "disabled"; 463 }; 464 465 cpsw0_port3: port@3 { 466 reg = <3>; 467 ti,mac-only; 468 label = "port3"; 469 status = "disabled"; 470 }; 471 472 cpsw0_port4: port@4 { 473 reg = <4>; 474 ti,mac-only; 475 label = "port4"; 476 status = "disabled"; 477 }; 478 479 cpsw0_port5: port@5 { 480 reg = <5>; 481 ti,mac-only; 482 label = "port5"; 483 status = "disabled"; 484 }; 485 486 cpsw0_port6: port@6 { 487 reg = <6>; 488 ti,mac-only; 489 label = "port6"; 490 status = "disabled"; 491 }; 492 493 cpsw0_port7: port@7 { 494 reg = <7>; 495 ti,mac-only; 496 label = "port7"; 497 status = "disabled"; 498 }; 499 500 cpsw0_port8: port@8 { 501 reg = <8>; 502 ti,mac-only; 503 label = "port8"; 504 status = "disabled"; 505 }; 506 }; 507 508 cpsw9g_mdio: mdio@f00 { 509 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 510 reg = <0x0 0xf00 0x0 0x100>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clocks = <&k3_clks 19 89>; 514 clock-names = "fck"; 515 bus_freq = <1000000>; 516 status = "disabled"; 517 }; 518 519 cpts@3d000 { 520 compatible = "ti,j721e-cpts"; 521 reg = <0x0 0x3d000 0x0 0x400>; 522 clocks = <&k3_clks 19 16>; 523 clock-names = "cpts"; 524 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "cpts"; 526 ti,cpts-ext-ts-inputs = <4>; 527 ti,cpts-periodic-outputs = <2>; 528 }; 529 }; 530 531 main_crypto: crypto@4e00000 { 532 compatible = "ti,j721e-sa2ul"; 533 reg = <0x0 0x4e00000 0x0 0x1200>; 534 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 535 #address-cells = <2>; 536 #size-cells = <2>; 537 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 538 539 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 540 <&main_udmap 0x4001>; 541 dma-names = "tx", "rx1", "rx2"; 542 543 rng: rng@4e10000 { 544 compatible = "inside-secure,safexcel-eip76"; 545 reg = <0x0 0x4e10000 0x0 0x7d>; 546 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 547 }; 548 }; 549 550 main_pmx0: pinctrl@11c000 { 551 compatible = "pinctrl-single"; 552 /* Proxy 0 addressing */ 553 reg = <0x0 0x11c000 0x0 0x2b4>; 554 #pinctrl-cells = <1>; 555 pinctrl-single,register-width = <32>; 556 pinctrl-single,function-mask = <0xffffffff>; 557 }; 558 559 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 560 main_timerio_input: pinctrl@104200 { 561 compatible = "pinctrl-single"; 562 reg = <0x00 0x104200 0x00 0x50>; 563 #pinctrl-cells = <1>; 564 pinctrl-single,register-width = <32>; 565 pinctrl-single,function-mask = <0x00000007>; 566 }; 567 568 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 569 main_timerio_output: pinctrl@104280 { 570 compatible = "pinctrl-single"; 571 reg = <0x00 0x104280 0x00 0x20>; 572 #pinctrl-cells = <1>; 573 pinctrl-single,register-width = <32>; 574 pinctrl-single,function-mask = <0x0000001f>; 575 }; 576 577 ti_csi2rx0: ticsi2rx@4500000 { 578 compatible = "ti,j721e-csi2rx-shim"; 579 reg = <0x0 0x4500000 0x0 0x1000>; 580 ranges; 581 #address-cells = <2>; 582 #size-cells = <2>; 583 dmas = <&main_udmap 0x4940>; 584 dma-names = "rx0"; 585 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 586 status = "disabled"; 587 588 cdns_csi2rx0: csi-bridge@4504000 { 589 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 590 reg = <0x0 0x4504000 0x0 0x1000>; 591 clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, 592 <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; 593 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 594 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 595 phys = <&dphy0>; 596 phy-names = "dphy"; 597 598 ports { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 602 csi0_port0: port@0 { 603 reg = <0>; 604 status = "disabled"; 605 }; 606 607 csi0_port1: port@1 { 608 reg = <1>; 609 status = "disabled"; 610 }; 611 612 csi0_port2: port@2 { 613 reg = <2>; 614 status = "disabled"; 615 }; 616 617 csi0_port3: port@3 { 618 reg = <3>; 619 status = "disabled"; 620 }; 621 622 csi0_port4: port@4 { 623 reg = <4>; 624 status = "disabled"; 625 }; 626 }; 627 }; 628 }; 629 630 ti_csi2rx1: ticsi2rx@4510000 { 631 compatible = "ti,j721e-csi2rx-shim"; 632 reg = <0x0 0x4510000 0x0 0x1000>; 633 ranges; 634 #address-cells = <2>; 635 #size-cells = <2>; 636 dmas = <&main_udmap 0x4960>; 637 dma-names = "rx0"; 638 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 639 status = "disabled"; 640 641 cdns_csi2rx1: csi-bridge@4514000 { 642 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 643 reg = <0x0 0x4514000 0x0 0x1000>; 644 clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, 645 <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; 646 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 647 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 648 phys = <&dphy1>; 649 phy-names = "dphy"; 650 651 ports { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 655 csi1_port0: port@0 { 656 reg = <0>; 657 status = "disabled"; 658 }; 659 660 csi1_port1: port@1 { 661 reg = <1>; 662 status = "disabled"; 663 }; 664 665 csi1_port2: port@2 { 666 reg = <2>; 667 status = "disabled"; 668 }; 669 670 csi1_port3: port@3 { 671 reg = <3>; 672 status = "disabled"; 673 }; 674 675 csi1_port4: port@4 { 676 reg = <4>; 677 status = "disabled"; 678 }; 679 }; 680 }; 681 }; 682 683 dphy0: phy@4580000 { 684 compatible = "cdns,dphy-rx"; 685 reg = <0x0 0x4580000 0x0 0x1100>; 686 #phy-cells = <0>; 687 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 688 status = "disabled"; 689 }; 690 691 dphy1: phy@4590000 { 692 compatible = "cdns,dphy-rx"; 693 reg = <0x0 0x4590000 0x0 0x1100>; 694 #phy-cells = <0>; 695 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 696 status = "disabled"; 697 }; 698 699 serdes_wiz0: wiz@5000000 { 700 compatible = "ti,j721e-wiz-16g"; 701 #address-cells = <1>; 702 #size-cells = <1>; 703 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 704 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 705 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 706 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 707 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 708 num-lanes = <2>; 709 #reset-cells = <1>; 710 ranges = <0x5000000 0x0 0x5000000 0x10000>; 711 712 wiz0_pll0_refclk: pll0-refclk { 713 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 714 #clock-cells = <0>; 715 assigned-clocks = <&wiz0_pll0_refclk>; 716 assigned-clock-parents = <&k3_clks 292 11>; 717 }; 718 719 wiz0_pll1_refclk: pll1-refclk { 720 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 721 #clock-cells = <0>; 722 assigned-clocks = <&wiz0_pll1_refclk>; 723 assigned-clock-parents = <&k3_clks 292 0>; 724 }; 725 726 wiz0_refclk_dig: refclk-dig { 727 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 728 #clock-cells = <0>; 729 assigned-clocks = <&wiz0_refclk_dig>; 730 assigned-clock-parents = <&k3_clks 292 11>; 731 }; 732 733 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 734 clocks = <&wiz0_refclk_dig>; 735 #clock-cells = <0>; 736 }; 737 738 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 739 clocks = <&wiz0_pll1_refclk>; 740 #clock-cells = <0>; 741 }; 742 743 serdes0: serdes@5000000 { 744 compatible = "ti,sierra-phy-t0"; 745 reg-names = "serdes"; 746 reg = <0x5000000 0x10000>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 #clock-cells = <1>; 750 resets = <&serdes_wiz0 0>; 751 reset-names = "sierra_reset"; 752 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 753 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 754 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 755 "pll0_refclk", "pll1_refclk"; 756 }; 757 }; 758 759 serdes_wiz1: wiz@5010000 { 760 compatible = "ti,j721e-wiz-16g"; 761 #address-cells = <1>; 762 #size-cells = <1>; 763 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 764 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 765 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 766 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 767 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 768 num-lanes = <2>; 769 #reset-cells = <1>; 770 ranges = <0x5010000 0x0 0x5010000 0x10000>; 771 772 wiz1_pll0_refclk: pll0-refclk { 773 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 774 #clock-cells = <0>; 775 assigned-clocks = <&wiz1_pll0_refclk>; 776 assigned-clock-parents = <&k3_clks 293 13>; 777 }; 778 779 wiz1_pll1_refclk: pll1-refclk { 780 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 781 #clock-cells = <0>; 782 assigned-clocks = <&wiz1_pll1_refclk>; 783 assigned-clock-parents = <&k3_clks 293 0>; 784 }; 785 786 wiz1_refclk_dig: refclk-dig { 787 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 788 #clock-cells = <0>; 789 assigned-clocks = <&wiz1_refclk_dig>; 790 assigned-clock-parents = <&k3_clks 293 13>; 791 }; 792 793 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { 794 clocks = <&wiz1_refclk_dig>; 795 #clock-cells = <0>; 796 }; 797 798 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 799 clocks = <&wiz1_pll1_refclk>; 800 #clock-cells = <0>; 801 }; 802 803 serdes1: serdes@5010000 { 804 compatible = "ti,sierra-phy-t0"; 805 reg-names = "serdes"; 806 reg = <0x5010000 0x10000>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 #clock-cells = <1>; 810 resets = <&serdes_wiz1 0>; 811 reset-names = "sierra_reset"; 812 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 813 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 814 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 815 "pll0_refclk", "pll1_refclk"; 816 }; 817 }; 818 819 serdes_wiz2: wiz@5020000 { 820 compatible = "ti,j721e-wiz-16g"; 821 #address-cells = <1>; 822 #size-cells = <1>; 823 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 824 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 825 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 826 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 827 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 828 num-lanes = <2>; 829 #reset-cells = <1>; 830 ranges = <0x5020000 0x0 0x5020000 0x10000>; 831 832 wiz2_pll0_refclk: pll0-refclk { 833 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 834 #clock-cells = <0>; 835 assigned-clocks = <&wiz2_pll0_refclk>; 836 assigned-clock-parents = <&k3_clks 294 11>; 837 }; 838 839 wiz2_pll1_refclk: pll1-refclk { 840 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 841 #clock-cells = <0>; 842 assigned-clocks = <&wiz2_pll1_refclk>; 843 assigned-clock-parents = <&k3_clks 294 0>; 844 }; 845 846 wiz2_refclk_dig: refclk-dig { 847 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 848 #clock-cells = <0>; 849 assigned-clocks = <&wiz2_refclk_dig>; 850 assigned-clock-parents = <&k3_clks 294 11>; 851 }; 852 853 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 854 clocks = <&wiz2_refclk_dig>; 855 #clock-cells = <0>; 856 }; 857 858 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 859 clocks = <&wiz2_pll1_refclk>; 860 #clock-cells = <0>; 861 }; 862 863 serdes2: serdes@5020000 { 864 compatible = "ti,sierra-phy-t0"; 865 reg-names = "serdes"; 866 reg = <0x5020000 0x10000>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 #clock-cells = <1>; 870 resets = <&serdes_wiz2 0>; 871 reset-names = "sierra_reset"; 872 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 873 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 874 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 875 "pll0_refclk", "pll1_refclk"; 876 }; 877 }; 878 879 serdes_wiz3: wiz@5030000 { 880 compatible = "ti,j721e-wiz-16g"; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 884 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 885 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 886 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 887 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 888 num-lanes = <2>; 889 #reset-cells = <1>; 890 ranges = <0x5030000 0x0 0x5030000 0x10000>; 891 892 wiz3_pll0_refclk: pll0-refclk { 893 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 894 #clock-cells = <0>; 895 assigned-clocks = <&wiz3_pll0_refclk>; 896 assigned-clock-parents = <&k3_clks 295 9>; 897 }; 898 899 wiz3_pll1_refclk: pll1-refclk { 900 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 901 #clock-cells = <0>; 902 assigned-clocks = <&wiz3_pll1_refclk>; 903 assigned-clock-parents = <&k3_clks 295 0>; 904 }; 905 906 wiz3_refclk_dig: refclk-dig { 907 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 908 #clock-cells = <0>; 909 assigned-clocks = <&wiz3_refclk_dig>; 910 assigned-clock-parents = <&k3_clks 295 9>; 911 }; 912 913 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 914 clocks = <&wiz3_refclk_dig>; 915 #clock-cells = <0>; 916 }; 917 918 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 919 clocks = <&wiz3_pll1_refclk>; 920 #clock-cells = <0>; 921 }; 922 923 serdes3: serdes@5030000 { 924 compatible = "ti,sierra-phy-t0"; 925 reg-names = "serdes"; 926 reg = <0x5030000 0x10000>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 #clock-cells = <1>; 930 resets = <&serdes_wiz3 0>; 931 reset-names = "sierra_reset"; 932 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 933 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 934 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 935 "pll0_refclk", "pll1_refclk"; 936 }; 937 }; 938 939 pcie0_rc: pcie@2900000 { 940 compatible = "ti,j721e-pcie-host"; 941 reg = <0x00 0x02900000 0x00 0x1000>, 942 <0x00 0x02907000 0x00 0x400>, 943 <0x00 0x0d000000 0x00 0x00800000>, 944 <0x00 0x10000000 0x00 0x00001000>; 945 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 946 interrupt-names = "link_state"; 947 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 948 device_type = "pci"; 949 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 950 max-link-speed = <3>; 951 num-lanes = <2>; 952 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 953 clocks = <&k3_clks 239 1>; 954 clock-names = "fck"; 955 #address-cells = <3>; 956 #size-cells = <2>; 957 bus-range = <0x0 0xff>; 958 vendor-id = <0x104c>; 959 device-id = <0xb00d>; 960 msi-map = <0x0 &gic_its 0x0 0x10000>; 961 dma-coherent; 962 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 963 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 964 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 965 status = "disabled"; 966 }; 967 968 pcie1_rc: pcie@2910000 { 969 compatible = "ti,j721e-pcie-host"; 970 reg = <0x00 0x02910000 0x00 0x1000>, 971 <0x00 0x02917000 0x00 0x400>, 972 <0x00 0x0d800000 0x00 0x00800000>, 973 <0x00 0x18000000 0x00 0x00001000>; 974 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 975 interrupt-names = "link_state"; 976 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 977 device_type = "pci"; 978 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 979 max-link-speed = <3>; 980 num-lanes = <2>; 981 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 982 clocks = <&k3_clks 240 1>; 983 clock-names = "fck"; 984 #address-cells = <3>; 985 #size-cells = <2>; 986 bus-range = <0x0 0xff>; 987 vendor-id = <0x104c>; 988 device-id = <0xb00d>; 989 msi-map = <0x0 &gic_its 0x10000 0x10000>; 990 dma-coherent; 991 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 992 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 993 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 994 status = "disabled"; 995 }; 996 997 pcie2_rc: pcie@2920000 { 998 compatible = "ti,j721e-pcie-host"; 999 reg = <0x00 0x02920000 0x00 0x1000>, 1000 <0x00 0x02927000 0x00 0x400>, 1001 <0x00 0x0e000000 0x00 0x00800000>, 1002 <0x44 0x00000000 0x00 0x00001000>; 1003 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1004 interrupt-names = "link_state"; 1005 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 1006 device_type = "pci"; 1007 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 1008 max-link-speed = <3>; 1009 num-lanes = <2>; 1010 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 1011 clocks = <&k3_clks 241 1>; 1012 clock-names = "fck"; 1013 #address-cells = <3>; 1014 #size-cells = <2>; 1015 bus-range = <0x0 0xff>; 1016 vendor-id = <0x104c>; 1017 device-id = <0xb00d>; 1018 msi-map = <0x0 &gic_its 0x20000 0x10000>; 1019 dma-coherent; 1020 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 1021 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 1022 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1023 status = "disabled"; 1024 }; 1025 1026 pcie3_rc: pcie@2930000 { 1027 compatible = "ti,j721e-pcie-host"; 1028 reg = <0x00 0x02930000 0x00 0x1000>, 1029 <0x00 0x02937000 0x00 0x400>, 1030 <0x00 0x0e800000 0x00 0x00800000>, 1031 <0x44 0x10000000 0x00 0x00001000>; 1032 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1033 interrupt-names = "link_state"; 1034 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 1035 device_type = "pci"; 1036 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 1037 max-link-speed = <3>; 1038 num-lanes = <2>; 1039 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 1040 clocks = <&k3_clks 242 1>; 1041 clock-names = "fck"; 1042 #address-cells = <3>; 1043 #size-cells = <2>; 1044 bus-range = <0x0 0xff>; 1045 vendor-id = <0x104c>; 1046 device-id = <0xb00d>; 1047 msi-map = <0x0 &gic_its 0x30000 0x10000>; 1048 dma-coherent; 1049 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 1050 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 1051 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1052 status = "disabled"; 1053 }; 1054 1055 serdes_wiz4: wiz@5050000 { 1056 compatible = "ti,am64-wiz-10g"; 1057 #address-cells = <1>; 1058 #size-cells = <1>; 1059 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 1060 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 1061 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1062 assigned-clocks = <&k3_clks 297 9>; 1063 assigned-clock-parents = <&k3_clks 297 10>; 1064 assigned-clock-rates = <19200000>; 1065 num-lanes = <4>; 1066 #reset-cells = <1>; 1067 #clock-cells = <1>; 1068 ranges = <0x05050000 0x00 0x05050000 0x010000>, 1069 <0x0a030a00 0x00 0x0a030a00 0x40>; 1070 1071 serdes4: serdes@5050000 { 1072 /* 1073 * Note: we also map DPTX PHY registers as the Torrent 1074 * needs to manage those. 1075 */ 1076 compatible = "ti,j721e-serdes-10g"; 1077 reg = <0x05050000 0x010000>, 1078 <0x0a030a00 0x40>; /* DPTX PHY */ 1079 reg-names = "torrent_phy", "dptx_phy"; 1080 1081 resets = <&serdes_wiz4 0>; 1082 reset-names = "torrent_reset"; 1083 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 1084 clock-names = "refclk"; 1085 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1086 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1087 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1088 assigned-clock-parents = <&k3_clks 297 9>, 1089 <&k3_clks 297 9>, 1090 <&k3_clks 297 9>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 }; 1094 }; 1095 1096 main_timer0: timer@2400000 { 1097 compatible = "ti,am654-timer"; 1098 reg = <0x00 0x2400000 0x00 0x400>; 1099 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&k3_clks 49 1>; 1101 clock-names = "fck"; 1102 assigned-clocks = <&k3_clks 49 1>; 1103 assigned-clock-parents = <&k3_clks 49 2>; 1104 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1105 ti,timer-pwm; 1106 }; 1107 1108 main_timer1: timer@2410000 { 1109 compatible = "ti,am654-timer"; 1110 reg = <0x00 0x2410000 0x00 0x400>; 1111 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&k3_clks 50 1>; 1113 clock-names = "fck"; 1114 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; 1115 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; 1116 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1117 ti,timer-pwm; 1118 }; 1119 1120 main_timer2: timer@2420000 { 1121 compatible = "ti,am654-timer"; 1122 reg = <0x00 0x2420000 0x00 0x400>; 1123 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&k3_clks 51 1>; 1125 clock-names = "fck"; 1126 assigned-clocks = <&k3_clks 51 1>; 1127 assigned-clock-parents = <&k3_clks 51 2>; 1128 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1129 ti,timer-pwm; 1130 }; 1131 1132 main_timer3: timer@2430000 { 1133 compatible = "ti,am654-timer"; 1134 reg = <0x00 0x2430000 0x00 0x400>; 1135 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&k3_clks 52 1>; 1137 clock-names = "fck"; 1138 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; 1139 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; 1140 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1141 ti,timer-pwm; 1142 }; 1143 1144 main_timer4: timer@2440000 { 1145 compatible = "ti,am654-timer"; 1146 reg = <0x00 0x2440000 0x00 0x400>; 1147 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&k3_clks 53 1>; 1149 clock-names = "fck"; 1150 assigned-clocks = <&k3_clks 53 1>; 1151 assigned-clock-parents = <&k3_clks 53 2>; 1152 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1153 ti,timer-pwm; 1154 }; 1155 1156 main_timer5: timer@2450000 { 1157 compatible = "ti,am654-timer"; 1158 reg = <0x00 0x2450000 0x00 0x400>; 1159 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&k3_clks 54 1>; 1161 clock-names = "fck"; 1162 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; 1163 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; 1164 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1165 ti,timer-pwm; 1166 }; 1167 1168 main_timer6: timer@2460000 { 1169 compatible = "ti,am654-timer"; 1170 reg = <0x00 0x2460000 0x00 0x400>; 1171 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&k3_clks 55 1>; 1173 clock-names = "fck"; 1174 assigned-clocks = <&k3_clks 55 1>; 1175 assigned-clock-parents = <&k3_clks 55 2>; 1176 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1177 ti,timer-pwm; 1178 }; 1179 1180 main_timer7: timer@2470000 { 1181 compatible = "ti,am654-timer"; 1182 reg = <0x00 0x2470000 0x00 0x400>; 1183 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&k3_clks 57 1>; 1185 clock-names = "fck"; 1186 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; 1187 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; 1188 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1189 ti,timer-pwm; 1190 }; 1191 1192 main_timer8: timer@2480000 { 1193 compatible = "ti,am654-timer"; 1194 reg = <0x00 0x2480000 0x00 0x400>; 1195 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&k3_clks 58 1>; 1197 clock-names = "fck"; 1198 assigned-clocks = <&k3_clks 58 1>; 1199 assigned-clock-parents = <&k3_clks 58 2>; 1200 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1201 ti,timer-pwm; 1202 }; 1203 1204 main_timer9: timer@2490000 { 1205 compatible = "ti,am654-timer"; 1206 reg = <0x00 0x2490000 0x00 0x400>; 1207 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&k3_clks 59 1>; 1209 clock-names = "fck"; 1210 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; 1211 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; 1212 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1213 ti,timer-pwm; 1214 }; 1215 1216 main_timer10: timer@24a0000 { 1217 compatible = "ti,am654-timer"; 1218 reg = <0x00 0x24a0000 0x00 0x400>; 1219 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&k3_clks 60 1>; 1221 clock-names = "fck"; 1222 assigned-clocks = <&k3_clks 60 1>; 1223 assigned-clock-parents = <&k3_clks 60 2>; 1224 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1225 ti,timer-pwm; 1226 }; 1227 1228 main_timer11: timer@24b0000 { 1229 compatible = "ti,am654-timer"; 1230 reg = <0x00 0x24b0000 0x00 0x400>; 1231 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&k3_clks 62 1>; 1233 clock-names = "fck"; 1234 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; 1235 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; 1236 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1237 ti,timer-pwm; 1238 }; 1239 1240 main_timer12: timer@24c0000 { 1241 compatible = "ti,am654-timer"; 1242 reg = <0x00 0x24c0000 0x00 0x400>; 1243 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&k3_clks 63 1>; 1245 clock-names = "fck"; 1246 assigned-clocks = <&k3_clks 63 1>; 1247 assigned-clock-parents = <&k3_clks 63 2>; 1248 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1249 ti,timer-pwm; 1250 }; 1251 1252 main_timer13: timer@24d0000 { 1253 compatible = "ti,am654-timer"; 1254 reg = <0x00 0x24d0000 0x00 0x400>; 1255 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&k3_clks 64 1>; 1257 clock-names = "fck"; 1258 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; 1259 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; 1260 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1261 ti,timer-pwm; 1262 }; 1263 1264 main_timer14: timer@24e0000 { 1265 compatible = "ti,am654-timer"; 1266 reg = <0x00 0x24e0000 0x00 0x400>; 1267 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&k3_clks 65 1>; 1269 clock-names = "fck"; 1270 assigned-clocks = <&k3_clks 65 1>; 1271 assigned-clock-parents = <&k3_clks 65 2>; 1272 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1273 ti,timer-pwm; 1274 }; 1275 1276 main_timer15: timer@24f0000 { 1277 compatible = "ti,am654-timer"; 1278 reg = <0x00 0x24f0000 0x00 0x400>; 1279 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1280 clocks = <&k3_clks 66 1>; 1281 clock-names = "fck"; 1282 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; 1283 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; 1284 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1285 ti,timer-pwm; 1286 }; 1287 1288 main_timer16: timer@2500000 { 1289 compatible = "ti,am654-timer"; 1290 reg = <0x00 0x2500000 0x00 0x400>; 1291 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&k3_clks 67 1>; 1293 clock-names = "fck"; 1294 assigned-clocks = <&k3_clks 67 1>; 1295 assigned-clock-parents = <&k3_clks 67 2>; 1296 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1297 ti,timer-pwm; 1298 }; 1299 1300 main_timer17: timer@2510000 { 1301 compatible = "ti,am654-timer"; 1302 reg = <0x00 0x2510000 0x00 0x400>; 1303 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&k3_clks 68 1>; 1305 clock-names = "fck"; 1306 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; 1307 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; 1308 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1309 ti,timer-pwm; 1310 }; 1311 1312 main_timer18: timer@2520000 { 1313 compatible = "ti,am654-timer"; 1314 reg = <0x00 0x2520000 0x00 0x400>; 1315 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&k3_clks 69 1>; 1317 clock-names = "fck"; 1318 assigned-clocks = <&k3_clks 69 1>; 1319 assigned-clock-parents = <&k3_clks 69 2>; 1320 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1321 ti,timer-pwm; 1322 }; 1323 1324 main_timer19: timer@2530000 { 1325 compatible = "ti,am654-timer"; 1326 reg = <0x00 0x2530000 0x00 0x400>; 1327 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1328 clocks = <&k3_clks 70 1>; 1329 clock-names = "fck"; 1330 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; 1331 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; 1332 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1333 ti,timer-pwm; 1334 }; 1335 1336 main_uart0: serial@2800000 { 1337 compatible = "ti,j721e-uart", "ti,am654-uart"; 1338 reg = <0x00 0x02800000 0x00 0x100>; 1339 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1340 clock-frequency = <48000000>; 1341 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 1342 clocks = <&k3_clks 146 0>; 1343 clock-names = "fclk"; 1344 status = "disabled"; 1345 }; 1346 1347 main_uart1: serial@2810000 { 1348 compatible = "ti,j721e-uart", "ti,am654-uart"; 1349 reg = <0x00 0x02810000 0x00 0x100>; 1350 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1351 clock-frequency = <48000000>; 1352 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1353 clocks = <&k3_clks 278 0>; 1354 clock-names = "fclk"; 1355 status = "disabled"; 1356 }; 1357 1358 main_uart2: serial@2820000 { 1359 compatible = "ti,j721e-uart", "ti,am654-uart"; 1360 reg = <0x00 0x02820000 0x00 0x100>; 1361 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1362 clock-frequency = <48000000>; 1363 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 1364 clocks = <&k3_clks 279 0>; 1365 clock-names = "fclk"; 1366 status = "disabled"; 1367 }; 1368 1369 main_uart3: serial@2830000 { 1370 compatible = "ti,j721e-uart", "ti,am654-uart"; 1371 reg = <0x00 0x02830000 0x00 0x100>; 1372 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1373 clock-frequency = <48000000>; 1374 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 1375 clocks = <&k3_clks 280 0>; 1376 clock-names = "fclk"; 1377 status = "disabled"; 1378 }; 1379 1380 main_uart4: serial@2840000 { 1381 compatible = "ti,j721e-uart", "ti,am654-uart"; 1382 reg = <0x00 0x02840000 0x00 0x100>; 1383 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1384 clock-frequency = <48000000>; 1385 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 1386 clocks = <&k3_clks 281 0>; 1387 clock-names = "fclk"; 1388 status = "disabled"; 1389 }; 1390 1391 main_uart5: serial@2850000 { 1392 compatible = "ti,j721e-uart", "ti,am654-uart"; 1393 reg = <0x00 0x02850000 0x00 0x100>; 1394 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1395 clock-frequency = <48000000>; 1396 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 1397 clocks = <&k3_clks 282 0>; 1398 clock-names = "fclk"; 1399 status = "disabled"; 1400 }; 1401 1402 main_uart6: serial@2860000 { 1403 compatible = "ti,j721e-uart", "ti,am654-uart"; 1404 reg = <0x00 0x02860000 0x00 0x100>; 1405 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1406 clock-frequency = <48000000>; 1407 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 1408 clocks = <&k3_clks 283 0>; 1409 clock-names = "fclk"; 1410 status = "disabled"; 1411 }; 1412 1413 main_uart7: serial@2870000 { 1414 compatible = "ti,j721e-uart", "ti,am654-uart"; 1415 reg = <0x00 0x02870000 0x00 0x100>; 1416 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1417 clock-frequency = <48000000>; 1418 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1419 clocks = <&k3_clks 284 0>; 1420 clock-names = "fclk"; 1421 status = "disabled"; 1422 }; 1423 1424 main_uart8: serial@2880000 { 1425 compatible = "ti,j721e-uart", "ti,am654-uart"; 1426 reg = <0x00 0x02880000 0x00 0x100>; 1427 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1428 clock-frequency = <48000000>; 1429 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1430 clocks = <&k3_clks 285 0>; 1431 clock-names = "fclk"; 1432 status = "disabled"; 1433 }; 1434 1435 main_uart9: serial@2890000 { 1436 compatible = "ti,j721e-uart", "ti,am654-uart"; 1437 reg = <0x00 0x02890000 0x00 0x100>; 1438 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1439 clock-frequency = <48000000>; 1440 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1441 clocks = <&k3_clks 286 0>; 1442 clock-names = "fclk"; 1443 status = "disabled"; 1444 }; 1445 1446 main_gpio0: gpio@600000 { 1447 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1448 reg = <0x0 0x00600000 0x0 0x100>; 1449 gpio-controller; 1450 #gpio-cells = <2>; 1451 interrupt-parent = <&main_gpio_intr>; 1452 interrupts = <256>, <257>, <258>, <259>, 1453 <260>, <261>, <262>, <263>; 1454 interrupt-controller; 1455 #interrupt-cells = <2>; 1456 ti,ngpio = <128>; 1457 ti,davinci-gpio-unbanked = <0>; 1458 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1459 clocks = <&k3_clks 105 0>; 1460 clock-names = "gpio"; 1461 status = "disabled"; 1462 }; 1463 1464 main_gpio1: gpio@601000 { 1465 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1466 reg = <0x0 0x00601000 0x0 0x100>; 1467 gpio-controller; 1468 #gpio-cells = <2>; 1469 interrupt-parent = <&main_gpio_intr>; 1470 interrupts = <288>, <289>, <290>; 1471 interrupt-controller; 1472 #interrupt-cells = <2>; 1473 ti,ngpio = <36>; 1474 ti,davinci-gpio-unbanked = <0>; 1475 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1476 clocks = <&k3_clks 106 0>; 1477 clock-names = "gpio"; 1478 status = "disabled"; 1479 }; 1480 1481 main_gpio2: gpio@610000 { 1482 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1483 reg = <0x0 0x00610000 0x0 0x100>; 1484 gpio-controller; 1485 #gpio-cells = <2>; 1486 interrupt-parent = <&main_gpio_intr>; 1487 interrupts = <264>, <265>, <266>, <267>, 1488 <268>, <269>, <270>, <271>; 1489 interrupt-controller; 1490 #interrupt-cells = <2>; 1491 ti,ngpio = <128>; 1492 ti,davinci-gpio-unbanked = <0>; 1493 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1494 clocks = <&k3_clks 107 0>; 1495 clock-names = "gpio"; 1496 status = "disabled"; 1497 }; 1498 1499 main_gpio3: gpio@611000 { 1500 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1501 reg = <0x0 0x00611000 0x0 0x100>; 1502 gpio-controller; 1503 #gpio-cells = <2>; 1504 interrupt-parent = <&main_gpio_intr>; 1505 interrupts = <292>, <293>, <294>; 1506 interrupt-controller; 1507 #interrupt-cells = <2>; 1508 ti,ngpio = <36>; 1509 ti,davinci-gpio-unbanked = <0>; 1510 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1511 clocks = <&k3_clks 108 0>; 1512 clock-names = "gpio"; 1513 status = "disabled"; 1514 }; 1515 1516 main_gpio4: gpio@620000 { 1517 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1518 reg = <0x0 0x00620000 0x0 0x100>; 1519 gpio-controller; 1520 #gpio-cells = <2>; 1521 interrupt-parent = <&main_gpio_intr>; 1522 interrupts = <272>, <273>, <274>, <275>, 1523 <276>, <277>, <278>, <279>; 1524 interrupt-controller; 1525 #interrupt-cells = <2>; 1526 ti,ngpio = <128>; 1527 ti,davinci-gpio-unbanked = <0>; 1528 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1529 clocks = <&k3_clks 109 0>; 1530 clock-names = "gpio"; 1531 status = "disabled"; 1532 }; 1533 1534 main_gpio5: gpio@621000 { 1535 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1536 reg = <0x0 0x00621000 0x0 0x100>; 1537 gpio-controller; 1538 #gpio-cells = <2>; 1539 interrupt-parent = <&main_gpio_intr>; 1540 interrupts = <296>, <297>, <298>; 1541 interrupt-controller; 1542 #interrupt-cells = <2>; 1543 ti,ngpio = <36>; 1544 ti,davinci-gpio-unbanked = <0>; 1545 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1546 clocks = <&k3_clks 110 0>; 1547 clock-names = "gpio"; 1548 status = "disabled"; 1549 }; 1550 1551 main_gpio6: gpio@630000 { 1552 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1553 reg = <0x0 0x00630000 0x0 0x100>; 1554 gpio-controller; 1555 #gpio-cells = <2>; 1556 interrupt-parent = <&main_gpio_intr>; 1557 interrupts = <280>, <281>, <282>, <283>, 1558 <284>, <285>, <286>, <287>; 1559 interrupt-controller; 1560 #interrupt-cells = <2>; 1561 ti,ngpio = <128>; 1562 ti,davinci-gpio-unbanked = <0>; 1563 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1564 clocks = <&k3_clks 111 0>; 1565 clock-names = "gpio"; 1566 status = "disabled"; 1567 }; 1568 1569 main_gpio7: gpio@631000 { 1570 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1571 reg = <0x0 0x00631000 0x0 0x100>; 1572 gpio-controller; 1573 #gpio-cells = <2>; 1574 interrupt-parent = <&main_gpio_intr>; 1575 interrupts = <300>, <301>, <302>; 1576 interrupt-controller; 1577 #interrupt-cells = <2>; 1578 ti,ngpio = <36>; 1579 ti,davinci-gpio-unbanked = <0>; 1580 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1581 clocks = <&k3_clks 112 0>; 1582 clock-names = "gpio"; 1583 status = "disabled"; 1584 }; 1585 1586 main_sdhci0: mmc@4f80000 { 1587 compatible = "ti,j721e-sdhci-8bit"; 1588 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1589 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1590 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1591 clock-names = "clk_ahb", "clk_xin"; 1592 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1593 assigned-clocks = <&k3_clks 91 1>; 1594 assigned-clock-parents = <&k3_clks 91 2>; 1595 bus-width = <8>; 1596 mmc-hs200-1_8v; 1597 mmc-ddr-1_8v; 1598 ti,otap-del-sel-legacy = <0x0>; 1599 ti,otap-del-sel-mmc-hs = <0x0>; 1600 ti,otap-del-sel-ddr52 = <0x5>; 1601 ti,otap-del-sel-hs200 = <0x6>; 1602 ti,otap-del-sel-hs400 = <0x0>; 1603 ti,itap-del-sel-legacy = <0x10>; 1604 ti,itap-del-sel-mmc-hs = <0xa>; 1605 ti,itap-del-sel-ddr52 = <0x3>; 1606 ti,trm-icp = <0x8>; 1607 dma-coherent; 1608 status = "disabled"; 1609 }; 1610 1611 main_sdhci1: mmc@4fb0000 { 1612 compatible = "ti,j721e-sdhci-4bit"; 1613 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1614 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1615 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1616 clock-names = "clk_ahb", "clk_xin"; 1617 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1618 assigned-clocks = <&k3_clks 92 0>; 1619 assigned-clock-parents = <&k3_clks 92 1>; 1620 ti,otap-del-sel-legacy = <0x0>; 1621 ti,otap-del-sel-sd-hs = <0x0>; 1622 ti,otap-del-sel-sdr12 = <0xf>; 1623 ti,otap-del-sel-sdr25 = <0xf>; 1624 ti,otap-del-sel-sdr50 = <0xc>; 1625 ti,otap-del-sel-ddr50 = <0xc>; 1626 ti,otap-del-sel-sdr104 = <0x5>; 1627 ti,itap-del-sel-legacy = <0x0>; 1628 ti,itap-del-sel-sd-hs = <0x0>; 1629 ti,itap-del-sel-sdr12 = <0x0>; 1630 ti,itap-del-sel-sdr25 = <0x0>; 1631 ti,itap-del-sel-ddr50 = <0x2>; 1632 ti,trm-icp = <0x8>; 1633 ti,clkbuf-sel = <0x7>; 1634 dma-coherent; 1635 sdhci-caps-mask = <0x2 0x0>; 1636 status = "disabled"; 1637 }; 1638 1639 main_sdhci2: mmc@4f98000 { 1640 compatible = "ti,j721e-sdhci-4bit"; 1641 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1642 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1643 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1644 clock-names = "clk_ahb", "clk_xin"; 1645 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1646 assigned-clocks = <&k3_clks 93 0>; 1647 assigned-clock-parents = <&k3_clks 93 1>; 1648 ti,otap-del-sel-legacy = <0x0>; 1649 ti,otap-del-sel-sd-hs = <0x0>; 1650 ti,otap-del-sel-sdr12 = <0xf>; 1651 ti,otap-del-sel-sdr25 = <0xf>; 1652 ti,otap-del-sel-sdr50 = <0xc>; 1653 ti,otap-del-sel-ddr50 = <0xc>; 1654 ti,otap-del-sel-sdr104 = <0x5>; 1655 ti,itap-del-sel-legacy = <0x0>; 1656 ti,itap-del-sel-sd-hs = <0x0>; 1657 ti,itap-del-sel-sdr12 = <0x0>; 1658 ti,itap-del-sel-sdr25 = <0x0>; 1659 ti,itap-del-sel-ddr50 = <0x2>; 1660 ti,trm-icp = <0x8>; 1661 ti,clkbuf-sel = <0x7>; 1662 dma-coherent; 1663 sdhci-caps-mask = <0x2 0x0>; 1664 status = "disabled"; 1665 }; 1666 1667 usbss0: cdns-usb@4104000 { 1668 compatible = "ti,j721e-usb"; 1669 reg = <0x00 0x4104000 0x00 0x100>; 1670 dma-coherent; 1671 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1672 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1673 clock-names = "ref", "lpm"; 1674 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1675 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1676 #address-cells = <2>; 1677 #size-cells = <2>; 1678 ranges; 1679 1680 usb0: usb@6000000 { 1681 compatible = "cdns,usb3"; 1682 reg = <0x00 0x6000000 0x00 0x10000>, 1683 <0x00 0x6010000 0x00 0x10000>, 1684 <0x00 0x6020000 0x00 0x10000>; 1685 reg-names = "otg", "xhci", "dev"; 1686 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1687 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1688 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1689 interrupt-names = "host", 1690 "peripheral", 1691 "otg"; 1692 maximum-speed = "super-speed"; 1693 dr_mode = "otg"; 1694 }; 1695 }; 1696 1697 usbss1: cdns-usb@4114000 { 1698 compatible = "ti,j721e-usb"; 1699 reg = <0x00 0x4114000 0x00 0x100>; 1700 dma-coherent; 1701 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1702 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1703 clock-names = "ref", "lpm"; 1704 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1705 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1706 #address-cells = <2>; 1707 #size-cells = <2>; 1708 ranges; 1709 1710 usb1: usb@6400000 { 1711 compatible = "cdns,usb3"; 1712 reg = <0x00 0x6400000 0x00 0x10000>, 1713 <0x00 0x6410000 0x00 0x10000>, 1714 <0x00 0x6420000 0x00 0x10000>; 1715 reg-names = "otg", "xhci", "dev"; 1716 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1717 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1718 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1719 interrupt-names = "host", 1720 "peripheral", 1721 "otg"; 1722 maximum-speed = "super-speed"; 1723 dr_mode = "otg"; 1724 }; 1725 }; 1726 1727 main_i2c0: i2c@2000000 { 1728 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1729 reg = <0x0 0x2000000 0x0 0x100>; 1730 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 clock-names = "fck"; 1734 clocks = <&k3_clks 187 0>; 1735 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1736 status = "disabled"; 1737 }; 1738 1739 main_i2c1: i2c@2010000 { 1740 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1741 reg = <0x0 0x2010000 0x0 0x100>; 1742 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 clock-names = "fck"; 1746 clocks = <&k3_clks 188 0>; 1747 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1748 status = "disabled"; 1749 }; 1750 1751 main_i2c2: i2c@2020000 { 1752 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1753 reg = <0x0 0x2020000 0x0 0x100>; 1754 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 clock-names = "fck"; 1758 clocks = <&k3_clks 189 0>; 1759 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1760 status = "disabled"; 1761 }; 1762 1763 main_i2c3: i2c@2030000 { 1764 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1765 reg = <0x0 0x2030000 0x0 0x100>; 1766 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 clock-names = "fck"; 1770 clocks = <&k3_clks 190 0>; 1771 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1772 status = "disabled"; 1773 }; 1774 1775 main_i2c4: i2c@2040000 { 1776 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1777 reg = <0x0 0x2040000 0x0 0x100>; 1778 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 clock-names = "fck"; 1782 clocks = <&k3_clks 191 0>; 1783 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1784 status = "disabled"; 1785 }; 1786 1787 main_i2c5: i2c@2050000 { 1788 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1789 reg = <0x0 0x2050000 0x0 0x100>; 1790 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 clock-names = "fck"; 1794 clocks = <&k3_clks 192 0>; 1795 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1796 status = "disabled"; 1797 }; 1798 1799 main_i2c6: i2c@2060000 { 1800 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1801 reg = <0x0 0x2060000 0x0 0x100>; 1802 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 clock-names = "fck"; 1806 clocks = <&k3_clks 193 0>; 1807 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1808 status = "disabled"; 1809 }; 1810 1811 ufs_wrapper: ufs-wrapper@4e80000 { 1812 compatible = "ti,j721e-ufs"; 1813 reg = <0x0 0x4e80000 0x0 0x100>; 1814 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1815 clocks = <&k3_clks 277 1>; 1816 assigned-clocks = <&k3_clks 277 1>; 1817 assigned-clock-parents = <&k3_clks 277 4>; 1818 ranges; 1819 #address-cells = <2>; 1820 #size-cells = <2>; 1821 1822 ufs@4e84000 { 1823 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1824 reg = <0x0 0x4e84000 0x0 0x10000>; 1825 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1826 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1827 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1828 clock-names = "core_clk", "phy_clk", "ref_clk"; 1829 dma-coherent; 1830 }; 1831 }; 1832 1833 mhdp: dp-bridge@a000000 { 1834 compatible = "ti,j721e-mhdp8546"; 1835 /* 1836 * Note: we do not map DPTX PHY area, as that is handled by 1837 * the PHY driver. 1838 */ 1839 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1840 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1841 reg-names = "mhdptx", "j721e-intg"; 1842 1843 clocks = <&k3_clks 151 36>; 1844 1845 interrupt-parent = <&gic500>; 1846 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1847 1848 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1849 1850 dp0_ports: ports { 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 1854 port@0 { 1855 reg = <0>; 1856 }; 1857 1858 port@4 { 1859 reg = <4>; 1860 }; 1861 }; 1862 }; 1863 1864 dss: dss@4a00000 { 1865 compatible = "ti,j721e-dss"; 1866 reg = 1867 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1868 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1869 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1870 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1871 1872 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1873 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1874 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1875 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1876 1877 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1878 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1879 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1880 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1881 1882 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1883 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1884 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1885 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1886 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1887 1888 reg-names = "common_m", "common_s0", 1889 "common_s1", "common_s2", 1890 "vidl1", "vidl2","vid1","vid2", 1891 "ovr1", "ovr2", "ovr3", "ovr4", 1892 "vp1", "vp2", "vp3", "vp4", 1893 "wb"; 1894 1895 clocks = <&k3_clks 152 0>, 1896 <&k3_clks 152 1>, 1897 <&k3_clks 152 4>, 1898 <&k3_clks 152 9>, 1899 <&k3_clks 152 13>; 1900 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1901 1902 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1903 1904 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1908 interrupt-names = "common_m", 1909 "common_s0", 1910 "common_s1", 1911 "common_s2"; 1912 1913 dss_ports: ports { 1914 }; 1915 }; 1916 1917 mcasp0: mcasp@2b00000 { 1918 compatible = "ti,am33xx-mcasp-audio"; 1919 reg = <0x0 0x02b00000 0x0 0x2000>, 1920 <0x0 0x02b08000 0x0 0x1000>; 1921 reg-names = "mpu","dat"; 1922 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1924 interrupt-names = "tx", "rx"; 1925 1926 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1927 dma-names = "tx", "rx"; 1928 1929 clocks = <&k3_clks 174 1>; 1930 clock-names = "fck"; 1931 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1932 status = "disabled"; 1933 }; 1934 1935 mcasp1: mcasp@2b10000 { 1936 compatible = "ti,am33xx-mcasp-audio"; 1937 reg = <0x0 0x02b10000 0x0 0x2000>, 1938 <0x0 0x02b18000 0x0 0x1000>; 1939 reg-names = "mpu","dat"; 1940 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1942 interrupt-names = "tx", "rx"; 1943 1944 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1945 dma-names = "tx", "rx"; 1946 1947 clocks = <&k3_clks 175 1>; 1948 clock-names = "fck"; 1949 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1950 status = "disabled"; 1951 }; 1952 1953 mcasp2: mcasp@2b20000 { 1954 compatible = "ti,am33xx-mcasp-audio"; 1955 reg = <0x0 0x02b20000 0x0 0x2000>, 1956 <0x0 0x02b28000 0x0 0x1000>; 1957 reg-names = "mpu","dat"; 1958 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1960 interrupt-names = "tx", "rx"; 1961 1962 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1963 dma-names = "tx", "rx"; 1964 1965 clocks = <&k3_clks 176 1>; 1966 clock-names = "fck"; 1967 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1968 status = "disabled"; 1969 }; 1970 1971 mcasp3: mcasp@2b30000 { 1972 compatible = "ti,am33xx-mcasp-audio"; 1973 reg = <0x0 0x02b30000 0x0 0x2000>, 1974 <0x0 0x02b38000 0x0 0x1000>; 1975 reg-names = "mpu","dat"; 1976 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1978 interrupt-names = "tx", "rx"; 1979 1980 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1981 dma-names = "tx", "rx"; 1982 1983 clocks = <&k3_clks 177 1>; 1984 clock-names = "fck"; 1985 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1986 status = "disabled"; 1987 }; 1988 1989 mcasp4: mcasp@2b40000 { 1990 compatible = "ti,am33xx-mcasp-audio"; 1991 reg = <0x0 0x02b40000 0x0 0x2000>, 1992 <0x0 0x02b48000 0x0 0x1000>; 1993 reg-names = "mpu","dat"; 1994 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1996 interrupt-names = "tx", "rx"; 1997 1998 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1999 dma-names = "tx", "rx"; 2000 2001 clocks = <&k3_clks 178 1>; 2002 clock-names = "fck"; 2003 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 2004 status = "disabled"; 2005 }; 2006 2007 mcasp5: mcasp@2b50000 { 2008 compatible = "ti,am33xx-mcasp-audio"; 2009 reg = <0x0 0x02b50000 0x0 0x2000>, 2010 <0x0 0x02b58000 0x0 0x1000>; 2011 reg-names = "mpu","dat"; 2012 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 2014 interrupt-names = "tx", "rx"; 2015 2016 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 2017 dma-names = "tx", "rx"; 2018 2019 clocks = <&k3_clks 179 1>; 2020 clock-names = "fck"; 2021 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 2022 status = "disabled"; 2023 }; 2024 2025 mcasp6: mcasp@2b60000 { 2026 compatible = "ti,am33xx-mcasp-audio"; 2027 reg = <0x0 0x02b60000 0x0 0x2000>, 2028 <0x0 0x02b68000 0x0 0x1000>; 2029 reg-names = "mpu","dat"; 2030 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 2032 interrupt-names = "tx", "rx"; 2033 2034 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 2035 dma-names = "tx", "rx"; 2036 2037 clocks = <&k3_clks 180 1>; 2038 clock-names = "fck"; 2039 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 2040 status = "disabled"; 2041 }; 2042 2043 mcasp7: mcasp@2b70000 { 2044 compatible = "ti,am33xx-mcasp-audio"; 2045 reg = <0x0 0x02b70000 0x0 0x2000>, 2046 <0x0 0x02b78000 0x0 0x1000>; 2047 reg-names = "mpu","dat"; 2048 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 2050 interrupt-names = "tx", "rx"; 2051 2052 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 2053 dma-names = "tx", "rx"; 2054 2055 clocks = <&k3_clks 181 1>; 2056 clock-names = "fck"; 2057 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 2058 status = "disabled"; 2059 }; 2060 2061 mcasp8: mcasp@2b80000 { 2062 compatible = "ti,am33xx-mcasp-audio"; 2063 reg = <0x0 0x02b80000 0x0 0x2000>, 2064 <0x0 0x02b88000 0x0 0x1000>; 2065 reg-names = "mpu","dat"; 2066 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 2068 interrupt-names = "tx", "rx"; 2069 2070 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 2071 dma-names = "tx", "rx"; 2072 2073 clocks = <&k3_clks 182 1>; 2074 clock-names = "fck"; 2075 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 2076 status = "disabled"; 2077 }; 2078 2079 mcasp9: mcasp@2b90000 { 2080 compatible = "ti,am33xx-mcasp-audio"; 2081 reg = <0x0 0x02b90000 0x0 0x2000>, 2082 <0x0 0x02b98000 0x0 0x1000>; 2083 reg-names = "mpu","dat"; 2084 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 2086 interrupt-names = "tx", "rx"; 2087 2088 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 2089 dma-names = "tx", "rx"; 2090 2091 clocks = <&k3_clks 183 1>; 2092 clock-names = "fck"; 2093 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 2094 status = "disabled"; 2095 }; 2096 2097 mcasp10: mcasp@2ba0000 { 2098 compatible = "ti,am33xx-mcasp-audio"; 2099 reg = <0x0 0x02ba0000 0x0 0x2000>, 2100 <0x0 0x02ba8000 0x0 0x1000>; 2101 reg-names = "mpu","dat"; 2102 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 2104 interrupt-names = "tx", "rx"; 2105 2106 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 2107 dma-names = "tx", "rx"; 2108 2109 clocks = <&k3_clks 184 1>; 2110 clock-names = "fck"; 2111 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 2112 status = "disabled"; 2113 }; 2114 2115 mcasp11: mcasp@2bb0000 { 2116 compatible = "ti,am33xx-mcasp-audio"; 2117 reg = <0x0 0x02bb0000 0x0 0x2000>, 2118 <0x0 0x02bb8000 0x0 0x1000>; 2119 reg-names = "mpu","dat"; 2120 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 2122 interrupt-names = "tx", "rx"; 2123 2124 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 2125 dma-names = "tx", "rx"; 2126 2127 clocks = <&k3_clks 185 1>; 2128 clock-names = "fck"; 2129 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 2130 status = "disabled"; 2131 }; 2132 2133 watchdog0: watchdog@2200000 { 2134 compatible = "ti,j7-rti-wdt"; 2135 reg = <0x0 0x2200000 0x0 0x100>; 2136 clocks = <&k3_clks 252 1>; 2137 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 2138 assigned-clocks = <&k3_clks 252 1>; 2139 assigned-clock-parents = <&k3_clks 252 5>; 2140 }; 2141 2142 watchdog1: watchdog@2210000 { 2143 compatible = "ti,j7-rti-wdt"; 2144 reg = <0x0 0x2210000 0x0 0x100>; 2145 clocks = <&k3_clks 253 1>; 2146 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 2147 assigned-clocks = <&k3_clks 253 1>; 2148 assigned-clock-parents = <&k3_clks 253 5>; 2149 }; 2150 2151 main_r5fss0: r5fss@5c00000 { 2152 compatible = "ti,j721e-r5fss"; 2153 ti,cluster-mode = <1>; 2154 #address-cells = <1>; 2155 #size-cells = <1>; 2156 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2157 <0x5d00000 0x00 0x5d00000 0x20000>; 2158 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 2159 2160 main_r5fss0_core0: r5f@5c00000 { 2161 compatible = "ti,j721e-r5f"; 2162 reg = <0x5c00000 0x00008000>, 2163 <0x5c10000 0x00008000>; 2164 reg-names = "atcm", "btcm"; 2165 ti,sci = <&dmsc>; 2166 ti,sci-dev-id = <245>; 2167 ti,sci-proc-ids = <0x06 0xff>; 2168 resets = <&k3_reset 245 1>; 2169 firmware-name = "j7-main-r5f0_0-fw"; 2170 ti,atcm-enable = <1>; 2171 ti,btcm-enable = <1>; 2172 ti,loczrama = <1>; 2173 }; 2174 2175 main_r5fss0_core1: r5f@5d00000 { 2176 compatible = "ti,j721e-r5f"; 2177 reg = <0x5d00000 0x00008000>, 2178 <0x5d10000 0x00008000>; 2179 reg-names = "atcm", "btcm"; 2180 ti,sci = <&dmsc>; 2181 ti,sci-dev-id = <246>; 2182 ti,sci-proc-ids = <0x07 0xff>; 2183 resets = <&k3_reset 246 1>; 2184 firmware-name = "j7-main-r5f0_1-fw"; 2185 ti,atcm-enable = <1>; 2186 ti,btcm-enable = <1>; 2187 ti,loczrama = <1>; 2188 }; 2189 }; 2190 2191 main_r5fss1: r5fss@5e00000 { 2192 compatible = "ti,j721e-r5fss"; 2193 ti,cluster-mode = <1>; 2194 #address-cells = <1>; 2195 #size-cells = <1>; 2196 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2197 <0x5f00000 0x00 0x5f00000 0x20000>; 2198 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 2199 2200 main_r5fss1_core0: r5f@5e00000 { 2201 compatible = "ti,j721e-r5f"; 2202 reg = <0x5e00000 0x00008000>, 2203 <0x5e10000 0x00008000>; 2204 reg-names = "atcm", "btcm"; 2205 ti,sci = <&dmsc>; 2206 ti,sci-dev-id = <247>; 2207 ti,sci-proc-ids = <0x08 0xff>; 2208 resets = <&k3_reset 247 1>; 2209 firmware-name = "j7-main-r5f1_0-fw"; 2210 ti,atcm-enable = <1>; 2211 ti,btcm-enable = <1>; 2212 ti,loczrama = <1>; 2213 }; 2214 2215 main_r5fss1_core1: r5f@5f00000 { 2216 compatible = "ti,j721e-r5f"; 2217 reg = <0x5f00000 0x00008000>, 2218 <0x5f10000 0x00008000>; 2219 reg-names = "atcm", "btcm"; 2220 ti,sci = <&dmsc>; 2221 ti,sci-dev-id = <248>; 2222 ti,sci-proc-ids = <0x09 0xff>; 2223 resets = <&k3_reset 248 1>; 2224 firmware-name = "j7-main-r5f1_1-fw"; 2225 ti,atcm-enable = <1>; 2226 ti,btcm-enable = <1>; 2227 ti,loczrama = <1>; 2228 }; 2229 }; 2230 2231 c66_0: dsp@4d80800000 { 2232 compatible = "ti,j721e-c66-dsp"; 2233 reg = <0x4d 0x80800000 0x00 0x00048000>, 2234 <0x4d 0x80e00000 0x00 0x00008000>, 2235 <0x4d 0x80f00000 0x00 0x00008000>; 2236 reg-names = "l2sram", "l1pram", "l1dram"; 2237 ti,sci = <&dmsc>; 2238 ti,sci-dev-id = <142>; 2239 ti,sci-proc-ids = <0x03 0xff>; 2240 resets = <&k3_reset 142 1>; 2241 firmware-name = "j7-c66_0-fw"; 2242 status = "disabled"; 2243 }; 2244 2245 c66_1: dsp@4d81800000 { 2246 compatible = "ti,j721e-c66-dsp"; 2247 reg = <0x4d 0x81800000 0x00 0x00048000>, 2248 <0x4d 0x81e00000 0x00 0x00008000>, 2249 <0x4d 0x81f00000 0x00 0x00008000>; 2250 reg-names = "l2sram", "l1pram", "l1dram"; 2251 ti,sci = <&dmsc>; 2252 ti,sci-dev-id = <143>; 2253 ti,sci-proc-ids = <0x04 0xff>; 2254 resets = <&k3_reset 143 1>; 2255 firmware-name = "j7-c66_1-fw"; 2256 status = "disabled"; 2257 }; 2258 2259 c71_0: dsp@64800000 { 2260 compatible = "ti,j721e-c71-dsp"; 2261 reg = <0x00 0x64800000 0x00 0x00080000>, 2262 <0x00 0x64e00000 0x00 0x0000c000>; 2263 reg-names = "l2sram", "l1dram"; 2264 ti,sci = <&dmsc>; 2265 ti,sci-dev-id = <15>; 2266 ti,sci-proc-ids = <0x30 0xff>; 2267 resets = <&k3_reset 15 1>; 2268 firmware-name = "j7-c71_0-fw"; 2269 status = "disabled"; 2270 }; 2271 2272 icssg0: icssg@b000000 { 2273 compatible = "ti,j721e-icssg"; 2274 reg = <0x00 0xb000000 0x00 0x80000>; 2275 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 2276 #address-cells = <1>; 2277 #size-cells = <1>; 2278 ranges = <0x0 0x00 0x0b000000 0x100000>; 2279 2280 icssg0_mem: memories@0 { 2281 reg = <0x0 0x2000>, 2282 <0x2000 0x2000>, 2283 <0x10000 0x10000>; 2284 reg-names = "dram0", "dram1", 2285 "shrdram2"; 2286 }; 2287 2288 icssg0_cfg: cfg@26000 { 2289 compatible = "ti,pruss-cfg", "syscon"; 2290 reg = <0x26000 0x200>; 2291 #address-cells = <1>; 2292 #size-cells = <1>; 2293 ranges = <0x0 0x26000 0x2000>; 2294 2295 clocks { 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 2299 icssg0_coreclk_mux: coreclk-mux@3c { 2300 reg = <0x3c>; 2301 #clock-cells = <0>; 2302 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 2303 <&k3_clks 119 1>; /* icssg0_iclk */ 2304 assigned-clocks = <&icssg0_coreclk_mux>; 2305 assigned-clock-parents = <&k3_clks 119 1>; 2306 }; 2307 2308 icssg0_iepclk_mux: iepclk-mux@30 { 2309 reg = <0x30>; 2310 #clock-cells = <0>; 2311 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 2312 <&icssg0_coreclk_mux>; /* core_clk */ 2313 assigned-clocks = <&icssg0_iepclk_mux>; 2314 assigned-clock-parents = <&icssg0_coreclk_mux>; 2315 }; 2316 }; 2317 }; 2318 2319 icssg0_mii_rt: mii-rt@32000 { 2320 compatible = "ti,pruss-mii", "syscon"; 2321 reg = <0x32000 0x100>; 2322 }; 2323 2324 icssg0_mii_g_rt: mii-g-rt@33000 { 2325 compatible = "ti,pruss-mii-g", "syscon"; 2326 reg = <0x33000 0x1000>; 2327 }; 2328 2329 icssg0_intc: interrupt-controller@20000 { 2330 compatible = "ti,icssg-intc"; 2331 reg = <0x20000 0x2000>; 2332 interrupt-controller; 2333 #interrupt-cells = <3>; 2334 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 2340 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2341 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 2342 interrupt-names = "host_intr0", "host_intr1", 2343 "host_intr2", "host_intr3", 2344 "host_intr4", "host_intr5", 2345 "host_intr6", "host_intr7"; 2346 }; 2347 2348 pru0_0: pru@34000 { 2349 compatible = "ti,j721e-pru"; 2350 reg = <0x34000 0x3000>, 2351 <0x22000 0x100>, 2352 <0x22400 0x100>; 2353 reg-names = "iram", "control", "debug"; 2354 firmware-name = "j7-pru0_0-fw"; 2355 }; 2356 2357 rtu0_0: rtu@4000 { 2358 compatible = "ti,j721e-rtu"; 2359 reg = <0x4000 0x2000>, 2360 <0x23000 0x100>, 2361 <0x23400 0x100>; 2362 reg-names = "iram", "control", "debug"; 2363 firmware-name = "j7-rtu0_0-fw"; 2364 }; 2365 2366 tx_pru0_0: txpru@a000 { 2367 compatible = "ti,j721e-tx-pru"; 2368 reg = <0xa000 0x1800>, 2369 <0x25000 0x100>, 2370 <0x25400 0x100>; 2371 reg-names = "iram", "control", "debug"; 2372 firmware-name = "j7-txpru0_0-fw"; 2373 }; 2374 2375 pru0_1: pru@38000 { 2376 compatible = "ti,j721e-pru"; 2377 reg = <0x38000 0x3000>, 2378 <0x24000 0x100>, 2379 <0x24400 0x100>; 2380 reg-names = "iram", "control", "debug"; 2381 firmware-name = "j7-pru0_1-fw"; 2382 }; 2383 2384 rtu0_1: rtu@6000 { 2385 compatible = "ti,j721e-rtu"; 2386 reg = <0x6000 0x2000>, 2387 <0x23800 0x100>, 2388 <0x23c00 0x100>; 2389 reg-names = "iram", "control", "debug"; 2390 firmware-name = "j7-rtu0_1-fw"; 2391 }; 2392 2393 tx_pru0_1: txpru@c000 { 2394 compatible = "ti,j721e-tx-pru"; 2395 reg = <0xc000 0x1800>, 2396 <0x25800 0x100>, 2397 <0x25c00 0x100>; 2398 reg-names = "iram", "control", "debug"; 2399 firmware-name = "j7-txpru0_1-fw"; 2400 }; 2401 2402 icssg0_mdio: mdio@32400 { 2403 compatible = "ti,davinci_mdio"; 2404 reg = <0x32400 0x100>; 2405 clocks = <&k3_clks 119 1>; 2406 clock-names = "fck"; 2407 #address-cells = <1>; 2408 #size-cells = <0>; 2409 bus_freq = <1000000>; 2410 status = "disabled"; 2411 }; 2412 }; 2413 2414 icssg1: icssg@b100000 { 2415 compatible = "ti,j721e-icssg"; 2416 reg = <0x00 0xb100000 0x00 0x80000>; 2417 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 2418 #address-cells = <1>; 2419 #size-cells = <1>; 2420 ranges = <0x0 0x00 0x0b100000 0x100000>; 2421 2422 icssg1_mem: memories@b100000 { 2423 reg = <0x0 0x2000>, 2424 <0x2000 0x2000>, 2425 <0x10000 0x10000>; 2426 reg-names = "dram0", "dram1", 2427 "shrdram2"; 2428 }; 2429 2430 icssg1_cfg: cfg@26000 { 2431 compatible = "ti,pruss-cfg", "syscon"; 2432 reg = <0x26000 0x200>; 2433 #address-cells = <1>; 2434 #size-cells = <1>; 2435 ranges = <0x0 0x26000 0x2000>; 2436 2437 clocks { 2438 #address-cells = <1>; 2439 #size-cells = <0>; 2440 2441 icssg1_coreclk_mux: coreclk-mux@3c { 2442 reg = <0x3c>; 2443 #clock-cells = <0>; 2444 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 2445 <&k3_clks 120 4>; /* icssg1_iclk */ 2446 assigned-clocks = <&icssg1_coreclk_mux>; 2447 assigned-clock-parents = <&k3_clks 120 4>; 2448 }; 2449 2450 icssg1_iepclk_mux: iepclk-mux@30 { 2451 reg = <0x30>; 2452 #clock-cells = <0>; 2453 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 2454 <&icssg1_coreclk_mux>; /* core_clk */ 2455 assigned-clocks = <&icssg1_iepclk_mux>; 2456 assigned-clock-parents = <&icssg1_coreclk_mux>; 2457 }; 2458 }; 2459 }; 2460 2461 icssg1_mii_rt: mii-rt@32000 { 2462 compatible = "ti,pruss-mii", "syscon"; 2463 reg = <0x32000 0x100>; 2464 }; 2465 2466 icssg1_mii_g_rt: mii-g-rt@33000 { 2467 compatible = "ti,pruss-mii-g", "syscon"; 2468 reg = <0x33000 0x1000>; 2469 }; 2470 2471 icssg1_intc: interrupt-controller@20000 { 2472 compatible = "ti,icssg-intc"; 2473 reg = <0x20000 0x2000>; 2474 interrupt-controller; 2475 #interrupt-cells = <3>; 2476 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2484 interrupt-names = "host_intr0", "host_intr1", 2485 "host_intr2", "host_intr3", 2486 "host_intr4", "host_intr5", 2487 "host_intr6", "host_intr7"; 2488 }; 2489 2490 pru1_0: pru@34000 { 2491 compatible = "ti,j721e-pru"; 2492 reg = <0x34000 0x4000>, 2493 <0x22000 0x100>, 2494 <0x22400 0x100>; 2495 reg-names = "iram", "control", "debug"; 2496 firmware-name = "j7-pru1_0-fw"; 2497 }; 2498 2499 rtu1_0: rtu@4000 { 2500 compatible = "ti,j721e-rtu"; 2501 reg = <0x4000 0x2000>, 2502 <0x23000 0x100>, 2503 <0x23400 0x100>; 2504 reg-names = "iram", "control", "debug"; 2505 firmware-name = "j7-rtu1_0-fw"; 2506 }; 2507 2508 tx_pru1_0: txpru@a000 { 2509 compatible = "ti,j721e-tx-pru"; 2510 reg = <0xa000 0x1800>, 2511 <0x25000 0x100>, 2512 <0x25400 0x100>; 2513 reg-names = "iram", "control", "debug"; 2514 firmware-name = "j7-txpru1_0-fw"; 2515 }; 2516 2517 pru1_1: pru@38000 { 2518 compatible = "ti,j721e-pru"; 2519 reg = <0x38000 0x4000>, 2520 <0x24000 0x100>, 2521 <0x24400 0x100>; 2522 reg-names = "iram", "control", "debug"; 2523 firmware-name = "j7-pru1_1-fw"; 2524 }; 2525 2526 rtu1_1: rtu@6000 { 2527 compatible = "ti,j721e-rtu"; 2528 reg = <0x6000 0x2000>, 2529 <0x23800 0x100>, 2530 <0x23c00 0x100>; 2531 reg-names = "iram", "control", "debug"; 2532 firmware-name = "j7-rtu1_1-fw"; 2533 }; 2534 2535 tx_pru1_1: txpru@c000 { 2536 compatible = "ti,j721e-tx-pru"; 2537 reg = <0xc000 0x1800>, 2538 <0x25800 0x100>, 2539 <0x25c00 0x100>; 2540 reg-names = "iram", "control", "debug"; 2541 firmware-name = "j7-txpru1_1-fw"; 2542 }; 2543 2544 icssg1_mdio: mdio@32400 { 2545 compatible = "ti,davinci_mdio"; 2546 reg = <0x32400 0x100>; 2547 clocks = <&k3_clks 120 4>; 2548 clock-names = "fck"; 2549 #address-cells = <1>; 2550 #size-cells = <0>; 2551 bus_freq = <1000000>; 2552 status = "disabled"; 2553 }; 2554 }; 2555 2556 main_mcan0: can@2701000 { 2557 compatible = "bosch,m_can"; 2558 reg = <0x00 0x02701000 0x00 0x200>, 2559 <0x00 0x02708000 0x00 0x8000>; 2560 reg-names = "m_can", "message_ram"; 2561 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2562 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2563 clock-names = "hclk", "cclk"; 2564 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2566 interrupt-names = "int0", "int1"; 2567 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2568 status = "disabled"; 2569 }; 2570 2571 main_mcan1: can@2711000 { 2572 compatible = "bosch,m_can"; 2573 reg = <0x00 0x02711000 0x00 0x200>, 2574 <0x00 0x02718000 0x00 0x8000>; 2575 reg-names = "m_can", "message_ram"; 2576 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2577 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2578 clock-names = "hclk", "cclk"; 2579 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2581 interrupt-names = "int0", "int1"; 2582 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2583 status = "disabled"; 2584 }; 2585 2586 main_mcan2: can@2721000 { 2587 compatible = "bosch,m_can"; 2588 reg = <0x00 0x02721000 0x00 0x200>, 2589 <0x00 0x02728000 0x00 0x8000>; 2590 reg-names = "m_can", "message_ram"; 2591 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2592 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2593 clock-names = "hclk", "cclk"; 2594 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2596 interrupt-names = "int0", "int1"; 2597 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2598 status = "disabled"; 2599 }; 2600 2601 main_mcan3: can@2731000 { 2602 compatible = "bosch,m_can"; 2603 reg = <0x00 0x02731000 0x00 0x200>, 2604 <0x00 0x02738000 0x00 0x8000>; 2605 reg-names = "m_can", "message_ram"; 2606 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2607 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2608 clock-names = "hclk", "cclk"; 2609 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2611 interrupt-names = "int0", "int1"; 2612 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2613 status = "disabled"; 2614 }; 2615 2616 main_mcan4: can@2741000 { 2617 compatible = "bosch,m_can"; 2618 reg = <0x00 0x02741000 0x00 0x200>, 2619 <0x00 0x02748000 0x00 0x8000>; 2620 reg-names = "m_can", "message_ram"; 2621 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2622 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2623 clock-names = "hclk", "cclk"; 2624 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2625 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2626 interrupt-names = "int0", "int1"; 2627 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2628 status = "disabled"; 2629 }; 2630 2631 main_mcan5: can@2751000 { 2632 compatible = "bosch,m_can"; 2633 reg = <0x00 0x02751000 0x00 0x200>, 2634 <0x00 0x02758000 0x00 0x8000>; 2635 reg-names = "m_can", "message_ram"; 2636 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2637 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2638 clock-names = "hclk", "cclk"; 2639 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2640 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2641 interrupt-names = "int0", "int1"; 2642 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2643 status = "disabled"; 2644 }; 2645 2646 main_mcan6: can@2761000 { 2647 compatible = "bosch,m_can"; 2648 reg = <0x00 0x02761000 0x00 0x200>, 2649 <0x00 0x02768000 0x00 0x8000>; 2650 reg-names = "m_can", "message_ram"; 2651 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2652 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2653 clock-names = "hclk", "cclk"; 2654 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2655 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2656 interrupt-names = "int0", "int1"; 2657 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2658 status = "disabled"; 2659 }; 2660 2661 main_mcan7: can@2771000 { 2662 compatible = "bosch,m_can"; 2663 reg = <0x00 0x02771000 0x00 0x200>, 2664 <0x00 0x02778000 0x00 0x8000>; 2665 reg-names = "m_can", "message_ram"; 2666 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2667 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2668 clock-names = "hclk", "cclk"; 2669 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2671 interrupt-names = "int0", "int1"; 2672 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2673 status = "disabled"; 2674 }; 2675 2676 main_mcan8: can@2781000 { 2677 compatible = "bosch,m_can"; 2678 reg = <0x00 0x02781000 0x00 0x200>, 2679 <0x00 0x02788000 0x00 0x8000>; 2680 reg-names = "m_can", "message_ram"; 2681 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2682 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2683 clock-names = "hclk", "cclk"; 2684 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2685 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2686 interrupt-names = "int0", "int1"; 2687 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2688 status = "disabled"; 2689 }; 2690 2691 main_mcan9: can@2791000 { 2692 compatible = "bosch,m_can"; 2693 reg = <0x00 0x02791000 0x00 0x200>, 2694 <0x00 0x02798000 0x00 0x8000>; 2695 reg-names = "m_can", "message_ram"; 2696 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2697 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2698 clock-names = "hclk", "cclk"; 2699 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2701 interrupt-names = "int0", "int1"; 2702 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2703 status = "disabled"; 2704 }; 2705 2706 main_mcan10: can@27a1000 { 2707 compatible = "bosch,m_can"; 2708 reg = <0x00 0x027a1000 0x00 0x200>, 2709 <0x00 0x027a8000 0x00 0x8000>; 2710 reg-names = "m_can", "message_ram"; 2711 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2712 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2713 clock-names = "hclk", "cclk"; 2714 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2716 interrupt-names = "int0", "int1"; 2717 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2718 status = "disabled"; 2719 }; 2720 2721 main_mcan11: can@27b1000 { 2722 compatible = "bosch,m_can"; 2723 reg = <0x00 0x027b1000 0x00 0x200>, 2724 <0x00 0x027b8000 0x00 0x8000>; 2725 reg-names = "m_can", "message_ram"; 2726 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2727 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2728 clock-names = "hclk", "cclk"; 2729 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2731 interrupt-names = "int0", "int1"; 2732 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2733 status = "disabled"; 2734 }; 2735 2736 main_mcan12: can@27c1000 { 2737 compatible = "bosch,m_can"; 2738 reg = <0x00 0x027c1000 0x00 0x200>, 2739 <0x00 0x027c8000 0x00 0x8000>; 2740 reg-names = "m_can", "message_ram"; 2741 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2742 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2743 clock-names = "hclk", "cclk"; 2744 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2745 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2746 interrupt-names = "int0", "int1"; 2747 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2748 status = "disabled"; 2749 }; 2750 2751 main_mcan13: can@27d1000 { 2752 compatible = "bosch,m_can"; 2753 reg = <0x00 0x027d1000 0x00 0x200>, 2754 <0x00 0x027d8000 0x00 0x8000>; 2755 reg-names = "m_can", "message_ram"; 2756 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2757 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2758 clock-names = "hclk", "cclk"; 2759 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2761 interrupt-names = "int0", "int1"; 2762 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2763 status = "disabled"; 2764 }; 2765 2766 main_spi0: spi@2100000 { 2767 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2768 reg = <0x00 0x02100000 0x00 0x400>; 2769 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2770 #address-cells = <1>; 2771 #size-cells = <0>; 2772 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2773 clocks = <&k3_clks 266 1>; 2774 status = "disabled"; 2775 }; 2776 2777 main_spi1: spi@2110000 { 2778 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2779 reg = <0x00 0x02110000 0x00 0x400>; 2780 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2781 #address-cells = <1>; 2782 #size-cells = <0>; 2783 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2784 clocks = <&k3_clks 267 1>; 2785 status = "disabled"; 2786 }; 2787 2788 main_spi2: spi@2120000 { 2789 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2790 reg = <0x00 0x02120000 0x00 0x400>; 2791 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2792 #address-cells = <1>; 2793 #size-cells = <0>; 2794 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2795 clocks = <&k3_clks 268 1>; 2796 status = "disabled"; 2797 }; 2798 2799 main_spi3: spi@2130000 { 2800 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2801 reg = <0x00 0x02130000 0x00 0x400>; 2802 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2806 clocks = <&k3_clks 269 1>; 2807 status = "disabled"; 2808 }; 2809 2810 main_spi4: spi@2140000 { 2811 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2812 reg = <0x00 0x02140000 0x00 0x400>; 2813 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2814 #address-cells = <1>; 2815 #size-cells = <0>; 2816 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2817 clocks = <&k3_clks 270 1>; 2818 status = "disabled"; 2819 }; 2820 2821 main_spi5: spi@2150000 { 2822 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2823 reg = <0x00 0x02150000 0x00 0x400>; 2824 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2825 #address-cells = <1>; 2826 #size-cells = <0>; 2827 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2828 clocks = <&k3_clks 271 1>; 2829 status = "disabled"; 2830 }; 2831 2832 main_spi6: spi@2160000 { 2833 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2834 reg = <0x00 0x02160000 0x00 0x400>; 2835 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2839 clocks = <&k3_clks 272 1>; 2840 status = "disabled"; 2841 }; 2842 2843 main_spi7: spi@2170000 { 2844 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2845 reg = <0x00 0x02170000 0x00 0x400>; 2846 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2847 #address-cells = <1>; 2848 #size-cells = <0>; 2849 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2850 clocks = <&k3_clks 273 1>; 2851 status = "disabled"; 2852 }; 2853 2854 main_esm: esm@700000 { 2855 compatible = "ti,j721e-esm"; 2856 reg = <0x0 0x700000 0x0 0x1000>; 2857 bootph-pre-ram; 2858 ti,esm-pins = <344>, <345>; 2859 }; 2860}; 2861