1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with 4 * J721E board. 5 * 6 * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM 7 * 8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 */ 10 11/dts-v1/; 12/plugin/; 13 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/net/ti-dp83867.h> 16 17#include "k3-pinctrl.h" 18 19&{/} { 20 aliases { 21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; 24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; 25 }; 26}; 27 28&cpsw0 { 29 status = "okay"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&rgmii1_default_pins 32 &rgmii2_default_pins 33 &rgmii3_default_pins 34 &rgmii4_default_pins>; 35}; 36 37&cpsw0_port1 { 38 status = "okay"; 39 phy-handle = <&cpsw9g_phy12>; 40 phy-mode = "rgmii-rxid"; 41 mac-address = [00 00 00 00 00 00]; 42 phys = <&cpsw0_phy_gmii_sel 1>; 43}; 44 45&cpsw0_port2 { 46 status = "okay"; 47 phy-handle = <&cpsw9g_phy15>; 48 phy-mode = "rgmii-rxid"; 49 mac-address = [00 00 00 00 00 00]; 50 phys = <&cpsw0_phy_gmii_sel 2>; 51}; 52 53&cpsw0_port3 { 54 status = "okay"; 55 phy-handle = <&cpsw9g_phy0>; 56 phy-mode = "rgmii-rxid"; 57 mac-address = [00 00 00 00 00 00]; 58 phys = <&cpsw0_phy_gmii_sel 3>; 59}; 60 61&cpsw0_port4 { 62 status = "okay"; 63 phy-handle = <&cpsw9g_phy3>; 64 phy-mode = "rgmii-rxid"; 65 mac-address = [00 00 00 00 00 00]; 66 phys = <&cpsw0_phy_gmii_sel 4>; 67}; 68 69&cpsw9g_mdio { 70 status = "okay"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&mdio0_default_pins>; 73 bus_freq = <1000000>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpsw9g_phy0: ethernet-phy@0 { 78 reg = <0>; 79 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 80 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 81 ti,min-output-impedance; 82 }; 83 cpsw9g_phy3: ethernet-phy@3 { 84 reg = <3>; 85 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 86 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 87 ti,min-output-impedance; 88 }; 89 cpsw9g_phy12: ethernet-phy@12 { 90 reg = <12>; 91 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 92 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 93 ti,min-output-impedance; 94 }; 95 cpsw9g_phy15: ethernet-phy@15 { 96 reg = <15>; 97 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 98 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 99 ti,min-output-impedance; 100 }; 101}; 102 103&exp1 { 104 p15-hog { 105 /* P15 - EXP_MUX2 */ 106 gpio-hog; 107 gpios = <13 GPIO_ACTIVE_HIGH>; 108 output-high; 109 line-name = "EXP_MUX2"; 110 }; 111 112 p16-hog { 113 /* P16 - EXP_MUX3 */ 114 gpio-hog; 115 gpios = <14 GPIO_ACTIVE_HIGH>; 116 output-high; 117 line-name = "EXP_MUX3"; 118 }; 119}; 120 121&main_pmx0 { 122 mdio0_default_pins: mdio0-default-pins { 123 pinctrl-single,pins = < 124 J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ 125 J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ 126 >; 127 }; 128 129 rgmii1_default_pins: rgmii1-default-pins { 130 pinctrl-single,pins = < 131 J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */ 132 J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */ 133 J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */ 134 J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */ 135 J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */ 136 J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */ 137 J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */ 138 J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */ 139 J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */ 140 J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */ 141 J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */ 142 J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */ 143 >; 144 }; 145 146 rgmii2_default_pins: rgmii2-default-pins { 147 pinctrl-single,pins = < 148 J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */ 149 J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */ 150 J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */ 151 J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */ 152 J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */ 153 J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 154 J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */ 155 J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */ 156 J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */ 157 J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */ 158 J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */ 159 J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 160 >; 161 }; 162 163 rgmii3_default_pins: rgmii3-default-pins { 164 pinctrl-single,pins = < 165 J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */ 166 J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */ 167 J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */ 168 J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */ 169 J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */ 170 J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */ 171 J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */ 172 J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */ 173 J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */ 174 J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */ 175 J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */ 176 J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */ 177 >; 178 }; 179 180 rgmii4_default_pins: rgmii4-default-pins { 181 pinctrl-single,pins = < 182 J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */ 183 J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */ 184 J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */ 185 J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */ 186 J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */ 187 J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */ 188 J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */ 189 J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */ 190 J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */ 191 J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */ 192 J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */ 193 J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */ 194 >; 195 }; 196}; 197