1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Product Link: https://www.ti.com/tool/J721EXCPXEVM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e-som-p0.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14#include <dt-bindings/phy/phy-cadence.h> 15 16/ { 17 compatible = "ti,j721e-evm", "ti,j721e"; 18 model = "Texas Instruments J721e EVM"; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial1 = &mcu_uart0; 23 serial2 = &main_uart0; 24 serial3 = &main_uart1; 25 serial4 = &main_uart2; 26 serial6 = &main_uart4; 27 ethernet0 = &cpsw_port1; 28 mmc0 = &main_sdhci0; 29 mmc1 = &main_sdhci1; 30 }; 31 32 chosen { 33 stdout-path = "serial2:115200n8"; 34 }; 35 36 gpio_keys: gpio-keys { 37 compatible = "gpio-keys"; 38 autorepeat; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; 41 42 sw10: switch-10 { 43 label = "GPIO Key USER1"; 44 linux,code = <BTN_0>; 45 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 46 }; 47 48 sw11: switch-11 { 49 label = "GPIO Key USER2"; 50 linux,code = <BTN_1>; 51 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 52 }; 53 }; 54 55 evm_12v0: fixedregulator-evm12v0 { 56 /* main supply */ 57 compatible = "regulator-fixed"; 58 regulator-name = "evm_12v0"; 59 regulator-min-microvolt = <12000000>; 60 regulator-max-microvolt = <12000000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 vsys_3v3: fixedregulator-vsys3v3 { 66 /* Output of LMS140 */ 67 compatible = "regulator-fixed"; 68 regulator-name = "vsys_3v3"; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 vin-supply = <&evm_12v0>; 72 regulator-always-on; 73 regulator-boot-on; 74 }; 75 76 vsys_5v0: fixedregulator-vsys5v0 { 77 /* Output of LM5140 */ 78 compatible = "regulator-fixed"; 79 regulator-name = "vsys_5v0"; 80 regulator-min-microvolt = <5000000>; 81 regulator-max-microvolt = <5000000>; 82 vin-supply = <&evm_12v0>; 83 regulator-always-on; 84 regulator-boot-on; 85 }; 86 87 vdd_mmc1: fixedregulator-sd { 88 compatible = "regulator-fixed"; 89 regulator-name = "vdd_mmc1"; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 regulator-boot-on; 93 enable-active-high; 94 vin-supply = <&vsys_3v3>; 95 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 96 }; 97 98 vdd_sd_dv_alt: gpio-regulator-TLV71033 { 99 compatible = "regulator-gpio"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 102 regulator-name = "tlv71033"; 103 regulator-min-microvolt = <1800000>; 104 regulator-max-microvolt = <3300000>; 105 regulator-boot-on; 106 vin-supply = <&vsys_5v0>; 107 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 108 states = <1800000 0x0>, 109 <3300000 0x1>; 110 }; 111 112 sound0: sound-0 { 113 compatible = "ti,j721e-cpb-audio"; 114 model = "j721e-cpb"; 115 116 ti,cpb-mcasp = <&mcasp10>; 117 ti,cpb-codec = <&pcm3168a_1>; 118 119 clocks = <&k3_clks 184 1>, 120 <&k3_clks 184 2>, <&k3_clks 184 4>, 121 <&k3_clks 157 371>, 122 <&k3_clks 157 400>, <&k3_clks 157 401>; 123 clock-names = "cpb-mcasp-auxclk", 124 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 125 "cpb-codec-scki", 126 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 127 }; 128 129 transceiver1: can-phy0 { 130 compatible = "ti,tcan1043"; 131 #phy-cells = <0>; 132 max-bitrate = <5000000>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 135 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; 136 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 137 }; 138 139 transceiver2: can-phy1 { 140 compatible = "ti,tcan1042"; 141 #phy-cells = <0>; 142 max-bitrate = <5000000>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 145 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 146 }; 147 148 transceiver3: can-phy2 { 149 compatible = "ti,tcan1043"; 150 #phy-cells = <0>; 151 max-bitrate = <5000000>; 152 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; 153 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 154 }; 155 156 transceiver4: can-phy3 { 157 compatible = "ti,tcan1042"; 158 #phy-cells = <0>; 159 max-bitrate = <5000000>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&main_mcan2_gpio_pins_default>; 162 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; 163 }; 164 165 dp_pwr_3v3: regulator-dp-pwr { 166 compatible = "regulator-fixed"; 167 regulator-name = "dp-pwr"; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ 171 enable-active-high; 172 }; 173 174 dp0: connector { 175 compatible = "dp-connector"; 176 label = "DP0"; 177 type = "full-size"; 178 dp-pwr-supply = <&dp_pwr_3v3>; 179 180 port { 181 dp_connector_in: endpoint { 182 remote-endpoint = <&dp0_out>; 183 }; 184 }; 185 }; 186}; 187 188&main_pmx0 { 189 main_uart0_pins_default: main-uart0-default-pins { 190 pinctrl-single,pins = < 191 J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ 192 J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ 193 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 194 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 195 >; 196 }; 197 198 main_uart1_pins_default: main-uart1-default-pins { 199 pinctrl-single,pins = < 200 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 201 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 202 >; 203 }; 204 205 main_uart2_pins_default: main-uart2-default-pins { 206 pinctrl-single,pins = < 207 J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ 208 J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ 209 >; 210 }; 211 212 main_uart4_pins_default: main-uart4-default-pins { 213 pinctrl-single,pins = < 214 J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ 215 J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ 216 >; 217 }; 218 219 sw10_button_pins_default: sw10-button-default-pins { 220 pinctrl-single,pins = < 221 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 222 >; 223 }; 224 225 main_mmc1_pins_default: main-mmc1-default-pins { 226 pinctrl-single,pins = < 227 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 228 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 229 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 230 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 231 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 232 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 233 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 234 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 235 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 236 >; 237 }; 238 239 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 240 pinctrl-single,pins = < 241 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 242 >; 243 }; 244 245 main_usbss0_pins_default: main-usbss0-default-pins { 246 pinctrl-single,pins = < 247 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 248 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 249 >; 250 }; 251 252 main_usbss1_pins_default: main-usbss1-default-pins { 253 pinctrl-single,pins = < 254 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 255 >; 256 }; 257 258 dp0_pins_default: dp0-default-pins { 259 pinctrl-single,pins = < 260 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 261 >; 262 }; 263 264 main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { 265 pinctrl-single,pins = < 266 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 267 >; 268 }; 269 270 main_i2c0_pins_default: main-i2c0-default-pins { 271 pinctrl-single,pins = < 272 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 273 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 274 >; 275 }; 276 277 main_i2c1_pins_default: main-i2c1-default-pins { 278 pinctrl-single,pins = < 279 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 280 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 281 >; 282 }; 283 284 main_i2c3_pins_default: main-i2c3-default-pins { 285 pinctrl-single,pins = < 286 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 287 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 288 >; 289 }; 290 291 main_i2c6_pins_default: main-i2c6-default-pins { 292 pinctrl-single,pins = < 293 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 294 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 295 >; 296 }; 297 298 mcasp10_pins_default: mcasp10-default-pins { 299 pinctrl-single,pins = < 300 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 301 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 302 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 303 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 304 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 305 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 306 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 307 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 308 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 309 >; 310 }; 311 312 audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { 313 pinctrl-single,pins = < 314 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 315 >; 316 }; 317 318 main_mcan0_pins_default: main-mcan0-default-pins { 319 pinctrl-single,pins = < 320 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 321 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 322 >; 323 }; 324 325 main_mcan2_pins_default: main-mcan2-default-pins { 326 pinctrl-single,pins = < 327 J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ 328 J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ 329 >; 330 }; 331 332 main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { 333 pinctrl-single,pins = < 334 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 335 >; 336 }; 337}; 338 339&wkup_pmx0 { 340 wkup_uart0_pins_default: wkup-uart0-default-pins { 341 pinctrl-single,pins = < 342 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 343 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 344 >; 345 }; 346 347 mcu_uart0_pins_default: mcu-uart0-default-pins { 348 pinctrl-single,pins = < 349 J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ 350 J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ 351 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 352 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 353 >; 354 }; 355 356 sw11_button_pins_default: sw11-button-default-pins { 357 pinctrl-single,pins = < 358 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 359 >; 360 }; 361 362 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 363 pinctrl-single,pins = < 364 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 365 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 366 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 367 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 368 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 369 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 370 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 371 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 372 >; 373 }; 374 375 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 376 pinctrl-single,pins = < 377 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 378 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 379 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 380 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 381 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 382 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 383 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 384 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 385 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 386 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 387 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 388 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 389 >; 390 }; 391 392 mcu_mdio_pins_default: mcu-mdio1-default-pins { 393 pinctrl-single,pins = < 394 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 395 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 396 >; 397 }; 398 399 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 400 pinctrl-single,pins = < 401 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 402 J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 403 >; 404 }; 405 406 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 407 pinctrl-single,pins = < 408 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ 409 J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ 410 >; 411 }; 412 413 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 414 pinctrl-single,pins = < 415 J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ 416 J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ 417 >; 418 }; 419 420 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 421 pinctrl-single,pins = < 422 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ 423 >; 424 }; 425 426 wkup_gpio_pins_default: wkup-gpio-default-pins { 427 pinctrl-single,pins = < 428 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ 429 >; 430 }; 431}; 432 433&wkup_uart0 { 434 /* Wakeup UART is used by System firmware */ 435 status = "reserved"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&wkup_uart0_pins_default>; 438}; 439 440&mcu_uart0 { 441 status = "okay"; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&mcu_uart0_pins_default>; 444}; 445 446&main_uart0 { 447 status = "okay"; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&main_uart0_pins_default>; 450 /* Shared with ATF on this platform */ 451 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 452}; 453 454&main_uart1 { 455 status = "okay"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&main_uart1_pins_default>; 458}; 459 460&main_uart2 { 461 status = "okay"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&main_uart2_pins_default>; 464}; 465 466&main_uart4 { 467 status = "okay"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&main_uart4_pins_default>; 470}; 471 472&wkup_gpio0 { 473 status = "okay"; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&wkup_gpio_pins_default>; 476}; 477 478&main_gpio0 { 479 status = "okay"; 480}; 481 482&main_gpio1 { 483 status = "okay"; 484}; 485 486&main_sdhci0 { 487 /* eMMC */ 488 status = "okay"; 489 non-removable; 490 ti,driver-strength-ohm = <50>; 491 disable-wp; 492}; 493 494&main_sdhci1 { 495 /* SD/MMC */ 496 status = "okay"; 497 vmmc-supply = <&vdd_mmc1>; 498 vqmmc-supply = <&vdd_sd_dv_alt>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&main_mmc1_pins_default>; 501 ti,driver-strength-ohm = <50>; 502 disable-wp; 503}; 504 505&usb_serdes_mux { 506 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 507}; 508 509&serdes_ln_ctrl { 510 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 511 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 512 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 513 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 514 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 515 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 516}; 517 518&serdes_wiz3 { 519 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 520 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 521}; 522 523&serdes3 { 524 serdes3_usb_link: phy@0 { 525 reg = <0>; 526 cdns,num-lanes = <2>; 527 #phy-cells = <0>; 528 cdns,phy-type = <PHY_TYPE_USB3>; 529 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 530 }; 531}; 532 533&usbss0 { 534 pinctrl-names = "default"; 535 pinctrl-0 = <&main_usbss0_pins_default>; 536 ti,vbus-divider; 537}; 538 539&usb0 { 540 dr_mode = "otg"; 541 maximum-speed = "super-speed"; 542 phys = <&serdes3_usb_link>; 543 phy-names = "cdns3,usb3-phy"; 544}; 545 546&usbss1 { 547 pinctrl-names = "default"; 548 pinctrl-0 = <&main_usbss1_pins_default>; 549 ti,usb2-only; 550}; 551 552&usb1 { 553 dr_mode = "host"; 554 maximum-speed = "high-speed"; 555}; 556 557&ospi1 { 558 pinctrl-names = "default"; 559 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 560 561 flash@0 { 562 compatible = "jedec,spi-nor"; 563 reg = <0x0>; 564 spi-tx-bus-width = <1>; 565 spi-rx-bus-width = <4>; 566 spi-max-frequency = <40000000>; 567 cdns,tshsl-ns = <60>; 568 cdns,tsd2d-ns = <60>; 569 cdns,tchsh-ns = <60>; 570 cdns,tslch-ns = <60>; 571 cdns,read-delay = <2>; 572 573 partitions { 574 compatible = "fixed-partitions"; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 578 partition@0 { 579 label = "qspi.tiboot3"; 580 reg = <0x0 0x80000>; 581 }; 582 583 partition@80000 { 584 label = "qspi.tispl"; 585 reg = <0x80000 0x200000>; 586 }; 587 588 partition@280000 { 589 label = "qspi.u-boot"; 590 reg = <0x280000 0x400000>; 591 }; 592 593 partition@680000 { 594 label = "qspi.env"; 595 reg = <0x680000 0x20000>; 596 }; 597 598 partition@6a0000 { 599 label = "qspi.env.backup"; 600 reg = <0x6a0000 0x20000>; 601 }; 602 603 partition@6c0000 { 604 label = "qspi.sysfw"; 605 reg = <0x6c0000 0x100000>; 606 }; 607 608 partition@800000 { 609 label = "qspi.rootfs"; 610 reg = <0x800000 0x37c0000>; 611 }; 612 613 partition@3fe0000 { 614 label = "qspi.phypattern"; 615 reg = <0x3fe0000 0x20000>; 616 }; 617 }; 618 }; 619}; 620 621&tscadc0 { 622 status = "okay"; 623 adc { 624 ti,adc-channels = <0 1 2 3 4 5 6 7>; 625 }; 626}; 627 628&tscadc1 { 629 status = "okay"; 630 adc { 631 ti,adc-channels = <0 1 2 3 4 5 6 7>; 632 }; 633}; 634 635&main_i2c0 { 636 status = "okay"; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&main_i2c0_pins_default>; 639 clock-frequency = <400000>; 640 641 exp1: gpio@20 { 642 compatible = "ti,tca6416"; 643 reg = <0x20>; 644 gpio-controller; 645 #gpio-cells = <2>; 646 }; 647 648 exp2: gpio@22 { 649 compatible = "ti,tca6424"; 650 reg = <0x22>; 651 gpio-controller; 652 #gpio-cells = <2>; 653 654 p09-hog { 655 /* P11 - MCASP/TRACE_MUX_S0 */ 656 gpio-hog; 657 gpios = <9 GPIO_ACTIVE_HIGH>; 658 output-low; 659 line-name = "MCASP/TRACE_MUX_S0"; 660 }; 661 662 p10-hog { 663 /* P12 - MCASP/TRACE_MUX_S1 */ 664 gpio-hog; 665 gpios = <10 GPIO_ACTIVE_HIGH>; 666 output-high; 667 line-name = "MCASP/TRACE_MUX_S1"; 668 }; 669 }; 670}; 671 672&main_i2c1 { 673 status = "okay"; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&main_i2c1_pins_default>; 676 clock-frequency = <400000>; 677 678 exp4: gpio@20 { 679 compatible = "ti,tca6408"; 680 reg = <0x20>; 681 gpio-controller; 682 #gpio-cells = <2>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 685 interrupt-parent = <&main_gpio1>; 686 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 }; 690}; 691 692&k3_clks { 693 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 694 pinctrl-names = "default"; 695 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 696}; 697 698&main_i2c3 { 699 status = "okay"; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&main_i2c3_pins_default>; 702 clock-frequency = <400000>; 703 704 exp3: gpio@20 { 705 compatible = "ti,tca6408"; 706 reg = <0x20>; 707 gpio-controller; 708 #gpio-cells = <2>; 709 }; 710 711 pcm3168a_1: audio-codec@44 { 712 compatible = "ti,pcm3168a"; 713 reg = <0x44>; 714 715 #sound-dai-cells = <1>; 716 717 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 718 719 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 720 clocks = <&k3_clks 157 371>; 721 clock-names = "scki"; 722 723 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 724 assigned-clocks = <&k3_clks 157 371>; 725 assigned-clock-parents = <&k3_clks 157 400>; 726 assigned-clock-rates = <24576000>; /* for 48KHz */ 727 728 VDD1-supply = <&vsys_3v3>; 729 VDD2-supply = <&vsys_3v3>; 730 VCCAD1-supply = <&vsys_5v0>; 731 VCCAD2-supply = <&vsys_5v0>; 732 VCCDA1-supply = <&vsys_5v0>; 733 VCCDA2-supply = <&vsys_5v0>; 734 }; 735}; 736 737&main_i2c6 { 738 status = "okay"; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&main_i2c6_pins_default>; 741 clock-frequency = <400000>; 742 743 exp5: gpio@20 { 744 compatible = "ti,tca6408"; 745 reg = <0x20>; 746 gpio-controller; 747 #gpio-cells = <2>; 748 }; 749}; 750 751&mcu_cpsw { 752 pinctrl-names = "default"; 753 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 754}; 755 756&davinci_mdio { 757 phy0: ethernet-phy@0 { 758 reg = <0>; 759 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 760 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 761 }; 762}; 763 764&cpsw_port1 { 765 phy-mode = "rgmii-rxid"; 766 phy-handle = <&phy0>; 767}; 768 769&dss { 770 /* 771 * These clock assignments are chosen to enable the following outputs: 772 * 773 * VP0 - DisplayPort SST 774 * VP1 - DPI0 775 * VP2 - DSI 776 * VP3 - DPI1 777 */ 778 779 assigned-clocks = <&k3_clks 152 1>, 780 <&k3_clks 152 4>, 781 <&k3_clks 152 9>, 782 <&k3_clks 152 13>; 783 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 784 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 785 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 786 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 787}; 788 789&dss_ports { 790 port { 791 dpi0_out: endpoint { 792 remote-endpoint = <&dp0_in>; 793 }; 794 }; 795}; 796 797&dp0_ports { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 port@0 { 802 reg = <0>; 803 dp0_in: endpoint { 804 remote-endpoint = <&dpi0_out>; 805 }; 806 }; 807 808 port@4 { 809 reg = <4>; 810 dp0_out: endpoint { 811 remote-endpoint = <&dp_connector_in>; 812 }; 813 }; 814}; 815 816&mcasp10 { 817 status = "okay"; 818 #sound-dai-cells = <0>; 819 820 pinctrl-names = "default"; 821 pinctrl-0 = <&mcasp10_pins_default>; 822 823 op-mode = <0>; /* MCASP_IIS_MODE */ 824 tdm-slots = <2>; 825 auxclk-fs-ratio = <256>; 826 827 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 828 1 1 1 1 829 2 2 2 0 830 >; 831 tx-num-evt = <0>; 832 rx-num-evt = <0>; 833}; 834 835&cmn_refclk1 { 836 clock-frequency = <100000000>; 837}; 838 839&wiz0_pll1_refclk { 840 assigned-clocks = <&wiz0_pll1_refclk>; 841 assigned-clock-parents = <&cmn_refclk1>; 842}; 843 844&wiz0_refclk_dig { 845 assigned-clocks = <&wiz0_refclk_dig>; 846 assigned-clock-parents = <&cmn_refclk1>; 847}; 848 849&wiz1_pll1_refclk { 850 assigned-clocks = <&wiz1_pll1_refclk>; 851 assigned-clock-parents = <&cmn_refclk1>; 852}; 853 854&wiz1_refclk_dig { 855 assigned-clocks = <&wiz1_refclk_dig>; 856 assigned-clock-parents = <&cmn_refclk1>; 857}; 858 859&wiz2_pll1_refclk { 860 assigned-clocks = <&wiz2_pll1_refclk>; 861 assigned-clock-parents = <&cmn_refclk1>; 862}; 863 864&wiz2_refclk_dig { 865 assigned-clocks = <&wiz2_refclk_dig>; 866 assigned-clock-parents = <&cmn_refclk1>; 867}; 868 869&serdes0 { 870 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; 871 assigned-clock-parents = <&wiz0_pll1_refclk>; 872 873 serdes0_pcie_link: phy@0 { 874 reg = <0>; 875 cdns,num-lanes = <1>; 876 #phy-cells = <0>; 877 cdns,phy-type = <PHY_TYPE_PCIE>; 878 resets = <&serdes_wiz0 1>; 879 }; 880}; 881 882&serdes1 { 883 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; 884 assigned-clock-parents = <&wiz1_pll1_refclk>; 885 886 serdes1_pcie_link: phy@0 { 887 reg = <0>; 888 cdns,num-lanes = <2>; 889 #phy-cells = <0>; 890 cdns,phy-type = <PHY_TYPE_PCIE>; 891 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 892 }; 893}; 894 895&serdes2 { 896 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; 897 assigned-clock-parents = <&wiz2_pll1_refclk>; 898 899 serdes2_pcie_link: phy@0 { 900 reg = <0>; 901 cdns,num-lanes = <2>; 902 #phy-cells = <0>; 903 cdns,phy-type = <PHY_TYPE_PCIE>; 904 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 905 }; 906}; 907 908&serdes4 { 909 torrent_phy_dp: phy@0 { 910 reg = <0>; 911 resets = <&serdes_wiz4 1>; 912 cdns,phy-type = <PHY_TYPE_DP>; 913 cdns,num-lanes = <4>; 914 cdns,max-bit-rate = <5400>; 915 #phy-cells = <0>; 916 }; 917}; 918 919&mhdp { 920 phys = <&torrent_phy_dp>; 921 phy-names = "dpphy"; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&dp0_pins_default>; 924}; 925 926&pcie0_rc { 927 status = "okay"; 928 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 929 phys = <&serdes0_pcie_link>; 930 phy-names = "pcie-phy"; 931 num-lanes = <1>; 932}; 933 934&pcie1_rc { 935 status = "okay"; 936 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 937 phys = <&serdes1_pcie_link>; 938 phy-names = "pcie-phy"; 939 num-lanes = <2>; 940}; 941 942&pcie2_rc { 943 status = "okay"; 944 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 945 phys = <&serdes2_pcie_link>; 946 phy-names = "pcie-phy"; 947 num-lanes = <2>; 948}; 949 950&mcu_mcan0 { 951 status = "okay"; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&mcu_mcan0_pins_default>; 954 phys = <&transceiver1>; 955}; 956 957&mcu_mcan1 { 958 status = "okay"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&mcu_mcan1_pins_default>; 961 phys = <&transceiver2>; 962}; 963 964&main_mcan0 { 965 status = "okay"; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&main_mcan0_pins_default>; 968 phys = <&transceiver3>; 969}; 970 971&main_mcan2 { 972 status = "okay"; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&main_mcan2_pins_default>; 975 phys = <&transceiver4>; 976}; 977