1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9 10#include "k3-j7200.dtsi" 11 12/ { 13 memory@80000000 { 14 device_type = "memory"; 15 /* 4G RAM */ 16 reg = <0x00 0x80000000 0x00 0x80000000>, 17 <0x08 0x80000000 0x00 0x80000000>; 18 }; 19 20 reserved_memory: reserved-memory { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 secure_ddr: optee@9e800000 { 26 reg = <0x00 0x9e800000 0x00 0x01800000>; 27 alignment = <0x1000>; 28 no-map; 29 }; 30 31 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 32 compatible = "shared-dma-pool"; 33 reg = <0x00 0xa0000000 0x00 0x100000>; 34 no-map; 35 }; 36 37 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 38 compatible = "shared-dma-pool"; 39 reg = <0x00 0xa0100000 0x00 0xf00000>; 40 no-map; 41 }; 42 43 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 44 compatible = "shared-dma-pool"; 45 reg = <0x00 0xa1000000 0x00 0x100000>; 46 no-map; 47 }; 48 49 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 50 compatible = "shared-dma-pool"; 51 reg = <0x00 0xa1100000 0x00 0xf00000>; 52 no-map; 53 }; 54 55 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa2000000 0x00 0x100000>; 58 no-map; 59 }; 60 61 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa2100000 0x00 0xf00000>; 64 no-map; 65 }; 66 67 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa3000000 0x00 0x100000>; 70 no-map; 71 }; 72 73 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa3100000 0x00 0xf00000>; 76 no-map; 77 }; 78 79 rtos_ipc_memory_region: ipc-memories@a4000000 { 80 reg = <0x00 0xa4000000 0x00 0x00800000>; 81 alignment = <0x1000>; 82 no-map; 83 }; 84 }; 85 86 mux0: mux-controller { 87 compatible = "gpio-mux"; 88 #mux-state-cells = <1>; 89 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; 90 }; 91 92 mux1: mux-controller { 93 compatible = "gpio-mux"; 94 #mux-state-cells = <1>; 95 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; 96 }; 97 98 transceiver0: can-phy0 { 99 /* standby pin has been grounded by default */ 100 compatible = "ti,tcan1042"; 101 #phy-cells = <0>; 102 max-bitrate = <5000000>; 103 }; 104}; 105 106&wkup_pmx0 { 107 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { 108 pinctrl-single,pins = < 109 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 110 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 111 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 112 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 113 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 114 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 115 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 116 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 117 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 118 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 119 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 120 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 121 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 122 >; 123 }; 124 125 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 126 pinctrl-single,pins = < 127 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 128 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 129 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 130 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 131 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 132 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 133 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 134 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 135 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 136 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 137 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 138 >; 139 }; 140}; 141 142&wkup_pmx2 { 143 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 144 pinctrl-single,pins = < 145 J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ 146 J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ 147 >; 148 }; 149}; 150 151&wkup_pmx3 { 152 pmic_irq_pins_default: pmic-irq-default-pins { 153 pinctrl-single,pins = < 154 J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */ 155 >; 156 }; 157}; 158 159&main_pmx0 { 160 main_i2c0_pins_default: main-i2c0-default-pins { 161 pinctrl-single,pins = < 162 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ 163 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ 164 >; 165 }; 166 167 main_mcan0_pins_default: main-mcan0-default-pins { 168 pinctrl-single,pins = < 169 J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */ 170 J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */ 171 >; 172 }; 173}; 174 175&hbmc { 176 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 177 * appropriate node based on board detection 178 */ 179 status = "disabled"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 182 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 183 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 184 185 flash@0,0 { 186 compatible = "cypress,hyperflash", "cfi-flash"; 187 reg = <0x00 0x00 0x4000000>; 188 189 partitions { 190 compatible = "fixed-partitions"; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 194 partition@0 { 195 label = "hbmc.tiboot3"; 196 reg = <0x0 0x100000>; 197 }; 198 199 partition@100000 { 200 label = "hbmc.tispl"; 201 reg = <0x100000 0x200000>; 202 }; 203 204 partition@300000 { 205 label = "hbmc.u-boot"; 206 reg = <0x300000 0x400000>; 207 }; 208 209 partition@700000 { 210 label = "hbmc.env"; 211 reg = <0x700000 0x40000>; 212 }; 213 214 partition@800000 { 215 label = "hbmc.rootfs"; 216 reg = <0x800000 0x3800000>; 217 }; 218 }; 219 }; 220}; 221 222&mailbox0_cluster0 { 223 status = "okay"; 224 interrupts = <436>; 225 226 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 227 ti,mbox-rx = <0 0 0>; 228 ti,mbox-tx = <1 0 0>; 229 }; 230 231 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 232 ti,mbox-rx = <2 0 0>; 233 ti,mbox-tx = <3 0 0>; 234 }; 235}; 236 237&mailbox0_cluster1 { 238 status = "okay"; 239 interrupts = <432>; 240 241 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 242 ti,mbox-rx = <0 0 0>; 243 ti,mbox-tx = <1 0 0>; 244 }; 245 246 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 247 ti,mbox-rx = <2 0 0>; 248 ti,mbox-tx = <3 0 0>; 249 }; 250}; 251 252&mcu_r5fss0_core0 { 253 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 254 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 255 <&mcu_r5fss0_core0_memory_region>; 256}; 257 258&mcu_r5fss0_core1 { 259 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 260 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 261 <&mcu_r5fss0_core1_memory_region>; 262}; 263 264&main_r5fss0_core0 { 265 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 266 memory-region = <&main_r5fss0_core0_dma_memory_region>, 267 <&main_r5fss0_core0_memory_region>; 268}; 269 270&main_r5fss0_core1 { 271 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 272 memory-region = <&main_r5fss0_core1_dma_memory_region>, 273 <&main_r5fss0_core1_memory_region>; 274}; 275 276&main_i2c0 { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&main_i2c0_pins_default>; 279 clock-frequency = <400000>; 280 281 exp_som: gpio@21 { 282 compatible = "ti,tca6408"; 283 reg = <0x21>; 284 gpio-controller; 285 #gpio-cells = <2>; 286 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 287 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 288 "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", 289 "GPIO_LIN_EN", "CAN_STB"; 290 }; 291}; 292 293&wkup_i2c0 { 294 status = "okay"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&wkup_i2c0_pins_default>; 297 clock-frequency = <400000>; 298 299 eeprom@50 { 300 compatible = "atmel,24c256"; 301 reg = <0x50>; 302 }; 303 304 tps659414: pmic@48 { 305 compatible = "ti,tps6594-q1"; 306 reg = <0x48>; 307 system-power-controller; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pmic_irq_pins_default>; 310 interrupt-parent = <&wkup_gpio0>; 311 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 312 gpio-controller; 313 #gpio-cells = <2>; 314 ti,primary-pmic; 315 buck1-supply = <&vsys_3v3>; 316 buck2-supply = <&vsys_3v3>; 317 buck3-supply = <&vsys_3v3>; 318 buck4-supply = <&vsys_3v3>; 319 buck5-supply = <&vsys_3v3>; 320 ldo1-supply = <&vsys_3v3>; 321 ldo2-supply = <&vsys_3v3>; 322 ldo3-supply = <&vsys_3v3>; 323 ldo4-supply = <&vsys_3v3>; 324 325 regulators { 326 bucka1: buck1 { 327 regulator-name = "vda_mcu_1v8"; 328 regulator-min-microvolt = <1800000>; 329 regulator-max-microvolt = <1800000>; 330 regulator-boot-on; 331 regulator-always-on; 332 }; 333 334 bucka2: buck2 { 335 regulator-name = "vdd_mcuio_1v8"; 336 regulator-min-microvolt = <1800000>; 337 regulator-max-microvolt = <1800000>; 338 regulator-boot-on; 339 regulator-always-on; 340 }; 341 342 bucka3: buck3 { 343 regulator-name = "vdd_mcu_0v85"; 344 regulator-min-microvolt = <850000>; 345 regulator-max-microvolt = <850000>; 346 regulator-boot-on; 347 regulator-always-on; 348 }; 349 350 bucka4: buck4 { 351 regulator-name = "vdd_ddr_1v1"; 352 regulator-min-microvolt = <1100000>; 353 regulator-max-microvolt = <1100000>; 354 regulator-boot-on; 355 regulator-always-on; 356 }; 357 358 bucka5: buck5 { 359 regulator-name = "vdd_phyio_1v8"; 360 regulator-min-microvolt = <1800000>; 361 regulator-max-microvolt = <1800000>; 362 regulator-boot-on; 363 regulator-always-on; 364 }; 365 366 ldoa1: ldo1 { 367 regulator-name = "vdd1_lpddr4_1v8"; 368 regulator-min-microvolt = <1800000>; 369 regulator-max-microvolt = <1800000>; 370 regulator-boot-on; 371 regulator-always-on; 372 }; 373 374 ldoa2: ldo2 { 375 regulator-name = "vda_dll_0v8"; 376 regulator-min-microvolt = <800000>; 377 regulator-max-microvolt = <800000>; 378 regulator-boot-on; 379 regulator-always-on; 380 }; 381 382 ldoa3: ldo3 { 383 regulator-name = "vdd_wk_0v8"; 384 regulator-min-microvolt = <800000>; 385 regulator-max-microvolt = <800000>; 386 regulator-boot-on; 387 regulator-always-on; 388 }; 389 390 ldoa4: ldo4 { 391 regulator-name = "vda_pll_1v8"; 392 regulator-min-microvolt = <1800000>; 393 regulator-max-microvolt = <1800000>; 394 regulator-boot-on; 395 regulator-always-on; 396 }; 397 }; 398 }; 399 400 lp876441: pmic@4c { 401 compatible = "ti,lp8764-q1"; 402 reg = <0x4c>; 403 system-power-controller; 404 interrupt-parent = <&wkup_gpio0>; 405 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 406 gpio-controller; 407 #gpio-cells = <2>; 408 buck1-supply = <&vsys_3v3>; 409 buck2-supply = <&vsys_3v3>; 410 buck3-supply = <&vsys_3v3>; 411 buck4-supply = <&vsys_3v3>; 412 413 regulators: regulators { 414 buckb1: buck1 { 415 regulator-name = "vdd_cpu_avs"; 416 regulator-min-microvolt = <600000>; 417 regulator-max-microvolt = <900000>; 418 regulator-always-on; 419 regulator-boot-on; 420 bootph-pre-ram; 421 }; 422 423 buckb2: buck2 { 424 regulator-name = "vdd_ram_0v85"; 425 regulator-min-microvolt = <850000>; 426 regulator-max-microvolt = <850000>; 427 regulator-boot-on; 428 regulator-always-on; 429 }; 430 431 buckb3: buck3 { 432 regulator-name = "vdd_core_0v85"; 433 regulator-min-microvolt = <850000>; 434 regulator-max-microvolt = <850000>; 435 regulator-boot-on; 436 regulator-always-on; 437 }; 438 439 buckb4: buck4 { 440 regulator-name = "vdd_io_1v8"; 441 regulator-min-microvolt = <1800000>; 442 regulator-max-microvolt = <1800000>; 443 regulator-boot-on; 444 regulator-always-on; 445 }; 446 }; 447 }; 448}; 449 450&ospi0 { 451 status = "okay"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 454 455 flash@0 { 456 compatible = "jedec,spi-nor"; 457 reg = <0x0>; 458 spi-tx-bus-width = <8>; 459 spi-rx-bus-width = <8>; 460 spi-max-frequency = <25000000>; 461 cdns,tshsl-ns = <60>; 462 cdns,tsd2d-ns = <60>; 463 cdns,tchsh-ns = <60>; 464 cdns,tslch-ns = <60>; 465 cdns,read-delay = <4>; 466 467 partitions { 468 compatible = "fixed-partitions"; 469 #address-cells = <1>; 470 #size-cells = <1>; 471 472 partition@0 { 473 label = "ospi.tiboot3"; 474 reg = <0x0 0x100000>; 475 }; 476 477 partition@100000 { 478 label = "ospi.tispl"; 479 reg = <0x100000 0x200000>; 480 }; 481 482 partition@300000 { 483 label = "ospi.u-boot"; 484 reg = <0x300000 0x400000>; 485 }; 486 487 partition@700000 { 488 label = "ospi.env"; 489 reg = <0x700000 0x40000>; 490 }; 491 492 partition@740000 { 493 label = "ospi.env.backup"; 494 reg = <0x740000 0x40000>; 495 }; 496 497 partition@800000 { 498 label = "ospi.rootfs"; 499 reg = <0x800000 0x37c0000>; 500 }; 501 502 partition@3fc0000 { 503 label = "ospi.phypattern"; 504 reg = <0x3fc0000 0x40000>; 505 }; 506 }; 507 }; 508}; 509 510&main_mcan0 { 511 status = "okay"; 512 pinctrl-0 = <&main_mcan0_pins_default>; 513 pinctrl-names = "default"; 514 phys = <&transceiver0>; 515}; 516