1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9 10#include "k3-j7200.dtsi" 11 12/ { 13 memory@80000000 { 14 device_type = "memory"; 15 bootph-all; 16 /* 4G RAM */ 17 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 18 <0x00000008 0x80000000 0x00000000 0x80000000>; 19 }; 20 21 reserved_memory: reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 secure_ddr: optee@9e800000 { 27 reg = <0x00 0x9e800000 0x00 0x01800000>; 28 alignment = <0x1000>; 29 no-map; 30 }; 31 32 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 33 compatible = "shared-dma-pool"; 34 reg = <0x00 0xa0000000 0x00 0x100000>; 35 no-map; 36 }; 37 38 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 39 compatible = "shared-dma-pool"; 40 reg = <0x00 0xa0100000 0x00 0xf00000>; 41 no-map; 42 }; 43 44 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 45 compatible = "shared-dma-pool"; 46 reg = <0x00 0xa1000000 0x00 0x100000>; 47 no-map; 48 }; 49 50 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 51 compatible = "shared-dma-pool"; 52 reg = <0x00 0xa1100000 0x00 0xf00000>; 53 no-map; 54 }; 55 56 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 57 compatible = "shared-dma-pool"; 58 reg = <0x00 0xa2000000 0x00 0x100000>; 59 no-map; 60 }; 61 62 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 63 compatible = "shared-dma-pool"; 64 reg = <0x00 0xa2100000 0x00 0xf00000>; 65 no-map; 66 }; 67 68 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 69 compatible = "shared-dma-pool"; 70 reg = <0x00 0xa3000000 0x00 0x100000>; 71 no-map; 72 }; 73 74 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 75 compatible = "shared-dma-pool"; 76 reg = <0x00 0xa3100000 0x00 0xf00000>; 77 no-map; 78 }; 79 80 rtos_ipc_memory_region: ipc-memories@a4000000 { 81 reg = <0x00 0xa4000000 0x00 0x00800000>; 82 alignment = <0x1000>; 83 no-map; 84 }; 85 }; 86 87 mux0: mux-controller { 88 compatible = "gpio-mux"; 89 #mux-state-cells = <1>; 90 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; 91 }; 92 93 mux1: mux-controller { 94 compatible = "gpio-mux"; 95 #mux-state-cells = <1>; 96 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; 97 }; 98 99 transceiver0: can-phy0 { 100 /* standby pin has been grounded by default */ 101 compatible = "ti,tcan1042"; 102 #phy-cells = <0>; 103 max-bitrate = <5000000>; 104 }; 105}; 106 107&wkup_pmx0 { 108 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { 109 pinctrl-single,pins = < 110 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 111 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 112 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 113 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 114 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 115 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 116 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 117 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 118 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 119 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 120 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 121 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 122 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 123 >; 124 }; 125 126 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 127 pinctrl-single,pins = < 128 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 129 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 130 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 131 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 132 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 133 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 134 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 135 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 136 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 137 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 138 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 139 >; 140 }; 141}; 142 143&wkup_pmx2 { 144 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 145 pinctrl-single,pins = < 146 J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ 147 J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ 148 >; 149 }; 150}; 151 152&wkup_pmx3 { 153 pmic_irq_pins_default: pmic-irq-default-pins { 154 pinctrl-single,pins = < 155 J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */ 156 >; 157 }; 158}; 159 160&main_pmx0 { 161 main_i2c0_pins_default: main-i2c0-default-pins { 162 pinctrl-single,pins = < 163 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ 164 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ 165 >; 166 }; 167 168 main_mcan0_pins_default: main-mcan0-default-pins { 169 pinctrl-single,pins = < 170 J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */ 171 J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */ 172 >; 173 }; 174}; 175 176&hbmc { 177 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 178 * appropriate node based on board detection 179 */ 180 status = "disabled"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 183 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 184 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 185 186 flash@0,0 { 187 compatible = "cypress,hyperflash", "cfi-flash"; 188 reg = <0x00 0x00 0x4000000>; 189 190 partitions { 191 compatible = "fixed-partitions"; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 195 partition@0 { 196 label = "hbmc.tiboot3"; 197 reg = <0x0 0x100000>; 198 }; 199 200 partition@100000 { 201 label = "hbmc.tispl"; 202 reg = <0x100000 0x200000>; 203 }; 204 205 partition@300000 { 206 label = "hbmc.u-boot"; 207 reg = <0x300000 0x400000>; 208 }; 209 210 partition@700000 { 211 label = "hbmc.env"; 212 reg = <0x700000 0x40000>; 213 }; 214 215 partition@800000 { 216 label = "hbmc.rootfs"; 217 reg = <0x800000 0x3800000>; 218 }; 219 }; 220 }; 221}; 222 223&mailbox0_cluster0 { 224 status = "okay"; 225 interrupts = <436>; 226 227 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 228 ti,mbox-rx = <0 0 0>; 229 ti,mbox-tx = <1 0 0>; 230 }; 231 232 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 233 ti,mbox-rx = <2 0 0>; 234 ti,mbox-tx = <3 0 0>; 235 }; 236}; 237 238&mailbox0_cluster1 { 239 status = "okay"; 240 interrupts = <432>; 241 242 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 243 ti,mbox-rx = <0 0 0>; 244 ti,mbox-tx = <1 0 0>; 245 }; 246 247 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 248 ti,mbox-rx = <2 0 0>; 249 ti,mbox-tx = <3 0 0>; 250 }; 251}; 252 253&mcu_r5fss0_core0 { 254 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 255 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 256 <&mcu_r5fss0_core0_memory_region>; 257}; 258 259&mcu_r5fss0_core1 { 260 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 261 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 262 <&mcu_r5fss0_core1_memory_region>; 263}; 264 265&main_r5fss0_core0 { 266 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 267 memory-region = <&main_r5fss0_core0_dma_memory_region>, 268 <&main_r5fss0_core0_memory_region>; 269}; 270 271&main_r5fss0_core1 { 272 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 273 memory-region = <&main_r5fss0_core1_dma_memory_region>, 274 <&main_r5fss0_core1_memory_region>; 275}; 276 277&main_i2c0 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&main_i2c0_pins_default>; 280 clock-frequency = <400000>; 281 282 exp_som: gpio@21 { 283 compatible = "ti,tca6408"; 284 reg = <0x21>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 288 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 289 "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", 290 "GPIO_LIN_EN", "CAN_STB"; 291 }; 292}; 293 294&wkup_i2c0 { 295 status = "okay"; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&wkup_i2c0_pins_default>; 298 clock-frequency = <400000>; 299 300 eeprom@50 { 301 compatible = "atmel,24c256"; 302 reg = <0x50>; 303 }; 304 305 tps659414: pmic@48 { 306 compatible = "ti,tps6594-q1"; 307 reg = <0x48>; 308 system-power-controller; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pmic_irq_pins_default>; 311 interrupt-parent = <&wkup_gpio0>; 312 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 ti,primary-pmic; 316 buck1-supply = <&vsys_3v3>; 317 buck2-supply = <&vsys_3v3>; 318 buck3-supply = <&vsys_3v3>; 319 buck4-supply = <&vsys_3v3>; 320 buck5-supply = <&vsys_3v3>; 321 ldo1-supply = <&vsys_3v3>; 322 ldo2-supply = <&vsys_3v3>; 323 ldo3-supply = <&vsys_3v3>; 324 ldo4-supply = <&vsys_3v3>; 325 326 regulators { 327 bucka1: buck1 { 328 regulator-name = "vda_mcu_1v8"; 329 regulator-min-microvolt = <1800000>; 330 regulator-max-microvolt = <1800000>; 331 regulator-boot-on; 332 regulator-always-on; 333 }; 334 335 bucka2: buck2 { 336 regulator-name = "vdd_mcuio_1v8"; 337 regulator-min-microvolt = <1800000>; 338 regulator-max-microvolt = <1800000>; 339 regulator-boot-on; 340 regulator-always-on; 341 }; 342 343 bucka3: buck3 { 344 regulator-name = "vdd_mcu_0v85"; 345 regulator-min-microvolt = <850000>; 346 regulator-max-microvolt = <850000>; 347 regulator-boot-on; 348 regulator-always-on; 349 }; 350 351 bucka4: buck4 { 352 regulator-name = "vdd_ddr_1v1"; 353 regulator-min-microvolt = <1100000>; 354 regulator-max-microvolt = <1100000>; 355 regulator-boot-on; 356 regulator-always-on; 357 }; 358 359 bucka5: buck5 { 360 regulator-name = "vdd_phyio_1v8"; 361 regulator-min-microvolt = <1800000>; 362 regulator-max-microvolt = <1800000>; 363 regulator-boot-on; 364 regulator-always-on; 365 }; 366 367 ldoa1: ldo1 { 368 regulator-name = "vdd1_lpddr4_1v8"; 369 regulator-min-microvolt = <1800000>; 370 regulator-max-microvolt = <1800000>; 371 regulator-boot-on; 372 regulator-always-on; 373 }; 374 375 ldoa2: ldo2 { 376 regulator-name = "vda_dll_0v8"; 377 regulator-min-microvolt = <800000>; 378 regulator-max-microvolt = <800000>; 379 regulator-boot-on; 380 regulator-always-on; 381 }; 382 383 ldoa3: ldo3 { 384 regulator-name = "vdd_wk_0v8"; 385 regulator-min-microvolt = <800000>; 386 regulator-max-microvolt = <800000>; 387 regulator-boot-on; 388 regulator-always-on; 389 }; 390 391 ldoa4: ldo4 { 392 regulator-name = "vda_pll_1v8"; 393 regulator-min-microvolt = <1800000>; 394 regulator-max-microvolt = <1800000>; 395 regulator-boot-on; 396 regulator-always-on; 397 }; 398 }; 399 }; 400 401 lp876441: pmic@4c { 402 compatible = "ti,lp8764-q1"; 403 reg = <0x4c>; 404 system-power-controller; 405 interrupt-parent = <&wkup_gpio0>; 406 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 buck1-supply = <&vsys_3v3>; 410 buck2-supply = <&vsys_3v3>; 411 buck3-supply = <&vsys_3v3>; 412 buck4-supply = <&vsys_3v3>; 413 414 regulators: regulators { 415 buckb1: buck1 { 416 regulator-name = "vdd_cpu_avs"; 417 regulator-min-microvolt = <600000>; 418 regulator-max-microvolt = <900000>; 419 regulator-always-on; 420 regulator-boot-on; 421 bootph-pre-ram; 422 }; 423 424 buckb2: buck2 { 425 regulator-name = "vdd_ram_0v85"; 426 regulator-min-microvolt = <850000>; 427 regulator-max-microvolt = <850000>; 428 regulator-boot-on; 429 regulator-always-on; 430 }; 431 432 buckb3: buck3 { 433 regulator-name = "vdd_core_0v85"; 434 regulator-min-microvolt = <850000>; 435 regulator-max-microvolt = <850000>; 436 regulator-boot-on; 437 regulator-always-on; 438 }; 439 440 buckb4: buck4 { 441 regulator-name = "vdd_io_1v8"; 442 regulator-min-microvolt = <1800000>; 443 regulator-max-microvolt = <1800000>; 444 regulator-boot-on; 445 regulator-always-on; 446 }; 447 }; 448 }; 449}; 450 451&ospi0 { 452 status = "okay"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 455 456 flash@0 { 457 compatible = "jedec,spi-nor"; 458 reg = <0x0>; 459 spi-tx-bus-width = <8>; 460 spi-rx-bus-width = <8>; 461 spi-max-frequency = <25000000>; 462 cdns,tshsl-ns = <60>; 463 cdns,tsd2d-ns = <60>; 464 cdns,tchsh-ns = <60>; 465 cdns,tslch-ns = <60>; 466 cdns,read-delay = <4>; 467 468 partitions { 469 compatible = "fixed-partitions"; 470 #address-cells = <1>; 471 #size-cells = <1>; 472 473 partition@0 { 474 label = "ospi.tiboot3"; 475 reg = <0x0 0x100000>; 476 }; 477 478 partition@100000 { 479 label = "ospi.tispl"; 480 reg = <0x100000 0x200000>; 481 }; 482 483 partition@300000 { 484 label = "ospi.u-boot"; 485 reg = <0x300000 0x400000>; 486 }; 487 488 partition@700000 { 489 label = "ospi.env"; 490 reg = <0x700000 0x40000>; 491 }; 492 493 partition@740000 { 494 label = "ospi.env.backup"; 495 reg = <0x740000 0x40000>; 496 }; 497 498 partition@800000 { 499 label = "ospi.rootfs"; 500 reg = <0x800000 0x37c0000>; 501 }; 502 503 partition@3fc0000 { 504 label = "ospi.phypattern"; 505 reg = <0x3fc0000 0x40000>; 506 }; 507 }; 508 }; 509}; 510 511&main_mcan0 { 512 status = "okay"; 513 pinctrl-0 = <&main_mcan0_pins_default>; 514 pinctrl-names = "default"; 515 phys = <&transceiver0>; 516}; 517