1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200.dtsi" 9 10/ { 11 memory@80000000 { 12 device_type = "memory"; 13 /* 4G RAM */ 14 reg = <0x00 0x80000000 0x00 0x80000000>, 15 <0x08 0x80000000 0x00 0x80000000>; 16 }; 17 18 reserved_memory: reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 secure_ddr: optee@9e800000 { 24 reg = <0x00 0x9e800000 0x00 0x01800000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 30 compatible = "shared-dma-pool"; 31 reg = <0x00 0xa0000000 0x00 0x100000>; 32 no-map; 33 }; 34 35 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 36 compatible = "shared-dma-pool"; 37 reg = <0x00 0xa0100000 0x00 0xf00000>; 38 no-map; 39 }; 40 41 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 42 compatible = "shared-dma-pool"; 43 reg = <0x00 0xa1000000 0x00 0x100000>; 44 no-map; 45 }; 46 47 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 48 compatible = "shared-dma-pool"; 49 reg = <0x00 0xa1100000 0x00 0xf00000>; 50 no-map; 51 }; 52 53 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa2000000 0x00 0x100000>; 56 no-map; 57 }; 58 59 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa2100000 0x00 0xf00000>; 62 no-map; 63 }; 64 65 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa3000000 0x00 0x100000>; 68 no-map; 69 }; 70 71 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa3100000 0x00 0xf00000>; 74 no-map; 75 }; 76 77 rtos_ipc_memory_region: ipc-memories@a4000000 { 78 reg = <0x00 0xa4000000 0x00 0x00800000>; 79 alignment = <0x1000>; 80 no-map; 81 }; 82 }; 83}; 84 85&wkup_pmx0 { 86 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { 87 pinctrl-single,pins = < 88 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 89 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 90 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 91 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 92 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 93 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 94 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 95 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 96 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 97 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 98 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 99 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 100 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 101 >; 102 }; 103}; 104 105&main_pmx0 { 106 main_i2c0_pins_default: main-i2c0-pins-default { 107 pinctrl-single,pins = < 108 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ 109 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ 110 >; 111 }; 112}; 113 114&hbmc { 115 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 116 * appropriate node based on board detection 117 */ 118 status = "disabled"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 121 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 122 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 123 124 flash@0,0 { 125 compatible = "cypress,hyperflash", "cfi-flash"; 126 reg = <0x00 0x00 0x4000000>; 127 }; 128}; 129 130&mailbox0_cluster0 { 131 interrupts = <436>; 132 133 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 134 ti,mbox-rx = <0 0 0>; 135 ti,mbox-tx = <1 0 0>; 136 }; 137 138 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 139 ti,mbox-rx = <2 0 0>; 140 ti,mbox-tx = <3 0 0>; 141 }; 142}; 143 144&mailbox0_cluster1 { 145 interrupts = <432>; 146 147 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 148 ti,mbox-rx = <0 0 0>; 149 ti,mbox-tx = <1 0 0>; 150 }; 151 152 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 153 ti,mbox-rx = <2 0 0>; 154 ti,mbox-tx = <3 0 0>; 155 }; 156}; 157 158&mailbox0_cluster2 { 159 status = "disabled"; 160}; 161 162&mailbox0_cluster3 { 163 status = "disabled"; 164}; 165 166&mailbox0_cluster4 { 167 status = "disabled"; 168}; 169 170&mailbox0_cluster5 { 171 status = "disabled"; 172}; 173 174&mailbox0_cluster6 { 175 status = "disabled"; 176}; 177 178&mailbox0_cluster7 { 179 status = "disabled"; 180}; 181 182&mailbox0_cluster8 { 183 status = "disabled"; 184}; 185 186&mailbox0_cluster9 { 187 status = "disabled"; 188}; 189 190&mailbox0_cluster10 { 191 status = "disabled"; 192}; 193 194&mailbox0_cluster11 { 195 status = "disabled"; 196}; 197 198&mcu_r5fss0_core0 { 199 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 200 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 201 <&mcu_r5fss0_core0_memory_region>; 202}; 203 204&mcu_r5fss0_core1 { 205 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 206 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 207 <&mcu_r5fss0_core1_memory_region>; 208}; 209 210&main_r5fss0_core0 { 211 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 212 memory-region = <&main_r5fss0_core0_dma_memory_region>, 213 <&main_r5fss0_core0_memory_region>; 214}; 215 216&main_r5fss0_core1 { 217 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 218 memory-region = <&main_r5fss0_core1_dma_memory_region>, 219 <&main_r5fss0_core1_memory_region>; 220}; 221 222&main_i2c0 { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&main_i2c0_pins_default>; 225 clock-frequency = <400000>; 226 227 exp_som: gpio@21 { 228 compatible = "ti,tca6408"; 229 reg = <0x21>; 230 gpio-controller; 231 #gpio-cells = <2>; 232 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 233 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 234 "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", 235 "GPIO_LIN_EN", "CAN_STB"; 236 }; 237}; 238